CN112763078B - Signal reading circuit and method of uncooled infrared focal plane array detector - Google Patents
Signal reading circuit and method of uncooled infrared focal plane array detector Download PDFInfo
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Abstract
The application relates to a signal reading circuit and a signal reading method of an uncooled infrared focal plane array detector. The readout circuit comprises a row selection module and a non-refrigeration infrared focal plane array; the uncooled infrared focal plane array comprises a plurality of rows of infrared sensitive pixels and a plurality of rows of dummy resistors; the row selection module gates the infrared sensitive pixels and the dummy resistors in each row one by one according to a set sequence in the front-end time period of the current frame, and controls the preset target dummy resistor row to be in a conducting state in the frame redundancy time period of the current frame; wherein the target dummy resistance line is at least one of the plurality of rows of dummy resistances. In the frame redundancy period of the reading circuit, the equivalent load of the detector array is unchanged, the working voltage ripple caused by load fluctuation is reduced, and the stability of the working voltage is improved, so that the stability of the output signal of the reading circuit is improved.
Description
Technical Field
The application relates to the technical field of uncooled infrared focal plane array detectors, in particular to a signal reading circuit and a signal reading method of an uncooled infrared focal plane array detector.
Background
The uncooled infrared focal plane array reading circuit can extract, integrate, sample/hold and output weak electric signals generated by the uncooled detector array in sequence after analog-to-digital conversion. The uncooled infrared focal plane array reading circuit is a digital-analog mixed circuit system, generally, an analog circuit is a signal channel of the infrared focal plane array, and the performance of the analog circuit is related to the quality of an output signal and is a core part of the reading circuit; the digital control section provides timing, status configuration, etc. for the normal operation of the readout circuit. The detector array is composed of a plurality of imaging units capable of normally sensing radiation and a plurality of dummy resistor rows incapable of sensing radiation. The column-level integrated uncooled infrared focal plane array reading circuit usually adopts the working mode of row-by-row integration and column-by-column reading. The stability of the working voltage of the uncooled infrared focal plane array reading circuit directly influences the output result of the reading circuit.
Disclosure of Invention
The application provides a signal read-out circuit and a method of an uncooled infrared focal plane array detector to improve the stability of the working voltage of the signal read-out circuit of the uncooled infrared focal plane array detector, and improve the stability of the output signal of the read-out circuit. The specific technical scheme is as follows:
in a first aspect of the embodiments of the present application, a signal readout circuit of an uncooled infrared focal plane array detector is provided, which includes a central timing control module, a row selection module, and an uncooled infrared focal plane array;
the uncooled infrared focal plane array comprises a plurality of rows of infrared sensitive pixels and a plurality of rows of dummy resistors;
the central time sequence control module is electrically connected with the row selection module and is used for providing time sequence signals for the row selection module;
the row selection module comprises a row selection signal generation circuit, a row selection module and a row selection module, wherein the row selection signal generation circuit is used for gating the infrared sensitive pixels and the dummy resistors in each row one by one according to a set sequence in the front-end time period of the current frame according to the time sequence signal and controlling the preset target dummy resistor row to be in a conducting state in the frame redundancy time period of the current frame according to the time sequence signal; wherein the target dummy resistance behavior is at least one of the plurality of rows of dummy resistances.
Further, the row selection module includes a second flip-flop, and the second flip-flop can receive a frame redundancy trigger signal and a frame redundancy end signal, and can control a preset target dummy resistance row to enter a conducting state when receiving the frame redundancy trigger signal, and disconnect the preset target dummy resistance row when receiving the frame redundancy end signal.
Further, the row selection module comprises a second row selection signal generation circuit, and the second row selection signal generation circuit comprises the second flip-flop and a plurality of third flip-flops connected in sequence; each third trigger is connected with one row of the dummy resistors, so that each third trigger controls one row of the dummy resistors; the clock signal input end and the reset signal input end of each third trigger are respectively connected with the clock signal end and the reset signal end, and the data signal input end of each third trigger is connected with the positive signal output end of the previous third trigger from the third trigger positioned at the second position; the data signal end of the second trigger is connected with the high-level signal end, the clock signal input end of the second trigger is used for receiving a frame redundancy trigger signal, and the reset signal end of the second trigger is used for receiving a frame redundancy end signal; and the positive signal output end of the second trigger and the positive signal output end of the third trigger positioned at the tail end are respectively connected to different input ends of the OR gate.
Furthermore, the row selection module comprises a first row selection signal generation circuit, the first row selection signal generation circuit comprises a first signal generation module and a plurality of first triggers which are connected in sequence, and each first trigger is connected with one row of the infrared sensitive pixels, so that each first trigger controls one row of the infrared sensitive pixels; the data signal input end, the clock signal input end and the reset signal input end of the first signal generation module are respectively connected with the high-level signal end, the clock signal end and the reset signal end, and the output end of the first signal generation module is connected with the data signal input end of the first trigger positioned at the head end; except the first trigger at the tail end, the positive signal output end of each of the other first triggers is connected with the data signal input end of the next first trigger, and the clock signal input end and the reset signal input end of each first trigger are respectively connected with the clock signal end and the reset signal end.
Further, the first signal generating module comprises a fourth flip-flop and a fifth flip-flop;
a data signal input end, a clock signal input end and a reset signal input end of the fourth trigger are respectively connected with a high-level signal end, a clock signal end and a reset signal end, and a positive signal output end of the fourth trigger is connected with a data signal input end of the fifth trigger;
a clock signal input end and a reset signal input end of the fifth trigger are respectively connected with a clock signal end and a reset signal end; the negative signal output end of the fifth trigger and the positive signal output end of the fourth trigger are respectively connected with different input ends of an AND gate, and the output end of the AND gate is connected with the data signal input end of the first trigger positioned at the head; or, the data signal input end of the third trigger at the head end is connected with the positive signal output end or the ground end of the first trigger at the tail end through the first selector;
the positive signal output end, the grounding end and the gating signal end of the first trigger positioned at the tail end are respectively connected with different input ends of the first selector, and the output end of the first selector is connected with the data signal input end of the third trigger positioned at the head end.
Further, a clock signal input end of the second flip-flop is connected with a positive signal output end of a target third flip-flop or a positive signal output end of the first flip-flop at the tail end, and the target third flip-flop is a third flip-flop connected with a target dummy resistor row.
Further, the target third flip-flop is a third flip-flop located at the tail end, and a clock signal input end of the second flip-flop is connected to a positive signal output end of the third flip-flop located at the tail end or a positive signal output end of the first flip-flop located at the tail end.
Further, a clock signal input end of the second flip-flop is connected with a positive signal output end of a third flip-flop at the tail end or a positive signal output end of the first flip-flop at the tail end through a second selector;
and the positive signal output end of the third trigger positioned at the tail end, the positive signal output end of the first trigger positioned at the tail end and the gating signal end are respectively connected with different input ends of the second selector, and the output end of the second selector is connected with the clock signal input end of the second trigger.
Further, the flip-flop is a falling edge D-type flip-flop.
Furthermore, the signal reading circuit also comprises a reference circuit, a detector bridge branch and an integrating, collecting and protecting and analog-digital conversion module;
the reference circuit is respectively and electrically connected with the integrating, acquiring and protecting, analog-to-digital conversion module and the detector bridge branch and is used for respectively providing bias voltage for the integrating, acquiring and protecting, analog-to-digital conversion module and the detector bridge branch;
the detector bridge branch is respectively and electrically connected with the integrating, collecting and protecting module and the uncooled infrared focal plane array, is used for being matched with the reference circuit and the uncooled infrared focal plane array, acquiring a current signal generated by the uncooled infrared focal plane array during working, and transmitting the current signal to the integrating, collecting and protecting module and the uncooled infrared focal plane array;
the integrating, collecting and protecting and analog-to-digital conversion module is used for integrating, collecting and protecting and analog-to-digital converting the current signals transmitted by the detector bridge branch.
According to a second aspect of the embodiments of the present application, there is provided a signal readout method for an uncooled infrared focal plane array, including:
the row selection module gates the infrared sensitive pixels and the dummy resistors in each row one by one according to a set sequence in the front-end time period of the current frame, and controls the preset target dummy resistor row to be in a conducting state in the frame redundancy time period of the current frame; wherein the target dummy resistance behavior is at least one of the plurality of rows of dummy resistances.
Further, the signal readout circuit further includes a reference circuit, a detector bridge branch, and an integrating, sampling, protecting, and analog-to-digital conversion module, and the signal readout method further includes:
bias voltages are respectively provided for the integrating module, the collecting and protecting module, the analog-to-digital conversion module and the detector bridge branch circuit through the reference circuit;
the detector bridge branch is matched with the reference circuit and the uncooled infrared focal plane array to obtain a current signal generated by the uncooled infrared focal plane array during working, and the current signal is transmitted to the integrating, collecting and protecting and analog-digital conversion module;
and integrating, collecting and protecting and analog-to-digital converting the current signals transmitted by the detector bridge branch by an integrating, collecting and protecting and analog-to-digital converting module.
The signal read-out circuit of uncooled infrared focal plane array detector that this application embodiment provided is in the conducting state at frame redundancy interval through controlling the target dummy resistance row that predetermines, realizes that the equivalent load of detector array is in the state of relatively invariable at frame redundancy interval, reduces the operating voltage ripple that arouses because the load is undulant to reduce the influence to the follow-up work of read-out circuit, be favorable to improving the stability of read-out circuit output signal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of an operating process of a signal readout circuit of a related uncooled infrared focal plane array detector;
FIG. 2 is a schematic diagram of a simulation unit of an imaging circuit of a detector;
FIG. 3 is a diagram illustrating the effect of correlated timing redundancy time on circuit ripple;
fig. 4 is a schematic structural diagram of an operating process of a signal readout circuit of an uncooled infrared focal plane array detector according to an embodiment of the present disclosure;
FIG. 5 (a) is a schematic diagram of a first row selection signal generating circuit according to an embodiment of the present application;
FIG. 5 (b) is a schematic diagram of a second row selection signal generating circuit according to an embodiment of the present application;
FIG. 6 is a timing diagram of row selection signals during row selection of dummy resistors;
FIG. 7 is a schematic diagram of the timing relationship of row select signals when the dummy resistor row is not gated;
FIG. 8 is a block diagram illustrating a detector array architecture for a row selection control scheme according to an embodiment of the present application;
FIG. 9 is a schematic diagram of an embodiment of a readout circuit with improved electrical ripple.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
Fig. 1 is a schematic diagram of a working process of a signal readout circuit of a related uncooled infrared focal plane array detector, where the readout circuit includes a central timing control module 10', a row selection module 20', an uncooled infrared focal plane array 30', a reference circuit 70', a detector bridge branch 60', and an integrating, acquiring, protecting, and analog-to-digital conversion module 50'. The uncooled infrared focal plane array 30' includes an imaging array portion 301' having N x M infrared sensitive pixel elements and a non-imaging array portion 302' having N x R Dummy resistors (which may be referred to as Dummy resistors). That is, the uncooled infrared focal plane array 30' includes M rows of infrared sensitive pixel rows and R rows of Dummy resistor rows (also called Dummy rows). The dummy resistor row has a special role in image correction and testing. In order to meet the control and image output requirements of the detector in different application environments, the related uncooled infrared focal plane array reading circuit usually needs to adjust parameters such as frame frequency, data transmission rate and the like in the working process, and a corresponding frame redundancy period can be generated at the end of each frame. After the readout circuit shown in fig. 1 starts to work, the imaging array with N × M infrared sensitive pixels is turned on line by line, after the imaging array is turned on, the non-imaging part with N × R dummy resistors starts to be turned on, when the last line of the non-imaging part finishes working, a frame redundancy period is entered, all the resistors in the non-refrigeration infrared focal plane array 30' are disconnected in the frame redundancy period, and the readout circuit stops working.
The column-level integrated uncooled infrared focal plane array reading circuit usually adopts the working mode of row-by-row integration and column-by-column reading. The basic operation of the sensing circuit shown in fig. 1 is as follows: when the circuit enters a normal working state, the central timing control module 10' can generate a series of clock control signals, such as row selection control signals, integral control signals, column selection control signals and the like, the row selection module 20' can generate row selection signals according to the row selection control signals to gate the infrared sensitive pixels and the dummy resistor rows, and the integrating, sampling and holding and analog-to-digital conversion module 50' can sequentially perform the operations of integrating, sampling/holding, analog-to-digital conversion and the like on weak current signals caused by the selected passing infrared sensitive pixels and finally output digital signals.
FIG. 2 is a schematic diagram of a detector imaging circuit simulation unit, which includes field effect transistors M1, M2, M3, M4, and a resistor Rs、Rd、Rdm、RsmAnd an integrating circuit; wherein R issThe resistance R of the infrared sensitive pixel is caused by the change of external infrared radiationsVariation of resistance, RdA compensation resistor for adjusting the temperature of the substrate. RdmAnd RsmFor externally regulating the generated matching resistance for suppressing the voltage V of the first voltage terminalskAnd a voltage V of the second voltage terminaldetThe noise of (2). Compensation resistor RdmOne end of which is connected with a first voltage end VskAnd the other end is connected with the source electrode of the field effect transistor M4. Compensation resistor RsmOne end of the field is connected with a second voltage end VdetAnd the other end is connected with the source electrode of the field effect transistor M3. The drain electrode of the effect tube M4 is connected with the drain electrode of the field effect tube M3. Compensation resistor RdOne end of the second resistor is connected with the first voltage end, and the other end of the second resistor is connected with the source electrode of the field effect transistor M2. Infrared sensitive pixel resistor RsOne end of which is connected with a second voltage end VdetAnd the other end is connected with the source electrode of the field effect transistor M1. And the drain electrodes of the field effect transistor M1 and the field effect transistor M2 are connected, and are connected with the input end of the integrating circuit. The grid of the field effect transistor M4 is connected with the grid of the field effect transistor M2, and the grid of the field effect transistor M3 is connected with the grid of the field effect transistor M1. Veb、VrefFor a fixed DC bias voltage, supplied by the reference circuit, VfidIncluding a resistor R from the leftdm、RsmAnd mirror image circuit generation of field effect transistors M3 and M4 for adjusting infrared sensitive pixel resistor RsThe bias voltage of (1). Taking the direction of current as the specified direction in the figure as an example, the integral voltage V output by the integral circuit0Can be expressed as:
wherein, TintFor integration time, CintIs an integrating capacitance. VfidThe expression is as follows:
FIG. 3 is a diagram illustrating the effect of relative timing redundancy time on circuit ripple. As shown in FIG. 3, VskThe voltage of the first voltage end can also be understood as the working voltage of the reading circuit; the row selection state representation circuit is in a conducting state or a disconnecting state, wherein the circuit is in the conducting state when the row selection state is high, and the circuit is in the disconnecting state when the row selection state is low. For the array detector with N multiplied by M infrared sensitive pixels and N multiplied by R dummy resistors, after the imaging array part is conducted, the non-imaging array part is conducted, and the reading circuit enters a frame redundancy time interval T after the last row of operation is finishedoAnd at the moment, all the resistors in the uncooled infrared focal plane array are disconnected, and the reading circuit stops working until the next frame is restarted. V is caused due to variation in equivalent load in the frame redundancy period read-out circuitskAnd the like, and the imaging effect is influenced. Wherein, VskThe change in (c) will affect the operation of the read-out circuit at the start of the next frame and will have a direct effect on the output signal. Concretely, the formula (2) is substituted into the formula (1) and V is treatedskThe deviation was calculated to obtain the formula (3), and it was found that the formula (3) indicates VskThe amount of associated impact.
Based on the above-mentioned frame redundancy period because the readout circuit equivalent load changes and the adverse effect that brings, the application provides a signal readout circuit of new uncooled infrared focal plane array detector, and this signal readout circuit can include row selection module and uncooled infrared focal plane array.
The uncooled infrared focal plane array comprises a plurality of rows of infrared sensitive pixels and a plurality of rows of dummy resistors which are arranged in rows and columns.
The row selection module is used for gating the infrared sensitive pixels and the dummy resistors in each row one by one according to a set sequence in the front-end time period of the current frame and controlling the preset target dummy resistor row to be in a conducting state in the frame redundancy time period of the current frame; wherein the target dummy resistance behavior is at least one of the plurality of rows of dummy resistances.
It should be noted that the front-end period referred to herein may be understood as a period in which each row of the sensitive pixel and each row of the dummy resistor are selected in one frame, that is, a period other than the frame redundancy period. In specific implementation, the conducting sequence of each row of the sensitive pixels and each row of the dummy resistors can be set, and the conducting sequence of each row of the infrared sensitive pixels can be set to be conducted row by row or can be set to be conducted in a row skipping manner. Similarly, the order of conducting the dummy resistors of each row may be set to conduct row by row, or may be set to conduct skip row. The target dummy resistance row referred to herein may be understood as a dummy resistance row which is preset to be capable of being turned on in the frame redundancy period. In some embodiments, the target dummy resistance row may be one row, such as the last row of dummy resistance rows, but may be other dummy resistance rows. In some embodiments, the target dummy resistance row may also be a plurality of rows that may be turned on row by row or may be turned on in a skipping manner in the frame redundancy period.
Further, the uncooled infrared focal plane array includes a central timing control module. The central time sequence control module is electrically connected with the row selection module and used for providing time sequence signals for the row selection module.
The line selection module gates the infrared sensitive pixels and the dummy resistors in each line one by one according to a set sequence in the front-end time period of the current frame, and controls the preset target dummy resistor line to be in a conducting state in the frame redundancy time period of the current frame, specifically according to the time sequence signal.
Furthermore, the signal reading circuit also comprises a reference circuit, a detector bridge branch and an integrating, collecting and protecting and analog-digital conversion module;
the reference circuit is respectively and electrically connected with the integrating, acquiring and protecting, analog-to-digital conversion module and the detector bridge branch and is used for respectively providing bias voltage for the integrating, acquiring and protecting, analog-to-digital conversion module and the detector bridge branch;
the detector bridge branch is respectively and electrically connected with the integrating, collecting and protecting module and the uncooled infrared focal plane array, is used for being matched with the reference circuit and the uncooled infrared focal plane array, acquiring a current signal generated by the uncooled infrared focal plane array during working, and transmitting the current signal to the integrating, collecting and protecting module and the uncooled infrared focal plane array;
the integrating, collecting and protecting and analog-to-digital conversion module is used for integrating, collecting and protecting and analog-to-digital converting the current signals transmitted by the detector bridge branch.
The signal readout circuit of the uncooled infrared focal plane array detector will be described with reference to fig. 4 to 9. Fig. 4 is a schematic structural diagram of an operating process of a signal readout circuit of an uncooled infrared focal plane array detector according to an embodiment of the present application, please refer to fig. 4 and fig. 5 (a) to 9 in combination as necessary. The readout circuit comprises a central timing control module 10, a row selection module 20, an uncooled infrared focal plane array 30, a reference circuit 70, a detector bridge branch 60 and an integrating, acquiring, protecting and analog-to-digital conversion module 50. The uncooled infrared focal plane array 30 includes an imaging array portion 301 having N × M infrared sensitive pixel elements and a non-imaging array portion 302 having N × R Dummy resistors (which may be referred to as Dummy resistors). That is, the uncooled infrared focal plane array 30 includes M rows of infrared sensitive pixel rows and R rows of Dummy resistor rows (also called Dummy rows).
After the signal reading circuit of the uncooled infrared focal plane array detector shown in fig. 4 starts to work, the imaging array with N × M infrared sensitive pixels is conducted line by line, after the conduction of the imaging array is finished, the non-imaging part with N × R dummy resistors starts to be conducted, and when the last line of the non-imaging part finishes working, the frame redundancy period continues to keep a conducting state until the first line of the next frame is conducted. The frame redundancy period is a period from the end of the last line in the dummy resistance line of the non-imaging part to the conduction of the first line of the next frame. That is, in the present embodiment, the target dummy resistance row is the last row of dummy resistance rows. During this frame redundancy period, the equivalent load of the circuit is in a relatively constant state.
In some embodiments, the row selection module may include a second flip-flop. The second flip-flop has one or more signal inputs capable of receiving a frame redundancy trigger signal and a frame redundancy end signal. The second flip-flop can control a preset target dummy resistance line to enter a conducting state when receiving the frame redundancy trigger signal, and disconnect the preset target dummy resistance line when receiving the frame redundancy end signal. The frame redundancy trigger signal triggers the second trigger to work when the front period of each frame is finished (the starting moment of the frame redundancy period), and the frame redundancy end signal triggers the second trigger to work when each frame is finished (namely the starting moment of the next frame).
Specifically, as shown in fig. 5 (a), 5 (b), 6 and 7, the row selection module 20 includes a row selection signal generation circuit, which includes a first row selection signal generation circuit shown in fig. 5 (a) and a second row selection signal generation circuit shown in fig. 5 (b), and the first row selection signal generation circuit is connected to the second row selection signal generation circuit. The first row selection signal generating circuit shown in fig. 5 (a) includes an imaging portion row selection signal generating circuit, and the second row selection signal generating circuit shown in fig. 5 (b) includes a non-imaging portion row selection signal generating circuit.
Specifically, the first row selection signal generation circuit comprises a first signal generation module 201 and a plurality of first flip-flops B1, B2 \8230, bm connected in sequence. Each first trigger is connected with a row of infrared sensitive pixels to output row selection signals to the connected row of infrared sensitive pixels. The data signal input end, the clock signal input end and the reset signal input end of the first signal generation module are respectively connected with a high-level signal end VDDH, a clock signal end Rowsel _ Clk and a reset signal end Frame _ Rst. The output end of the first signal generating module 201 is connected to the data signal input end of the first flip-flop B1 at the head end. The signal output by the output terminal of the first signal generating module 201 is used as the input data signal of the first flip-flop B1. The positive signal output ends of the first flip-flops except the first flip-flop Bm at the tail end are connected with the data signal input end of the next first flip-flop. For example, the positive signal output terminal of the first flip-flop B1 is connected to the data signal input terminal of the first flip-flop B2, that is, the positive signal Row <1> output by the positive signal output terminal of the first flip-flop B1 is used as the input data signal of the first flip-flop B2. The clock signal input end and the reset signal input end of each of the first triggers B1 and B2 \8230, \8230andBm are respectively connected with a clock signal end Rowsel _ Clk and a reset signal end Frame _ Rst.
The second row selection signal generating circuit comprises a second trigger D1 and a plurality of third triggers C1, C2, 8230, 8230and Cr which are connected in sequence. Each third flip-flop is connected to a row of dummy resistors. The data signal input end of the third flip-flop C1 at the head end is connected to the positive signal output end or the ground end GND of the first flip-flop Bm at the tail end, from the third flip-flop C2 at the second position, the data signal input end of each third flip-flop is connected to the positive signal output end of the previous third flip-flop, and the clock signal input end and the reset signal input end of each third flip-flop are respectively connected to the clock signal end Rowsel _ Clk and the reset signal end Frame _ Rst.
The data signal end of the second trigger D1 is connected with a high level signal end VDDH, the reset signal end is connected with the inverse signal output end of the first trigger B1 at the head end, and an inverse signal Row <1> _ N output by the inverse signal output end of the first trigger B1 is taken as a reset signal. In this embodiment, the target third flip-flop is the third flip-flop Cr located at the tail end, and the clock signal input end of the second flip-flop D1 is connected to the positive signal output end of the third flip-flop Cr located at the tail end or the positive signal output end of the first flip-flop Bm located at the tail end. Accordingly, the target Dummy resistance row is the Dummy resistance row to which the third flip-flop Cr is connected, such as the last Dummy row shown in fig. 4.
It should be noted that, in some other embodiments, the target dummy resistance may be preset to other dummy resistance rows, and accordingly, the target third flip-flop is another third flip-flop correspondingly connected to the target dummy resistance row. Correspondingly, the clock signal input end of the second flip-flop D1 is connected to the positive signal output end of the target third flip-flop or the positive signal output end of the first flip-flop at the tail end. It will be appreciated that the target third flip-flop is the third flip-flop connected to the target dummy resistance row. And the positive signal output end of the second trigger and the positive signal output end of the third trigger positioned at the tail end are respectively connected to different input ends of the OR gate so as to ensure that the target dummy resistor is conducted in the frame redundancy period.
In the above embodiment, the frame redundancy trigger signal may be a trigger signal input by the second flip-flop clock signal input terminal. The frame redundancy end signal may be a signal input to the reset signal input terminal of the second flip-flop, for example, an inverted signal Row <1> _ N output from the inverted signal output terminal of the first flip-flop B1, or may be another signal capable of triggering the second flip-flop to control the target dummy resistor to be turned off at the frame redundancy end time (i.e., the next frame start time). The present application does not limit this, and the setting may be performed according to specific situations.
Further, the first signal generating module 201 includes a fourth flip-flop A1 and a fifth flip-flop A2.
The data signal input end, the clock signal input end and the reset signal input end of the fourth flip-flop A1 are respectively connected with the high-level signal end VDDH, the clock signal end Rowsel _ Clk and the reset signal end Frame _ Rst. The positive signal output end of the fourth flip-flop A1 is connected with the data signal input end of the fifth flip-flop A2.
The clock signal input end and the reset signal input end of the fifth flip-flop A2 are respectively connected with the clock signal end Rowsel _ Clk and the reset signal end Frame _ Rst. The negative signal output end of the fifth trigger A2 and the positive signal output end of the fourth trigger A1 are respectively connected with different input ends of the AND gate to provide input signals for the AND gate. And the output end of the AND gate is connected with the data signal input end of the first trigger B1 positioned at the head position so as to provide a high pulse strobe signal with a certain length for the first trigger B1.
Further, the data signal input terminal of the third flip-flop C1 at the head end is connected to the positive signal output terminal or the ground terminal of the first flip-flop Bm at the tail end through the first selector (i.e., the selector 1).
The positive signal output end, the ground end and the gating signal end of the first flip-flop Bm at the tail end are respectively connected with different input ends of the first selector. The output terminal of the first selector is connected to the data signal input terminal of the third flip-flop C1 located at the head end to input a data signal thereto. The gate signal terminal can provide a gate signal Dummy _ sel to the first selector to gate the row selection signal output from the positive signal output terminal of the first flip-flop Bm at the tail end or gate the signal GND of the ground terminal and transmit the gated signal to the third flip-flop C1.
Further, the clock signal input terminal of the second flip-flop D1 is connected to the positive signal output terminal of the third flip-flop Cr at the tail end or the positive signal output terminal of the first flip-flop Bm at the tail end through a second selector (i.e., the selector 2).
The positive signal output end of the third flip-flop Cr located at the tail end, the positive signal output end of the first flip-flop Bm located at the tail end, and the strobe signal end are respectively connected to different input ends of the second selector, and the output end of the second selector is connected to the clock signal input end of the second flip-flop D1. The gate signal terminal can supply a gate signal Dummy _ sel to the second selector to gate the row selection signal output from the positive signal output terminal of the third flip-flop Cr or gate the row selection signal from the positive signal output terminal of the first flip-flop Bm at the tail end, and transmit the gated signal to the third flip-flop C1.
In this embodiment, each of the flip-flops is a falling edge D-type flip-flop. Accordingly, the frame redundancy trigger signal can be understood as a falling edge of the signal input at the clock input of the second flip-flop. For example, the falling edge of the signal Dummy < end > output from the positive signal output terminal of the third flip-flop Cr at the tail end or the falling edge of the signal Row < M > output from the positive signal output terminal of the first flip-flop Bm at the tail end. Of course, the signal may be other signals capable of triggering the second flip-flop to control the preset target dummy resistor to enter the conducting state when the front end period of each frame is ended (the start time of the frame redundancy period), which is not limited in the present application and may be set according to the specific application environment. Accordingly, the frame redundancy end signal may be a falling edge of the signal input to the second flip-flop reset signal input terminal. For example, the first flip-flop B1 inverts the falling edge of the signal Row <1> _ N output from the signal output terminal. In addition, in some other embodiments, each flip-flop may also be a rising edge D-type flip-flop, and the row selection signal generation circuit, the row selection timing signal, and the like need to be adjusted accordingly according to the operating principle of the rising edge D-type flip-flop.
The output signal of each flip-flop is a signal generated by the data signal inputted from the data signal input terminal under the combined action of the clock signal inputted from the clock signal input terminal and the reset signal inputted from the reset signal input terminal.
Specifically, as shown in fig. 5 (a), 5 (B), 6 and 7, the first flip-flops B1 and B2 \8230 \ 8230in the imaging array portion 301 sequentially generate Row selection signals Row <1>, row <2> \8230 \ 8230 \ 8230and Row < M > -corresponding to the infrared sensitive pixel rows when the flip-flops operate, and respectively output Row selection signals to the infrared sensitive pixel rows correspondingly connected to the first flip-flops to control the M-Row imaging array to be conducted Row by Row. Of course, in other embodiments, the conduction may not be performed line by line, and may be set according to a specific environment.
In the non-imaging array portion 302, except the third flip-flop at the tail end, each of the other third flip-flops sequentially generates the row selection signals Dummy <1>, dummy <2>, \8230 \ 8230 \ Dummy < end-1> -corresponding to each of the Dummy resistor rows during operation. That is, in the non-imaging array portion 302, the row selection signals Dummy <1>, dummy <2> \8230, dummy < end-1> except the last row are generated by controlling the corresponding third flip-flops according to the clock signal provided by the clock signal terminal Rowsel _ Clk. The LAST Row select signal Dummy _ LAST of the non-imaging array section 302 is controlled by the inverse signals Row <1> _ N and Dummy < end > of the Row select signal Row 1 of the imaging array section 301. The line selection signal Dummy _ LAST controls the LAST line to be conducted, so that the LAST line continues to maintain a conducting state after the normal work is finished, and the LAST line is maintained until the first line of the next frame is conducted, and the specific timing relationship is shown in fig. 6. It should be noted that, in addition to the row selection signal generating circuit shown in fig. 5, the digital portion of the detector readout circuit also needs to make corresponding adjustments to the row selection control circuit inside the digital circuit, which is related to the working state of the dummy resistor row of the non-imaging portion in the frame redundancy period, so as to ensure that the dummy resistor row can be correctly turned on in the frame redundancy period.
Of course, for embodiments that do not target the last row of Dummy resistors in non-imaging array portion 302, the third flip-flop Cr at the tail end generates the row select signal Dummy < end > for the last row of Dummy resistors. Accordingly, dummy _ LAST is only a Row select signal of the frame redundancy period, which is generated by the Row select signal generated by the target third flip-flop in control with the inverse signal Row <1> _ N of the 1 st Row select signal of the imaging array section 301.
In other embodiments, for simple application scenarios, the dummy resistor rows of the non-imaging array portion may not need to be on during normal operation of the detector. Specifically, it can be realized by the first selector (i.e. selector 1) in fig. 5 (b), if the dummy resistor row does not need to be gated in actual application, then this selector 1 gates GND as input. At the moment, the non-imaging part of the detector does not work, and after the imaging part is conducted, the detector enters a frame redundancy period. In this case, the detector readout circuit equivalent load variation causes a problem of circuit ripple in order to avoid the frame redundancy period. The row selection signal generating circuit of the row selection module can generate a row selection signal to forcedly select one row of the dummy resistance rows as a target dummy resistance row, so that the selected dummy resistance rows are in a conducting state in a frame redundancy period, and the equivalent load in the circuit is ensured to be the same as the load in normal operation. For example, as shown in fig. 5 (a) and 5 (b), the row selection signal generating circuit may be configured to generate the row selection signal Dummy _ LAST while forcibly gating the LAST row of Dummy resistance rows as the target Dummy resistance rows. The Row selection signal Dummy _ LAST is generated by the combined action of the inverse signals Row <1> _ N and Row < M > of the Row selection signal of the 1 st Row in the Row selection signal generating circuit, so that the LAST Row of Dummy resistor rows is continuously conducted in the frame redundancy period, the equivalent load of the array is ensured to be the same as that in normal operation, and the specific time sequence relation is shown in fig. 7. Of course, in other embodiments, the row select signal generating circuit may be arranged to generate other row select signals to force gating other row dummy resistance rows as target dummy resistance rows, but the selected target dummy resistance rows are in a conducting state during the frame redundancy period.
Further, fig. 8 shows an improved detector array structure using the readout circuit described above in the present application. The detector array includes an imaging array portion having NxM infrared-sensitive picture elements Rs, and a plurality of dummy resistors R having N columnsdummyThe infrared sensitive pixels and the dummy resistors are respectively provided with corresponding gating switches, and the infrared sensitive pixels or the dummy resistors can be respectively controlled to be switched in by the gating switches. When a certain gating switch is closed, the infrared sensitive pixel or the dummy resistor corresponding to the gating switch is conducted to the detector array structure and comprises a plurality of detector imaging circuit units and non-imaging circuit units similar to those shown in FIG. 2. The infrared sensitive pixel Rs of the imaging circuit unit part of the detector is selectively connected with the field effect transistor Mn and the dummy resistor R of the non-imaging circuit unit part through respective gating switchesdummyThe field effect transistor Mn is optionally connected via a respective gate switch. When the imaging is normal, a reading circuit of the detector firstly selects the infrared sensitive pixel Rs of a certain row, then the operations of extracting, integrating, sampling and holding, analog-to-digital conversion and the like of the infrared sensitive pixel Rs signal of the row are completed, and each column of digital signals can be read column by column through an output control module for parallel-serial conversion and the like by a column selection control part. When the dummy resistance row of the non-imaging array is turned on, that is, when the non-imaging circuit unit operates, the circuit internally keeps only the resistance of the dummy resistance row of the non-imaging array portion switched in, and does not perform operations such as integration and signal output.
It is further noted that the infrared sensitive pixel described herein is designed for low thermal conductivity to better detect ambient radiation temperature changes. In the present application, the dummy resistor, especially the target dummy resistor, needs to be designed as a resistor with high thermal conductivity due to long-term conduction in time sequence, so as to reduce the risk of overheating damage of the dummy resistor, especially the target dummy resistor, for long-term use, thereby being beneficial to increasing the service life of the dummy resistor and the whole readout circuit. I.e. the thermal conductivity of the dummy resistor of the non-imaging array portion is designed to be much higher than the thermal conductivity of the infrared-sensitive picture element.
FIG. 9 is a schematic diagram of an embodiment of a readout circuit for improving the electrical ripple according to the present invention, where V in FIG. 9skThe row selection state represents whether the circuit is in a conducting state or a disconnecting state for the voltage of the first voltage end, wherein the row selection state is high and represents that the circuit is in the conducting state. The frame synchronization signal is used for representing as an output signal, and the frame synchronization is high, which indicates that data is output, and is beneficial to peripheral hardware to acquire data. As can be seen from fig. 9, the gating state of each row in the array of the detector using the above-mentioned readout circuit is continuous in time, and the state that the array resistors are all disconnected in the frame redundancy period in the readout circuit of the relevant detector does not occur, so that the frame redundancy T shown in fig. 3 does not occuroRipple caused by the step voltage Vsk.
By adopting the embodiment, the last line of the non-imaging array part is always in a conducting state in the frame redundancy period corresponding to the relevant redundancy time, and the equivalent load of the signal read-out current of the non-refrigeration infrared focal plane array detector is the same as that in normal working, so that other signals in the circuit cannot fluctuate due to load change. So that the voltage V of the first voltage terminalskAmplitude change caused by the fact that all resistors in the array are disconnected can be avoided, and therefore the problem that the resistors affect output signals of the detector is well solved.
Further, the reference circuit 70 is electrically connected to the integrating, sampling and protection, analog-to-digital converting module 50 and the detector bridge branch 60, respectively, and is configured to provide bias voltages for the integrating, sampling and protection, analog-to-digital converting module 50 and the detector bridge branch 60, respectively.
The detector bridge branch 60 is respectively electrically connected with the integrating, collecting, protecting and analog-digital conversion module 50 and the uncooled infrared focal plane array, and is used for being matched with the reference circuit 70 and the uncooled infrared focal plane array to obtain a current signal generated by the uncooled infrared focal plane array during working and transmitting the current signal to the integrating, collecting, protecting and analog-digital conversion module;
the integrating, sampling, protecting and analog-to-digital converting module 50 is used for integrating, sampling, protecting and analog-to-digital converting the current signal transmitted by the detector bridge branch 60.
The application also provides a signal reading method of the uncooled infrared focal plane array detector, which is applied to the signal reading circuit of the uncooled infrared focal plane array detector, and the method comprises the following steps of S1 and S2:
in step S1, a timing signal is supplied to the row selection module 20 by controlling the central timing control module 10.
In step S2, the row selection signal generating circuit of the row selection module 20 gates the infrared sensitive pixels and the dummy resistors in each row one by one according to the timing signal in the front-end period of the current frame in a set order, and controls the preset target dummy resistor row to be in a conducting state in the frame redundancy period according to the timing signal in the frame redundancy period of the current frame. Wherein the target dummy resistance behavior is at least one of the plurality of rows of dummy resistances.
Further, the signal reading circuit further comprises a reference circuit, a detector bridge branch and an integrating, sampling and protecting and analog-to-digital conversion module, and the signal reading method further comprises the following steps:
bias voltage is respectively provided for the integrating, sampling and protecting, the analog-to-digital conversion module and the detector bridge branch circuit through a reference circuit;
the detector bridge branch is matched with the reference circuit and the uncooled infrared focal plane array to obtain a current signal generated by the uncooled infrared focal plane array during working, and the current signal is transmitted to the integrating, collecting and protecting and analog-digital conversion module;
and integrating, collecting and protecting and analog-to-digital converting the current signal transmitted by the detector bridge branch through an integrating, collecting and protecting and analog-to-digital converting module.
In the present application, the structural embodiments and the method embodiments may be complementary to each other without conflict.
In this application, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The terms "plurality," "plurality," and "a number" refer to two or more unless expressly limited otherwise.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (12)
1. A signal reading circuit of an uncooled infrared focal plane array detector is characterized by comprising a row selection module and an uncooled infrared focal plane array;
the uncooled infrared focal plane array comprises a plurality of rows of infrared sensitive pixels and a plurality of rows of dummy resistors;
the row selection module is used for gating the infrared sensitive pixels and the dummy resistors in each row one by one according to a set sequence in the front-end time period of the current frame and controlling the preset target dummy resistor row to be in a conducting state in the frame redundancy time period of the current frame; wherein the target dummy resistance behavior is at least one of the plurality of rows of dummy resistances.
2. The signal readout circuit of an uncooled infrared focal plane array detector of claim 1, wherein the row selection module comprises a second flip-flop capable of receiving a frame redundancy trigger signal and a frame redundancy end signal, and capable of controlling a preset target dummy resistor row to be in a conducting state when receiving the frame redundancy trigger signal, and disconnecting the preset target dummy resistor row when receiving the frame redundancy end signal.
3. The signal readout circuit of the uncooled infrared focal plane array detector of claim 2, wherein the row selection module comprises a second row selection signal generation circuit, and the second row selection signal generation circuit comprises the second flip-flop and a plurality of third flip-flops connected in sequence; each third trigger is connected with one row of the dummy resistors, so that each third trigger controls one row of the dummy resistors; the clock signal input end and the reset signal input end of each third trigger are respectively connected with the clock signal end and the reset signal end, and the data signal input end of each third trigger is connected with the positive signal output end of the previous third trigger from the third trigger positioned at the second position; the data signal end of the second trigger is connected with the high-level signal end, the clock signal input end of the second trigger is used for receiving a frame redundancy trigger signal, and the reset signal end of the second trigger is used for receiving a frame redundancy end signal; and the positive signal output end of the second trigger and the positive signal output end of the third trigger positioned at the tail end are respectively connected to different input ends of the OR gate.
4. The signal readout circuit of the uncooled infrared focal plane array detector of claim 3, wherein the row selection module comprises a first row selection signal generation circuit, the first row selection signal generation circuit comprises a first signal generation module and a plurality of first flip-flops connected in sequence, each of the first flip-flops is connected to a row of the infrared sensitive pixel, so that each of the first flip-flops controls a row of the infrared sensitive pixel; the data signal input end, the clock signal input end and the reset signal input end of the first signal generation module are respectively connected with the high-level signal end, the clock signal end and the reset signal end, and the output end of the first signal generation module is connected with the data signal input end of the first trigger positioned at the head end; except the first trigger at the tail end, the positive signal output end of each of the other first triggers is connected with the data signal input end of the next first trigger, and the clock signal input end and the reset signal input end of each first trigger are respectively connected with the clock signal end and the reset signal end.
5. The uncooled infrared focal plane array detector signal readout circuit of claim 4, wherein the first signal generating module includes a fourth flip-flop and a fifth flip-flop;
a data signal input end, a clock signal input end and a reset signal input end of the fourth trigger are respectively connected with a high-level signal end, a clock signal end and a reset signal end, and a positive signal output end of the fourth trigger is connected with a data signal input end of the fifth trigger;
a clock signal input end and a reset signal input end of the fifth trigger are respectively connected with a clock signal end and a reset signal end; the negative signal output end of the fifth trigger and the positive signal output end of the fourth trigger are respectively connected with different input ends of an AND gate, and the output end of the AND gate is connected with the data signal input end of the first trigger positioned at the head; or, the data signal input end of the third trigger at the head end is connected with the positive signal output end or the ground end of the first trigger at the tail end through the first selector;
the positive signal output end, the grounding end and the gating signal end of the first trigger positioned at the tail end are respectively connected with different input ends of the first selector, and the output end of the first selector is connected with the data signal input end of the third trigger positioned at the head end.
6. The signal readout circuit of the uncooled infrared focal plane array detector of claim 4, wherein the clock signal input terminal of the second flip-flop is connected to the positive signal output terminal of the target third flip-flop or the positive signal output terminal of the first flip-flop at the tail end, and the target third flip-flop is a third flip-flop connected to the target dummy resistor row.
7. The signal readout circuit of the uncooled infrared focal plane array detector of claim 6, wherein the target third flip-flop is a third flip-flop at the tail end, and the clock signal input terminal of the second flip-flop is connected to the positive signal output terminal of the third flip-flop at the tail end or the positive signal output terminal of the first flip-flop at the tail end.
8. The signal readout circuit of the uncooled infrared focal plane array detector, according to claim 7, wherein the clock signal input terminal of the second flip-flop is connected to the positive signal output terminal of the third flip-flop at the tail end or the positive signal output terminal of the first flip-flop at the tail end through a second selector;
and the positive signal output end of the third trigger positioned at the tail end, the positive signal output end of the first trigger positioned at the tail end and the gating signal end are respectively connected with different input ends of the second selector, and the output end of the second selector is connected with the clock signal input end of the second trigger.
9. The signal readout circuit of an uncooled infrared focal plane array detector, according to any one of claims 2-8, wherein the flip-flop is a falling edge D-type flip-flop.
10. The signal readout circuit of an uncooled infrared focal plane array detector as claimed in claim 1, wherein the signal readout circuit further comprises a reference circuit, a detector bridge branch and an integrating, sampling and protecting, analog-to-digital converting module;
the reference circuit is respectively and electrically connected with the integrating, acquiring and protecting, analog-to-digital conversion module and the detector bridge branch and is used for respectively providing bias voltage for the integrating, acquiring and protecting, analog-to-digital conversion module and the detector bridge branch;
the detector bridge branch is respectively and electrically connected with the integrating, collecting and protecting module and the uncooled infrared focal plane array, is used for being matched with the reference circuit and the uncooled infrared focal plane array, acquiring a current signal generated by the uncooled infrared focal plane array during working, and transmitting the current signal to the integrating, collecting and protecting module and the uncooled infrared focal plane array;
the integrating, collecting and protecting and analog-to-digital conversion module is used for integrating, collecting and protecting and analog-to-digital converting the current signals transmitted by the detector bridge branch.
11. A signal readout method of an uncooled infrared focal plane array detector, which is applied to a signal readout circuit of the uncooled infrared focal plane array detector according to any one of claims 1 to 10, and comprises:
the row selection module gates the infrared sensitive pixels and the dummy resistors in each row one by one according to a set sequence in the front-end time period of the current frame, and controls the preset target dummy resistor row to be in a conducting state in the frame redundancy time period of the current frame; wherein the target dummy resistance behavior is at least one of the plurality of rows of dummy resistances.
12. The method for reading out a signal from an uncooled infrared focal plane array detector as claimed in claim 11, wherein the signal reading out circuit further comprises a reference circuit, a detector bridge branch and an integrating, sampling and protecting, analog-to-digital converting module, the method further comprises:
bias voltages are respectively provided for the integrating, sampling and protecting, analog-to-digital conversion module and the detector bridge branch circuit through the reference circuit;
the detector bridge branch is matched with the reference circuit and the uncooled infrared focal plane array to obtain a current signal generated by the uncooled infrared focal plane array in working, and the current signal is transmitted to the integrating, collecting and protecting and analog-to-digital conversion module;
and integrating, collecting and protecting and analog-to-digital converting the current signals transmitted by the detector bridge branch by an integrating, collecting and protecting and analog-to-digital converting module.
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| CN110375863A (en) * | 2018-04-12 | 2019-10-25 | 杭州海康微影传感科技有限公司 | The signal read circuit and method of non-refrigerate infrared focal plane array seeker |
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