CN112748614A

CN112748614A - Display panel and liquid crystal display

Info

Publication number: CN112748614A
Application number: CN202110004703.1A
Authority: CN
Inventors: 刘永; 储周硕; 朱伟; 史欣坪; 肖锋
Original assignee: Chengdu CEC Panda Display Technology Co Ltd
Current assignee: Chengdu CEC Panda Display Technology Co Ltd
Priority date: 2021-01-04
Filing date: 2021-01-04
Publication date: 2021-05-04
Anticipated expiration: 2041-01-04
Also published as: CN112748614B

Abstract

The application provides a display panel and LCD, TFT that two sub-pixels correspond in the LCD with eight domain display modes in a pixel connects nonadjacent gate line respectively, make adjacent gate line need not carry out the drive in coordination to same pixel, make adjacent gate line can be when the GOA drive, can carry out the aversion in advance of drive signal between the gate line before stopping the drive to a pixel, make the LCD of eight domain display modes can realize GOA pre-charge function, improve GOA circuit's drive effect and LCD's pixel charge rate, and then improve LCD's display effect.

Description

Display panel and liquid crystal display

Technical Field

The application relates to the technical field of liquid crystal display, in particular to a display panel and a liquid crystal display.

Background

A Liquid Crystal Display (LCD) is a Display device which has a structure in which a Liquid Crystal layer is disposed between two substrates which are parallel to each other, a Thin Film Transistor (TFT) is disposed on a lower substrate, a color filter is disposed on an upper substrate, and a rotation direction of Liquid Crystal molecules in the Liquid Crystal layer is controlled by changing signals and voltages on the TFT on the lower substrate, and polarization of incident light is combined to Display an image.

In the prior art, because the liquid crystal display has a large viewing angle color distortion problem, some liquid crystal displays use a liquid crystal display panel of a multi-domain (domain) Vertical Alignment (VA) mode as a lower substrate, and when a pixel structure of the liquid crystal display is designed, a pixel is divided into two sub-pixels, and then when the two sub-pixels are at different voltages, the two sub-pixels respectively provide 4 different liquid crystal molecular directions for configuration, so that 8 different liquid crystal molecular directions (8 domains for short) are provided on one pixel, and finally, a low color cast effect is achieved, thereby improving the large viewing angle color distortion problem.

In the conventional eight-domain VA mode lcd, since one pixel includes two sub-pixels, two adjacent Gate lines are required to cooperatively control TFTs of the same pixel, and the driving signal between the Gate lines cannot be shifted in advance before the driving of one pixel is stopped, so that the lcd cannot achieve a precharge function of Gate Driver on Array (GOA).

Disclosure of Invention

The application provides a display panel and LCD, TFT that two sub-pixels correspond in the LCD with eight domain display modes in a pixel connects nonadjacent gate line respectively electricity, make adjacent gate line need not carry out the drive in coordination to same pixel, make adjacent gate line can be when the GOA drive, can carry out the aversion in advance of drive signal between the gate line before stopping the drive to a pixel, make the LCD of eight domain display technical mode can realize GOA pre-charge function, improve the drive effect of GOA circuit and LCD's pixel charge rate, and then improve LCD's display effect.

A first aspect of the present application provides a display panel, comprising: a plurality of data lines arranged in parallel at intervals along a first direction; the gate lines are arranged in parallel at intervals along a second direction, the first direction is vertical to the second direction, and the data lines and the gate lines are arranged in a crossed mode; a plurality of pixel regions; each pixel region is positioned between two gate lines and two data lines, and is electrically connected with one data line and two gate lines; one of the plurality of pixel regions includes a first pixel region including: the first sub-pixel electrode and the second sub-pixel electrode are arranged between the first gate line and the second gate line and are sequentially arranged at intervals along the second direction; the first switch component is electrically connected with the first gate line, the first sub-pixel electrode and the data line; the second switch component is electrically connected with the first gate line, the second sub-pixel electrode, the data line and the third switch component; a third switching element electrically connected to the second sub-pixel electrode target gate line; wherein the target gate line and the first gate line are spaced by at least one gate line.

In an embodiment of the first aspect of the present application, the first switch component, the second switch component and the third switch component are all thin film transistors; the grid electrode, the drain electrode and the source electrode of the first switch component are respectively and electrically connected with the first grid line, the first sub-pixel electrode and the data line; the grid electrode, the drain electrode and the source electrode of the second switch component are respectively and electrically connected with the first grid line, the second sub-pixel electrode and the data line; and the grid electrode, the drain electrode and the source electrode of the third switch component are respectively and electrically connected with the target grid line, the common electrode and the second sub-pixel electrode.

In an embodiment of the first aspect of the present application, the target gate line is a third gate line; wherein a second pixel region of the plurality of pixel regions is disposed between the second gate line and the third gate line.

In an embodiment of the first aspect of the present application, the method further includes: a first lead and a first via, a first end of the first lead being electrically connected to a source of the third switch component, the first lead being disposed through the first dark stripe region of the second pixel region along the second direction, a second end of the first lead being electrically connected to the first via, the first via being for electrically connecting the first lead and a portion of the second sub-pixel electrode crossing the second gate line; the first end of the second lead is electrically connected with the drain of the second switch component, the second lead penetrates through the dark fringe area at the edge of the first pixel area in the second direction, the second end of the second lead is electrically connected with the second via, and the second via is used for electrically connecting the second lead with the second sub-pixel electrode.

In an embodiment of the first aspect of the present application, the method further includes: a first lead and a first via, a first end of the first lead being electrically connected to a source of the third switch component, the first lead being disposed through the first dark stripe region of the second pixel region along the second direction, a second end of the first lead being electrically connected to the first via, the first via being for electrically connecting the first lead and a portion of the second sub-pixel electrode crossing the second gate line; a second lead and a second via, wherein a first end of the second lead is electrically connected to the drain of the second switch component, a second end of the second lead is electrically connected to the second via, and the second via is used for electrically connecting the extension portion of the second sub-pixel electrode and the drain of the second switch component; wherein the extending portion of the second sub-pixel is disposed in parallel to the edge of the first pixel region along the second direction at an interval.

In an embodiment of the first aspect of the present application, the first dark stripe region is a middle dark stripe region or an edge dark stripe region of the second pixel region.

In an embodiment of the first aspect of the present application, the target gate line is a fourth gate line; wherein a second pixel region of the plurality of pixel regions is disposed between the second gate line and a third gate line, and a third pixel region of the plurality of pixel regions is disposed between the third gate line and the fourth gate line.

In an embodiment of the first aspect of the present application, the method further includes: a third lead and a third via, wherein a first end of the third lead is electrically connected to a source of the third switch component, the third lead sequentially passes through a second dark stripe region of the third pixel region and a third dark stripe region of the second pixel region along the second direction, the third lead is arranged across the third gate line, a second end of the third lead is electrically connected to the third via, and the third via is used for electrically connecting the third lead and the second subpixel electrode; the first end of the fourth lead is electrically connected with the drain of the second switch component, the fourth lead penetrates through the dark fringe area at the edge of the first pixel area in the second direction, the second end of the fourth lead is electrically connected with the fourth via, and the fourth via is used for electrically connecting the fourth lead with the second sub-pixel electrode.

In an embodiment of the first aspect of the present application, the second dark stripe region is a middle dark stripe region or an edge dark stripe region of the third pixel region; the third dark stripe area is a middle dark stripe area or an edge dark stripe area of the second pixel area.

A second aspect of the present application provides a liquid crystal display comprising a display panel as defined in any one of the first aspects of the present application.

A third aspect of the present application provides a method for driving a liquid crystal display, which is applied to the display panel according to any one of the first aspect of the present application, including: the first switch component and the second switch component are conducted through the first grid line; charging the first subpixel electrode and the second subpixel electrode through a data line; and controlling the third switch component to be turned on through the target grid line, so that the second sub-pixel electrode is discharged through the third switch component, and the voltages of the first sub-pixel electrode and the second sub-pixel electrode are different.

In an embodiment of the third aspect of the present application, the driving method further includes: transmitting a second gate driving signal to a second gate line at a second timing after a first timing at which a first gate driving signal is transmitted to the first gate line; the first time and the second time are separated by N single-line scanning time, the duration of the first grid signal is M single-line scanning time, and N is more than 0 and less than M.

In summary, according to the display panel and the liquid crystal display provided by the application, TFTs corresponding to two sub-pixels in one pixel of the liquid crystal display in the eight-domain display mode are respectively connected to non-adjacent gate lines, so that the adjacent gate lines do not need to cooperatively drive the same pixel, and when the adjacent gate lines are driven by the GOA, the driving signals between the gate lines can be shifted in advance before the driving of the pixel is stopped, so that the liquid crystal display in the eight-domain display mode can achieve the GOA pre-charging function, the driving effect of the GOA circuit and the pixel charging rate of the liquid crystal display are improved, and further the display effect of the liquid crystal display is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

FIG. 1 is a schematic cross-sectional view of a liquid crystal display device in accordance with the present application;

FIG. 2 is a schematic view of a pixel of an eight-domain liquid crystal display;

FIG. 3 is a schematic diagram of a pixel structure of an LCD;

FIG. 4 is a schematic diagram of an equivalent circuit of an array substrate;

FIG. 5 is a schematic structural diagram of an array substrate;

FIG. 6 is a schematic diagram of a GOA precharge function;

fig. 7 is a schematic equivalent circuit diagram of an array substrate provided in the present application;

fig. 8 is a schematic equivalent circuit diagram of an array substrate provided in the present application;

fig. 9 is a schematic structural diagram of an array substrate provided in the present application;

fig. 10 is a schematic structural diagram of an array substrate provided in the present application;

fig. 11 is a schematic diagram of driving signals of an array substrate provided in the present application;

FIG. 12 is a schematic diagram of a pixel structure of a liquid crystal display provided in the present application;

fig. 13 is a schematic equivalent circuit diagram of an array substrate provided in the present application;

fig. 14 is a schematic structural diagram of an array substrate provided in the present application;

fig. 15 is a schematic structural diagram of an array substrate provided in the present application;

fig. 16 is a schematic diagram of driving signals of an array substrate provided in the present application;

fig. 17 is a schematic diagram of the advance time of the GOA pre-charge time provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural cross-sectional view of a liquid crystal display applied in the present application, wherein the liquid crystal display includes a TFT substrate 13 and a color filter substrate (CF substrate for short) 11 that are disposed at an interval. The CF substrate 11 is further provided with a common electrode 110, which may be a whole transparent conductive film, such as an Indium Tin Oxide (ITO) film. The liquid crystal layer 12 is filled between the TFT substrate 13 and the CF substrate 11, the liquid crystal molecules 120 are filled in the liquid crystal cell of the liquid crystal layer 12, various wirings, pixel electrodes and the like arranged on the TFT substrate 13 can be used for providing driving signals to the liquid crystal molecules 120 in the liquid crystal layer 12, and the rotation direction of the liquid crystal molecules 120 in the liquid crystal layer 12 is changed by the driving voltages at the two ends of the TFT substrate 13 and the CF substrate 11, so that the polarized light emitting direction of each pixel point in the liquid crystal layer 12 is controlled, and the display of light rays with different intensities and different colors is realized on each pixel point of the liquid crystal display.

Some liquid crystal displays have started to use multi-domain (multi-domain) display technologies, such as four-domain (4-domain), eight-domain (8-domain), etc., due to the problem of color distortion at large viewing angles. The principle is that a liquid crystal molecule alignment technology is utilized to realize multiple domain display in a pixel, as shown in a liquid crystal layer 12 of the liquid crystal display shown in fig. 1, liquid crystal in each pixel is divided into multiple domains according to the same direction under the action of an electric field, and the brightness of light rays emitted by the liquid crystal in different domains is complementary or even in different viewing angles, so that the wide viewing angle is realized, and the large viewing angle distortion of the liquid crystal display is reduced.

For example, fig. 2 is a schematic diagram of a pixel of an eight-domain liquid crystal display, in which, for each pixel 121 in the liquid crystal layer 12, two sub-pixels are divided into numbers of (r) and (c), liquid crystal molecules in the sub-pixels (r) and (c) are arranged in four domains, and the liquid crystal molecules in each sub-pixel have 4 different orientations. When the lcd is displaying, different voltages are applied to the sub-pixel (i) and the sub-pixel (ii) of the pixel 121, so that 8 different orientations of liquid crystal molecules exist in the whole pixel 121, thereby implementing an eight-domain configuration of the lcd.

More specifically, fig. 3 is a schematic diagram of a pixel structure of a liquid crystal display, as shown in fig. 3, in order to drive liquid crystal molecules of different pixels in a liquid crystal layer, on a TFT substrate as shown in fig. 3, the pixel structure includes: a plurality of data lines arranged in parallel and spaced apart from each other: source1, Source2, Source3 … …, and a plurality of gate lines arranged in parallel and at intervals: gate1, Gate2, Gate3, and Gate4 … …, and the data lines and the Gate lines are arranged to be staggered with each other. The pixels in the liquid crystal layer are arranged in a matrix form, meanwhile, each pixel in the pixel matrix is respectively arranged at the intersection of the corresponding data line and the corresponding gate line, and each pixel is electrically connected with the adjacent data line and two adjacent gate lines.

Fig. 4 is an equivalent circuit diagram of an array substrate, in which fig. 4 shows an equivalent circuit of an array substrate of a liquid crystal display, and in fig. 4, a pixel P11 of fig. 3 is taken as an example, and the pixel P11 is electrically connected to a data line Source1, a Gate line Gate1 and a Gate line Gate 2. In order to realize an eight-domain display, the pixel P11 includes a sub-pixel (r) including a TFT1 and a sub-pixel electrode main, and a sub-pixel (g) including a TFT2, a TFT3, and a sub-pixel electrode sub.

Then when the pixel P11 is going to display, the Gate1 signal controls the TFT1 and the TFT2 to charge the sub-pixel electrode main and the sub-pixel electrode sub, and after the charging is completed, under the action of the Gate line Gate2, the TFT2 discharges the sub-pixel electrode sub through the capacitor Cst3 electrically connected to the TFT3, so that there is a difference in the operating voltages of the sub-pixel electrode main electrically connected to the TFT1 and the sub-pixel electrode sub electrically connected to the TFT 2. The sub-pixel electrode main can display according to the data signal of the data line Source 1; the sub-pixel electrode sub can display according to the data signal of the data line Source 1. At this time, because the working voltages of the first sub-pixel and the second sub-pixel are different, the four different liquid crystal molecule deflection directions provided by the two sub-pixels are different, and the whole pixel can realize 8 different liquid crystal molecule deflection directions.

Fig. 5 is a schematic structural diagram of an array substrate, in which, taking Pixel1 as an example, Pixel1 is disposed between Gate lines Gate1 and Gate 2. The sub-Pixel electrode in the sub-Pixel (r) divided by the Pixel1 is main, and the TFT1 is electrically connected with the Gate line Gate1, the data line Source1 and the sub-Pixel electrode main; the sub-pixel electrode in the sub-pixel is sub, the TFT2 is electrically connected to the Gate line Gate1, the data line Source1 and the sub-pixel electrode sub, and the TFT3 is electrically connected to the Gate line Gate2 and the TFT 2. It is to be noted that the pixel structure shown in fig. 5 may be equivalent by a circuit shown in fig. 4, and only a main part of the circuit is shown in fig. 4.

That is, in the above-mentioned embodiments as shown in fig. 3 to 5, in order to realize the eight-domain display arrangement, each Pixel is divided into two sub-pixels, and the two sub-pixels respectively need two adjacent Gate lines for the cooperative driving and controlling, for example, the Pixel1 in fig. 5 needs to be electrically connected to the Gate1 and the Gate2 at the same time.

Meanwhile, in some liquid crystal displays using the GOA driving technique, in order to improve the driving efficiency of the TFT, a gate driving signal may be provided to a pixel in advance before the pixel displays, so as to improve the charging rate of the pixel to improve the driving efficiency. For example, fig. 6 is a schematic diagram of a GOA precharge function, taking 8 adjacent Gate lines in the lcd as an example, and it can be seen from the curve marked with precharge on the left side of the figure that Gate1-Gate8, before the Gate driving signal G1 corresponding to the Gate line Gate1 is ended, the Gate driving signal G2 can be provided to the Gate line Gate2 in advance. Accordingly, before the gate driving signal G2 is ended, the gate driving signal G3 and the gate driving signal G3 may be sent in advance, the gate driving signal G4 and the gate driving signal G4 may be sent in advance, the gate driving signal G5 and the gate driving signal G5 may be sent in advance, the gate driving signal G6 and the gate driving signal G6 may be sent in advance, the gate driving signal G7 and the gate driving signal G7 may be sent in advance, and the gate driving signal G8 may be sent in advance, thereby implementing the GOA pre-charging function for all the gate lines of the liquid crystal display as a whole.

In the liquid crystal display using the array substrate as shown in fig. 3 to 5, however, since two adjacent gate lines need to control one pixel at the same time, so that the gate lines cannot simultaneously transmit the driving signal of the next pixel before transmitting the driving signal of one pixel, for example, in the non-precharged curve on the right side of fig. 6, the Gate line Gate2 needs to be after the drive signal G1 for the previous pixel is ended, the gate driving signal G2 can be continuously supplied, the driving signals G1 and G2 cannot coincide, and for the same reason, the driving signals G2 and G3 cannot coincide, the driving signals G3 and G4 cannot coincide, the driving signals G4 and G5 cannot coincide, the driving signals G5 and G6 cannot coincide, the driving signals G6 and G7 cannot coincide, the driving signals G7 and G8 cannot coincide, therefore, the driving signals between the gate lines cannot be shifted in advance, and the liquid crystal display cannot realize the pre-charging function of GOA driving.

Therefore, the application provides a display panel and a liquid crystal display, the display panel can be specifically an array substrate of the liquid crystal display, in the liquid crystal display with an eight-domain display mode, TFTs corresponding to two sub-pixels in one pixel are respectively electrically connected with nonadjacent gate lines, so that the adjacent gate lines do not need to cooperatively drive the same pixel, and when adjacent gate lines are driven by a gate driver, the adjacent gate lines can perform advanced displacement of a driving signal between the gate lines before the driving of one pixel is stopped, so that the liquid crystal display with the eight-domain display mode can realize a GOA pre-charging function, thereby improving the driving effect of a GOA circuit and the pixel charging rate of the liquid crystal display, and further improving the display effect of the liquid crystal display.

The technical solution of the present application will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Fig. 7 is an equivalent circuit schematic diagram of an array substrate provided in the present application, where the array substrate shown in fig. 7 may be a TFT substrate 13 in a liquid crystal display shown in fig. 1, and meanwhile, the liquid crystal display adopts an eight-domain display configuration shown in fig. 2.

Fig. 7 is a schematic view of a pixel structure of a liquid crystal display provided in the present application, and as shown in fig. 7, in order to drive liquid crystal molecules of different pixels in a liquid crystal layer, the array substrate shown in fig. 7 includes: a plurality of data lines arranged in parallel and spaced apart from each other: source1, Source2, Source3 … …, and a plurality of gate lines arranged in parallel and at intervals: gate1, Gate2, Gate3, and Gate4 … …, and the data lines and the Gate lines are arranged to cross each other, and the first direction and the second direction are perpendicular when the direction in which the data lines extend is taken as the first direction and the direction in which the Gate lines extend is taken as the second direction. Pixels in a liquid crystal layer of the liquid crystal display are arranged in a matrix form, and each pixel in the pixel matrix is disposed at an intersection of a corresponding data line and a gate line, respectively.

In particular, in the present embodiment, each pixel is electrically connected to the data line adjacent to the pixel and electrically connected to two gate lines, wherein the two gate lines electrically connected to each pixel are not adjacent to each other, and at least one gate line is spaced between the two gate lines.

For example, in the example shown in fig. 7, each pixel is electrically connected to a first gate line adjacent thereto and is electrically connected to a target gate line, with a gate line spaced from the first gate line. Taking the pixel P11 as an example, the pixel P11 is electrically connected to the data line Source1 adjacent to the pixel and the Gate line Gate1 adjacent to the pixel, and is also electrically connected to the Gate line Gate3, and the Gate line Gate3 is separated from the Gate line Gate1 by one Gate line Gate 2.

Specifically, fig. 8 is a schematic diagram of an equivalent circuit of an array substrate of the present application, in fig. 8, an equivalent circuit of an array substrate of a liquid crystal display is shown, and in fig. 8, taking the pixel P11 in fig. 7 as an example, the pixel P11 is electrically connected to the data line Source1, the Gate line Gate1 and the Gate line Gate 3. The pixel area corresponding to the pixel P11 on the array substrate is compared with the first pixel area, and the pixel P11 is divided into a sub-pixel (i) and a sub-pixel (ii) according to the manner shown in fig. 2, and the sub-pixel (i) is realized by the first sub-pixel electrode main, and the sub-pixel (ii) is realized by the second sub-pixel electrode sub. The first pixel region in the array substrate shown in fig. 8 includes:

a first subpixel electrode main and a second subpixel electrode sub; the first and second sub-pixel electrodes main and sub are disposed between the first and second Gate lines Gate1 and Gate2 on the array substrate, and in the second direction, the first sub-pixel electrode main is adjacent to the first Gate line Gate1 and the second sub-pixel electrode sub is adjacent to the second Gate line Gate 2.

A first switching element TFT 1; the first switching element TFT1 may be a thin film transistor, and the Gate of the first switching element TFT1 is electrically connected to the first Gate line Gate1, the drain of the first switching element TFT is electrically connected to the first sub-pixel electrode main, and the Source of the first switching element TFT1 is electrically connected to the data line Source 1. The first switching element TFT1 further includes a first voltage dividing capacitor Clc1 between the drain thereof and the first sub-pixel main, and the drain of the first switching element TFT1 is further electrically connected to the common electrode CS through a first storage capacitor Cst 1.

A second switching element TFT 2; the second switching element TFT2 may be a thin film transistor, and the Gate of the second switching element TFT2 is electrically connected to the first Gate line Gate1, the drain of the second switching element TFT is electrically connected to the second sub-pixel electrode sub, and the Source of the second switching element TFT2 is electrically connected to the data line Source 1. A second voltage dividing capacitor Clc2 is further included between the drain of the second switching element TFT2 and the second sub-pixel sub, and the drain of the second switching element TFT2 is further electrically connected to the common electrode CS through a second storage capacitor Cst 2.

A third switching element TFT 3; the third switching element TFT3 may be a thin film transistor, and the Gate of the third switching element TFT3 is electrically connected to the third Gate line Gate3, the drain is electrically connected to the common electrode CS, and the source is electrically connected to the second sub-pixel electrode sub. A third storage capacitor Cst3 is further included between the source electrode of the third switching component and the second sub-pixel electrode sub.

In the array substrate as shown in fig. 8, when the pixel P11 is to be displayed, the Gate1 signal controls the TFT1 and the TFT2 to charge the first sub-pixel electrode main and the second sub-pixel electrode sub, and after the charging is completed, the TFT2 discharges the second sub-pixel electrode sub through the third storage capacitor Cst3 electrically connected to the TFT3 under the driving of the third Gate line Gate3, so that there is a difference in the operating voltages of the first sub-pixel electrode main electrically connected to the TFT1 and the second sub-pixel electrode sub electrically connected to the TFT 2. The sub-pixel electrode main can display according to the data signal of the data line Source1, and the sub-pixel electrode sub can display according to the data signal of the data line Source 1.

The present application further provides two embodiments of the array substrate, which can be used to implement the equivalent circuit diagram shown in fig. 8. The following description will be made with reference to fig. 9 and 10, respectively.

In a first embodiment, fig. 9 is a schematic structural diagram of an array substrate provided in the present application, and the structure of the array substrate shown in fig. 9 can be represented by an equivalent circuit shown in fig. 8. As shown in fig. 9, taking the first and second Pixel regions Pixel2 on the array substrate as an example, the first Pixel region Pixel1 is disposed between the first and second Gate lines Gate1 and Gate 2. The second Pixel region Pixel2 is disposed between the second Gate line Gate2 and the third Gate line Gate 3.

And in the first Pixel region Pixel1, the first sub-Pixel electrode main is adjacent to the first Gate line Gate1, the second sub-Pixel electrode sub is adjacent to the second Gate line Gate2, the first switching element TFT1 and the second switching element TFT2 are disposed on the first Gate line Gate1, and the third switching element TFT3 is disposed on the third Gate line Gate 3.

In conjunction with the structure of the liquid crystal display shown in fig. 1, the liquid crystal molecules 120 between the first sub-pixel electrode main and the common electrode 110 in the array substrate shown in fig. 9 form a first voltage dividing capacitance Clc 1; the liquid crystal molecules 120 between the second sub-pixel electrode sub and the common electrode 110 form a second divided capacitance Clc 2.

More specifically, in the present embodiment, the electrical connection between the switching elements of the first Pixel region Pixel1 and the Pixel electrodes is realized by wires and vias. The lead provided in this embodiment may be a metal lead, such as Cu and molybdenum, and on the array substrate, the lead, the via hole, and the pixel electrode are sequentially disposed on different adjacent layers, and the pixel electrode may specifically be ITO.

The Gate and drain of the first switching element TFT1 are electrically connected to the first Gate line Gate1 and the first data line Source1, respectively, and the Source of the first switching element TFT1 is electrically connected to the first sub-pixel electrode main through the lead wire 131 and the via hole 132.

The Gate and drain of the second switching element TFT2 are electrically connected to the first Gate line Gate1 and the first data line Source1, respectively, and the Source of the second switching element TFT2 is electrically connected to the second sub-pixel electrode sub through a lead 133 (denoted as a second lead) and a via 134 (denoted as a second via). A first end of the lead 133 is electrically connected to the drain of the second switching element TFT2, a second end is electrically connected to the via 134, the via 134 is disposed on the second sub-pixel electrode sub, and the via 134 is used to electrically connect the lead 133 and the second sub-pixel electrode sub. The lead line 133 is disposed in the second direction through the dark stripe region of the edge of the first sub-Pixel electrode main in the first Pixel region Pixel 1.

A Gate and a drain of the third switching element TFT3 are electrically connected to the third Gate line Gate3 and the common electrode CS, respectively, and a source of the third switching element TFT3 is electrically connected to the second sub-pixel electrode sub through a lead 135 and a via 136 (denoted as a first lead). A first end of the wire 135 is electrically connected to the source of the third switching element TFT3, and a second end of the wire 135 is electrically connected to the second via 136, the second via 136 being used to electrically connect the wire 135 and the second sub-pixel electrode sub. In particular, the second sub-pixel electrode sub is partially disposed across the second Gate line Gate2 in the present embodiment, the portion denoted by reference numeral 137 in fig. 9 being taken as an example, so that the via hole 136 disposed at the Gate2 side can be electrically connected with the portion of the second sub-pixel electrode sub disposed across the second Gate line Gate 2.

Also, the lead wire 135 provided in the embodiment of the present application is disposed through the first dark stripe region within the second Pixel region Pixel2 in the second direction. Alternatively, in the example shown in fig. 8, the first dark-stripe region is taken as an example of a dark-stripe region in the middle inside the second Pixel region Pixel 2. It is understood that the first dark stripe region may also be a dark stripe region at the inner edge of the second Pixel region Pixel 2.

In a second embodiment, fig. 10 is a schematic structural diagram of an array substrate provided by the present application, the composition of the array substrate of the embodiment shown in fig. 10 is the same as that shown in fig. 9, and the arrangement of the first switching element TFT1 and the third switching element TFT3 is the same as that shown in fig. 9, except that the second switching element TFT2 is electrically connected to the lead and the via of the second pixel electrode sub.

Specifically, in the present embodiment, a first end of the lead 133 of the lead 134 is electrically connected to the drain of the second switching element TFT2, a second end is electrically connected to the via 134, the via 134 is disposed on an extension of the second sub-pixel electrode sub, and the via 134 is used to electrically connect the lead 133 and the second sub-pixel electrode sub. The extending portion of the second sub-pixel electrode sub is disposed along the second direction in the dark fringe area at the edge of the first sub-pixel electrode main, the portion denoted by reference numeral 138 in fig. 10 is taken as an example, and there is an interval parallel to the second direction between the extending portion of the second sub-pixel electrode sub and the first sub-pixel electrode main, and the interval between the extending portion of the second sub-pixel electrode sub and the first sub-pixel electrode main is denoted by reference numeral 139 in fig. 10.

In summary, in the array substrate of the embodiment shown in fig. 7 to 10, for two sub-pixels in each pixel region, the TFT1 corresponding to the sub-pixel (i) is electrically connected to the first Gate line Gate1, the TFT2 corresponding to the sub-pixel (ii) is electrically connected to the first Gate line Gate1, and the TFT3 corresponding to the sub-pixel (ii) is electrically connected to the third Gate line Gate3, since the first Gate line Gate1 and the third Gate line Gate3 are not adjacent to each other, the adjacent Gate lines do not need to cooperatively drive the same pixel, and thus, the adjacent Gate lines can perform an early shift of the driving signal between the Gate lines before the driving of one pixel is stopped when the GOA driving is performed. For example, fig. 11 is a schematic diagram of driving signals of the array substrate provided by the present application, wherein a driving signal G1 of the first Gate line Gate1 may overlap with a signal G2 of the second Gate line Gate2, and the second Gate line Gate2 may send G2 in advance before the driving signal G1 of the first Gate line Gate1 is ended, and since the first Gate line Gate1 and the third Gate line Gate3 drive one pixel together, it is only necessary to keep the driving signal G1 of the first Gate line Gate1 and the driving signal G3 of the third Gate line Gate3 not overlap. For the same reason, the driving signal G3 may be sent earlier before the end of the driving signal G2, and the driving signal G2 may not coincide with the driving signal G4; the driving signal G4 may be sent earlier before the end of the driving signal G3, and the driving signal G3 may not coincide with the driving signal G5; the driving signal G5 may be sent earlier before the end of the driving signal G4, and the driving signal G4 may not coincide with the driving signal G6; the driving signal G6 may be sent earlier before the end of the driving signal G5, and the driving signal G5 may not coincide with the driving signal G7; the driving signal G7 may be sent earlier before the end of the driving signal G6, and the driving signal G6 and the driving signal G8 do not overlap. Finally, through the driving signals sent in advance between the adjacent gate lines, the liquid crystal display in the eight-domain display technology mode can achieve the GOA pre-charging function, the driving effect of the GOA circuit and the pixel charging rate of the liquid crystal display are improved, and the display effect of the liquid crystal display is further improved.

In the array substrate provided in fig. 7 to 11, by electrically connecting each pixel region to two non-adjacent gate lines on the array substrate and spacing one gate line between the two gate lines as an example, it can be understood that in other possible implementations, more gate lines may be spaced between the two gate lines.

For example, fig. 12 is a schematic view of a pixel structure of a liquid crystal display provided by the present application, where the basic composition of the array substrate shown in fig. 12 is the same as that shown in fig. 7, and the data lines and the gate lines are arranged in the same manner as that shown in fig. 7, except that each pixel region is electrically connected to an adjacent gate line and another gate line is spaced by two gate lines.

Specifically, the description is made by using fig. 13, where fig. 13 is a schematic equivalent circuit diagram of an array substrate provided by the present application, an equivalent circuit of an array substrate of a liquid crystal display is shown in fig. 13, and fig. 13 illustrates a pixel P11 in fig. 12, it can be seen that, in a pixel area as shown in fig. 13, a Gate of a third switching element TFT3 is electrically connected to a fourth Gate line Gate 4. The other parts in the pixel region shown in fig. 13 are the same as those shown in fig. 8, and are not described again.

Then, in the array substrate as shown in fig. 13, when the pixel P11 is displaying, the TFT1 and the TFT2 are charged by the operation signal, and after the charging is completed, under the driving of the fourth Gate line Gate4, the TFT2 is discharged through the third storage capacitor Cst3 electrically connected to the TFT3, so that there is a difference between the operation voltage of the sub-pixel electrode main electrically connected to the TFT1 and the operation voltage of the sub-pixel electrode sub electrically connected to the TFT 2. Subsequently, when the TFT1 receives the driving signal transmitted by the first Gate line Gate1, the sub-pixel electrode main can display according to the data signal of the data line Source 1; after the first TFT2 receives the driving signal transmitted by the Gate line Gate1, the sub-pixel electrode sub can display according to the data signal of the data line Source 1.

The present application further provides two embodiments of the array substrate, which can be used to implement the equivalent circuit shown in fig. 13. The following description will be made with reference to fig. 14 and 15, respectively.

In a first embodiment, fig. 14 is a schematic structural diagram of an array substrate provided herein, and the structure of the array substrate shown in fig. 14 can be represented by an equivalent circuit shown in fig. 13, as shown in fig. 14, taking as an example a first Pixel region Pixel, a second Pixel region Pixel2 and a third Pixel region Pixel3 on the array substrate, the first Pixel region Pixel1 is disposed between a first Gate line Gate1 and a second Gate line Gate2, the second Pixel region Pixel2 is disposed between a second Gate line Gate2 and a third Gate line Gate3, and the third Pixel region Pixel3 is disposed between a third Gate line Gate3 and a fourth Gate line Gate 4. And in the first Pixel region Pixel1, the first sub-Pixel electrode main is adjacent to the first Gate line Gate1, the second sub-Pixel electrode sub is adjacent to the second Gate line Gate2, the first switching element TFT1 and the second switching element TFT2 are disposed on the first Gate line Gate1, and the third switching element TFT3 is disposed on the fourth Gate line Gate 4.

More specifically, in the present embodiment, the electrical connection between the switching elements of the first Pixel region Pixel1 and the Pixel electrodes is realized by wires and vias. The lead provided in this embodiment may be a metal lead, for example, metal2, and on the array substrate, the lead, the via hole, and the pixel electrode ITO are sequentially disposed on different adjacent layers, and the pixel electrode may specifically be ITO.

The Gate and drain of the first switching element TFT1 are electrically connected to the first Gate line Gate1 and the first data line Source1, respectively, and the Source of the first switching element TFT1 is electrically connected to the first sub-pixel electrode main through the lead 141 and the via 142.

The Gate and drain of the second switching element TFT2 are electrically connected to the first Gate line Gate1 and the first data line Source1, respectively, and the Source of the second switching element TFT2 is electrically connected to the second sub-pixel electrode sub through a lead line 143 (denoted as a fourth lead line) and a via 144 (denoted as a fourth via hole). A first end of the wire 143 is electrically connected to the drain of the second switching element TFT2, a second end is electrically connected to a via 144, the via 144 is disposed on the second sub-pixel electrode sub, and the via 144 is used to electrically connect the wire 143 and the second sub-pixel electrode sub. The lead line 143 is disposed through the dark stripe region of the edge of the first sub-Pixel electrode main in the first Pixel region Pixel1 in the second direction.

A Gate and a drain of the third switching element TFT3 are electrically connected to the fourth Gate line Gate4 and the common electrode CS, respectively, and a source of the third switching element TFT3 is electrically connected to the second sub-pixel electrode sub through a lead 145 and a via 146 (denoted as a first lead). A first end of the wire 145 is electrically connected to the source of the third switching element TFT3, a second end of the wire 145 is electrically connected to the via 146, and the via 146 is used to electrically connect the wire 145 and the second sub-pixel electrode sub. The second sub-pixel electrode sub is partially disposed across the second Gate line Gate2 in the present embodiment, and the portion denoted by reference numeral 147 in fig. 14 is taken as an example, so that the via hole 146 disposed at the side of the Gate2 can be electrically connected to the portion where the second sub-pixel electrode sub is disposed across the second Gate line Gate 2.

Alternatively, in the present embodiment, the lead wire 145 is disposed sequentially through the second dark stripe region of the third Pixel region Pixel3, the third dark stripe region of the second Pixel region Pixel in the second direction, and in a portion denoted by reference numeral 148 in fig. 14, the lead wire 145 is further disposed across the third Gate line Gate 3. In the example shown in fig. 14, the second dark stripe region is the middle dark stripe region in the third Pixel region Pixel3, and the third dark stripe region is the middle dark stripe region in the second Pixel region Pixel2, and one or both of the second dark stripe region and the third dark stripe region may also be edge dark stripe regions.

For example, in a second embodiment, fig. 15 is a schematic structural diagram of an array substrate provided by the present application, and the composition of the array substrate shown in fig. 15 is the same as that shown in fig. 14, and the arrangement of the first switching element TFT1, the second switching element TFT2, and the third switching element TFT3 is the same as that shown in fig. 14, except that the lead 145 is in the third Pixel region Pixel3, and the second dark stripe region is an edge dark stripe region in the third Pixel region Pixel 3.

To sum up, in the array substrate of the embodiment shown in fig. 12 to 15, for two sub-pixels in each pixel region, the TFT1 corresponding to the sub-pixel (r) is electrically connected to the first Gate line Gate1, the TFT2 corresponding to the sub-pixel (r) is electrically connected to the first Gate line Gate1, and the TFT3 corresponding to the sub-pixel (r) is electrically connected to the fourth Gate line Gate4, since the first Gate line Gate1 and the fourth Gate line Gate4 are not adjacent to each other, the adjacent Gate lines do not need to cooperatively drive the same pixel, and thus, the adjacent Gate lines can perform an early shift of the driving signal between the Gate lines before stopping the driving of one pixel at the time of the GOA driving. For example, fig. 16 is a schematic diagram of driving signals of the array substrate provided by the present application, wherein the driving signal G1 of the first Gate line Gate1, the driving signal G2 of the second Gate line Gate2, and the driving signal G3 of the third Gate line Gate3 may overlap with each other, the second Gate line Gate2 may send G2 in advance before the driving signal G1 of the first Gate line Gate1 is ended, the third Gate line Gate3 may send G3 in advance before the driving signal G1 of the first Gate line Gate1 is ended, and since the first Gate line Gate1 and the fourth Gate line Gate4 drive one pixel together, it is only necessary to keep the driving signal G1 of the first Gate line Gate1 and the driving signal G4 of the fourth Gate line Gate 35gate 4 not to overlap with each other. For the same reason, the driving signal G3 and the driving signal G4 may be sent in advance before the end of the driving signal G2, and the driving signal G2 and the driving signal G5 do not overlap; the driving signal G4 and the driving signal G5 can be sent in advance before the end of the driving signal G3, and the driving signal G3 and the driving signal G6 do not overlap; the driving signal G5 and the driving signal G6 can be sent in advance before the end of the driving signal G4, and the driving signal G4 and the driving signal G7 do not overlap; the driving signal G6 and the driving signal G7 may be transmitted in advance before the end of the driving signal G5, and the driving signal G5 and the driving signal G8 do not overlap. Finally, the liquid crystal display in the eight-domain display technology mode can achieve the GOA pre-charging function through the driving signals sent in advance between the adjacent gate lines, compared with the mode shown in fig. 11, the pre-charging time of the GOA can be further advanced, the driving effect of the GOA circuit and the pixel charging rate of the liquid crystal display are further improved, and the display effect of the liquid crystal display is further improved.

Further, based on the array substrate provided in the above embodiments and the liquid crystal display using the array substrate, the present application also provides a driving method of the liquid crystal display, which can be applied to the liquid crystal display in any of the foregoing embodiments of the present application, or executed by a processing unit (e.g., a processor, a driver, etc.) in the liquid crystal display. Specifically, the driving method of the liquid crystal display provided by the embodiment includes:

s101: and the first switch component and the second switch component are conducted through the first grid line.

S102: the first subpixel electrode and the second subpixel electrode are charged through the data line.

S103: and controlling the third switching element to be conducted through the target gate line, so that the second sub-pixel electrode is discharged through the third switching element, and the voltages of the first sub-pixel electrode and the second sub-pixel electrode are different.

The specific implementation manner and principle of the driving method of the liquid crystal display provided by the present application are the same as those described in the foregoing embodiments, and are not repeated herein.

Further, in the driving method of the liquid crystal display described above, in order to implement the precharge function of the GOA driving, the driving method further includes:

s104: determining a first timing of a first gate driving signal transmitted to the first gate line, a second timing spaced apart by N single-row scanning times, and transmitting a second gate driving signal to the second gate line at the second timing. The second gate line is adjacent to the first gate line, the duration of the first gate signal is M single-line scanning times, the duration of the second gate signal may also be M single-line scanning times, and 0 < N < M. S104 may be performed after the liquid crystal display sends the first gate driving signal to the first gate line in S101, with an interval of N single-line scanning times, without limiting the precedence relationship with S102 and S103.

Fig. 17 is a schematic diagram illustrating the advance time of the GOA precharge time provided in the present application, wherein the duration of the first gate driving signal G1 of the first gate line is taken as four single-row scanning times, which are respectively denoted by (i) - (r), when M is 4, when the resolution of the lcd is 1080, the pixel array is correspondingly provided with 1080 rows, and when the line scanning frequency of the lcd for 1080 rows of the pixel array is 60Hz, the single-row scanning time T is 1/60/1080. Then, in the example shown in fig. 17, after the first time t1 when the liquid crystal display sends the first gate driving signal G1 to the first gate line, after two single-line scanning times with the interval of phi and phi, the second gate driving signal G2 can be sent to the second gate line at the second time t2 in advance, where N is 2.

Alternatively, the driver for transmitting the gate driving signals within the liquid crystal display may store the number N of advanced one-line scanning times in advance, and transmit the gate driving signals of the adjacent gate lines in advance of the N one-line scanning times. Alternatively, the driver of the liquid crystal display may also receive indication information sent by other devices or designers for indicating the number N of spaced single-line scanning times or the number M-N of advanced single-line scanning times, and then the driver may determine to send the gate driving signals of the adjacent gate lines in advance of N single-line scanning times according to the indication information.

Optionally, an embodiment of the present application further provides a readable storage medium, in which instructions are stored, and when the storage medium is executed on a computer, the computer is caused to execute the method performed by the liquid crystal display in the foregoing embodiment of the present application.

Optionally, an embodiment of the present application further provides a chip for executing the instruction, where the chip is used to execute the method executed by the liquid crystal display in the foregoing embodiment of the present application.

Embodiments of the present application further provide a program product, which includes a computer program, where the computer program is stored in a storage medium, and the computer program can be read from the storage medium by at least one processor, and when the computer program is executed by the at least one processor, the method performed by the liquid crystal display in the foregoing embodiments of the present application can be implemented.

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising:

a plurality of data lines arranged in parallel at intervals along a first direction;

the gate lines are arranged in parallel at intervals along a second direction, the first direction is vertical to the second direction, and the data lines and the gate lines are arranged in a crossed mode;

a plurality of pixel regions; each pixel region is positioned between two gate lines and two data lines, and is electrically connected with one data line and two gate lines;

one of the plurality of pixel regions includes a first pixel region including:

the first sub-pixel electrode and the second sub-pixel electrode are arranged between the first gate line and the second gate line and are sequentially arranged at intervals along the second direction;

the first switch component is electrically connected with the first gate line, the first sub-pixel electrode and the data line;

the second switch component is electrically connected with the first gate line, the second sub-pixel electrode, the data line and the third switch component;

a third switching element electrically connected to the second sub-pixel electrode target gate line; wherein the target gate line and the first gate line are spaced by at least one gate line.

2. The display panel according to claim 1,

the first switch assembly, the second switch assembly and the third switch assembly are all thin film transistors;

the grid electrode, the drain electrode and the source electrode of the first switch component are respectively and electrically connected with the first grid line, the first sub-pixel electrode and the data line;

the grid electrode, the drain electrode and the source electrode of the second switch component are respectively and electrically connected with the first grid line, the second sub-pixel electrode and the data line;

and the grid electrode, the drain electrode and the source electrode of the third switch component are respectively and electrically connected with the target grid line, the common electrode and the second sub-pixel electrode.

3. The display panel according to claim 2,

the target gate line is a third gate line;

wherein a second pixel region of the plurality of pixel regions is disposed between the second gate line and the third gate line.

4. The display panel according to claim 3, further comprising:

a first lead and a first via, a first end of the first lead being electrically connected to a source of the third switch component, the first lead being disposed through the first dark stripe region of the second pixel region along the second direction, a second end of the first lead being electrically connected to the first via, the first via being for electrically connecting the first lead and a portion of the second sub-pixel electrode crossing the second gate line;

the first end of the second lead is electrically connected with the drain of the second switch component, the second lead penetrates through the dark fringe area at the edge of the first pixel area in the second direction, the second end of the second lead is electrically connected with the second via, and the second via is used for electrically connecting the second lead with the second sub-pixel electrode.

5. The display panel according to claim 4, further comprising:

a second lead and a second via, wherein a first end of the second lead is electrically connected to the drain of the second switch component, a second end of the second lead is electrically connected to the second via, and the second via is used for electrically connecting the extension portion of the second sub-pixel electrode and the drain of the second switch component; wherein the extending portion of the second sub-pixel is disposed in parallel to the edge of the first pixel region along the second direction at an interval.

6. The display panel according to claim 4 or 5,

the first dark stripe area is a middle dark stripe area or an edge dark stripe area of the second pixel area.

7. The display panel according to claim 2,

the target gate line is a fourth gate line;

wherein a second pixel region of the plurality of pixel regions is disposed between the second gate line and a third gate line, and a third pixel region of the plurality of pixel regions is disposed between the third gate line and the fourth gate line.

8. The display panel according to claim 7, further comprising:

a third lead and a third via, wherein a first end of the third lead is electrically connected to a source of the third switch component, the third lead sequentially passes through a second dark stripe region of the third pixel region and a third dark stripe region of the second pixel region along the second direction, the third lead is arranged across the third gate line, a second end of the third lead is electrically connected to the third via, and the third via is used for electrically connecting the third lead and the second subpixel electrode;

the first end of the fourth lead is electrically connected with the drain of the second switch component, the fourth lead penetrates through the dark fringe area at the edge of the first pixel area in the second direction, the second end of the fourth lead is electrically connected with the fourth via, and the fourth via is used for electrically connecting the fourth lead with the second sub-pixel electrode.

9. The display panel according to claim 8,

the second dark fringe area is a middle dark fringe area or an edge dark fringe area of the third pixel area;

the third dark stripe area is a middle dark stripe area or an edge dark stripe area of the second pixel area.

10. A liquid crystal display comprising the display panel according to any one of claims 1 to 9.

11. A driving method of a liquid crystal display device applied to the display panel according to any one of claims 1 to 9, comprising:

the first switch component and the second switch component are conducted through the first grid line;

charging the first subpixel electrode and the second subpixel electrode through a data line;

and controlling the third switch component to be turned on through the target grid line, so that the second sub-pixel electrode is discharged through the third switch component, and the voltages of the first sub-pixel electrode and the second sub-pixel electrode are different.

12. The method of claim 11, further comprising:

transmitting a second gate driving signal to a second gate line at a second timing after a first timing at which a first gate driving signal is transmitted to the first gate line;

the first time and the second time are separated by N single-line scanning time, the duration of the first grid signal is M single-line scanning time, and N is more than 0 and less than M.