CN112737579A

CN112737579A - Sub-sampling phase-locked loop

Info

Publication number: CN112737579A
Application number: CN201911032046.0A
Authority: CN
Inventors: 杨育哲; 陈家源; 吕咏儒; 刘深渊
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2019-10-28
Filing date: 2019-10-28
Publication date: 2021-04-30

Abstract

The invention discloses a sub-sampling phase-locked loop, which comprises a phase detector, a charge pump, an oscillator and a buffer. In the operation of the sub-sampling phase-locked loop, the phase detector samples a feedback signal by using a reference frequency signal to generate a first phase detection result, the charge pump generates a control signal according to the first phase detection result and a pulse signal, and the oscillator generates an output frequency signal according to the control signal; and the buffer is used for receiving the output frequency signal, generating the feedback signal and controlling the revolution rate of the feedback signal according to a revolution rate control signal.

Description

Sub-sampling phase-locked loop

Technical Field

The invention relates to a sub-sampling phase-locked loop.

Background

In the pll, the bandwidth is affected by a plurality of parameters, such as the current of the charge pump, the coefficient of the frequency divider, and the gain of the vco, which are easily affected by the process-voltage-temperature (pvt) variations, resulting in unstable performance of the pll.

Disclosure of Invention

Therefore, it is an object of the present invention to provide a sub-sampling phase locked loop that provides a stable bandwidth to solve the problems described in the prior art.

In one embodiment of the present invention, a sub-sampling phase locked loop is disclosed, which includes a first phase detector, a first charge pump, an oscillator, and a first buffer. In the operation of the sub-sampling phase-locked loop, the first phase detector samples a feedback signal by using a reference frequency signal to generate a first phase detection result, the first charge pump generates a first control signal according to the first phase detection result and a pulse signal, and the oscillator generates an output frequency signal according to the first signal; and the first buffer is used for receiving the output frequency signal, generating the feedback signal and controlling the revolution rate of the feedback signal according to a revolution rate control signal.

In another embodiment of the present invention, a sub-sampling phase locked loop is disclosed, which comprises a phase detector, a pulse signal generating circuit, a charge pump, an oscillator, and a pulse width control circuit. In operation of the sub-sampling pll, the phase detector samples a feedback signal using a reference clock signal to generate a phase detection result; the pulse signal generating circuit generates a pulse signal according to the reference frequency signal; the charge pump generates a control signal according to the phase detection result and the pulse signal; the oscillator generates an output frequency signal according to the control signal; and the pulse width control circuit generates a pulse width control signal to the pulse signal generating circuit according to the output frequency signal so as to control the pulse width of the pulse signal.

Drawings

Fig. 1 is a schematic diagram of a sub-sampling phase-locked loop according to an embodiment of the invention.

Fig. 2 is a flowchart of a method for bandwidth calibration of a sub-sampling phase-locked loop according to an embodiment of the invention.

Fig. 3 is a schematic diagram of a pulse width control circuit according to an embodiment of the invention.

Fig. 4 is a schematic diagram of a buffer, a phase detection circuit and a slew rate control circuit according to an embodiment of the invention.

Detailed Description

Fig. 1 is a schematic diagram of a sub-sampling phase-locked loop (sub-sampling phase-locked loop)100 according to an embodiment of the invention. As shown in fig. 1, the sub-sampling phase-locked loop 100 includes a pulse signal generating circuit 110, a first charge pump 120, a phase detector 130, a buffer 140, an oscillator 150, a slew rate control circuit 160, a pulse width control circuit 170, a coarse frequency selection circuit 180, a phase frequency detector 192, a second charge pump 194, a frequency divider 196, capacitors CP, CS, and a resistor RS.

In the basic operation of the sub-sampling phase-locked loop 100, the pulse signal generating circuit 110 is used for receiving a reference clock signal CK _ REF to generate a pulse signal Vp; the phase detector 130 uses the reference clock signal CK _ REF to sample a feedback signal CK _ FB to generate a first phase detection result Vsam; the first charge pump 120 generates a first signal V1 for generating a control signal V _ tune to the oscillator 150 according to the first phase detection result Vsam and the pulse signal Vp, wherein the voltage V _ tune is generated by the first signal V1 combined with a second signal V2 and passing through a filter circuit; the oscillator 150 generates an output clock signal CK _ out according to a coarse clock code B _ code and the control signal V _ tune; the buffer 140 receives the output clock signal CK _ out to generate the feedback signal CK _ FB. On the other hand, the frequency divider 196 divides the output clock signal CK _ out to generate a divided output clock signal CK _ div, the phase clock detector 192 receives the reference clock signal CK _ REF and the divided output clock signal CK _ div to generate a phase clock detection result, and the second charge pump 194 generates the second signal V2 according to the phase clock detection result. It should be noted that the operations of the phase detector 192, the second charge pump 194 and the frequency divider 196 are performed to make the integer portion of the frequency of the output clock signal CK _ out correct, and the operations of the pulse signal generating circuit 110, the first charge pump 120, the phase detector 130 and the buffer 140 are performed to make the fractional portion of the frequency of the output clock signal CK _ out correct, for example, assuming that the frequency of the reference clock signal CK _ REF is 40MHz and the target of the output clock signal CK _ out is 2410MHz (multiple is 60.25), the two circuits are respectively used to lock the integer portion "60" and the fractional portion "0.25" of the multiple. It should be noted that, since the basic operations of the above components are well known to those skilled in the art, and the focus of the present invention is not herein described, further details are not provided herein.

In the sub-sampling phase-locked loop 100, the bandwidth thereof can be expressed as follows:

where gain _ SSPD refers to the gain of the phase detector 130, Gm is the transconductance of the first charge pump 120 and associated circuitry, KVCO is the gain of the oscillator 150, τ _ pul is the pulse width of the pulse signal Vp, Tref is the period of the reference frequency signal CK _ REF. In addition, the gain SSPD of the phase detector 130 may be expressed as follows:

wherein TVCO is the period of the output clock signal CK _ out. As mentioned above, since the bandwidth of the sub-sampling pll 100 is determined by the above parameters, which are easily affected by the process, voltage and temperature drift, in order to ensure that the sub-sampling pll 100 has a stable bandwidth, the slew rate control circuit 160 and the pulse width control circuit 170 are provided to respectively determine the slew rate of the feedback signal CK _ FB generated by the buffer 140 (i.e. corresponding to the equation (2))

) And the pulse width τ _ pul of the pulse signal Vp generated by the pulse signal generating circuit 110, plus the sum of (Gm × Rs) in the formula (1)) The first charge pump 120 can be designed to maintain a constant value in the prior art to achieve the above objective. The details of which are detailed in the examples below.

Fig. 2 is a flowchart illustrating a bandwidth calibration method of the sub-sampling phase-locked loop 100 according to an embodiment of the invention. Referring to the contents of fig. 1 and 2, in step 200, the process starts and the sub-sampling phase-locked loop 100 starts to operate to receive the reference clock signal CK _ REF to generate the output clock signal CK _ out. In step 202, the coarse frequency selection circuit 180 determines a coarse frequency handle B _ code for the oscillator 150 according to the output clock signal CK _ out and a target frequency of the sub-sampling phase-locked loop 100. Since the circuit structure and the related operation of the coarse frequency selection circuit 180 are well known to those skilled in the art, for example, the coarse frequency handle B _ code can be determined by using a conventional binary search method, and the content of the coarse frequency selection circuit 180 is not the focus of the present invention, the details thereof are not repeated herein.

In step 204, the pulse width control circuit 170 generates a plurality of control signals V _ tune with a plurality of different voltage levels to the oscillator 150, so that the oscillator 150 generates a plurality of output clock signals CK _ out with different frequencies, calculates the gain of the oscillator 150 according to the plurality of control signals V _ tune and the plurality of output clock signals CK _ out, determines the pulse width τ _ pul of the pulse signal Vp according to the gain of the oscillator 150, and accordingly generates a pulse width control signal P _ code to the pulse signal generating circuit 110. In detail, referring to the schematic diagram of the pulse width control circuit 170 and the oscillator 150 shown in fig. 3, the pulse width control circuit 170 includes two switches SW1 and SW2, a frequency divider 310, a counter 320, a calculating circuit 330 and a searching circuit 340, wherein VH and VL are respectively the highest voltage and the lowest voltage that the control signal V _ tune can have. In the operation of the pulse width control circuit 170, first, the pulse width control circuit 170 controls the switch SW1 to be turned on and the switch SW2 to be turned off to output the highest voltage VH as the control signal V _ tune to the oscillator 150 to generate the output clock signal CK _ out having the highest frequency. Next, the frequency divider 310 divides the output clock signal CK _ out to generate a divided output clock signal CK _ out', wherein in the present embodiment, the divisor of the frequency divider 310 may be "8". The counter 320 then counts a clock signal CK ' by using the divided output clock signal CK _ out ' to generate a first count value, wherein in the present embodiment, the clock signal CK ' can be obtained by a frequency divider (e.g., having a divisor of "128") dividing the reference clock signal CK _ REF. At this time, the first count value received by the calculating circuit 330 may reflect the highest frequency value fH of the output frequency signal CK _ out corresponding to the highest voltage VH. Then, the pulse width control circuit 170 operates similarly to control the switch SW2 to be turned on and the switch SW1 to be turned off, so as to output the lowest voltage VL as the control signal V _ tune to the oscillator 150 to generate the output clock signal CK _ out with the lowest frequency, and operates through the frequency divider 310 and the counter 320 to generate a second count value, wherein the second count value reflects the lowest frequency fL of the output clock signal CK _ out corresponding to the lowest voltage VL. Next, the calculation circuit 330 may calculate the gain KVCO of the oscillator 150 using the following equation:

KVCO＝(fH-fL)/(VH-VL)……………………………………………………(3)

after calculating the gain KVCO of the oscillator 150, the lookup circuit 340 may use a look-up table to determine the pulse width control signal P _ code such that the product of the gain KVCO of the oscillator 150 and the pulse width τ _ pul of the pulse signal Vp is a fixed value.

In step 206, the slew rate control circuit 160 generates a slew rate control signal S _ code according to the phase detection result Vsam' generated by the phase detector 130 to control the buffer 140 to generate the feedback signal CK _ FB. In detail, refer to the schematic diagram of the buffer 140, the phase detector 130 and the slew rate control circuit 160 shown in fig. 4. In FIG. 4, the output clock signal CK _ out includes the differential signal CK _ outp and the differential signal CK _ outn, the buffer 140 includes a first buffer 140_1 and a second buffer 140_2, wherein the second buffer 140_2 is a replica of the first buffer 140_1 (i.e., has the same structure and size), and

includesThe buffer circuits

402 and 404 and the switch resistors R1 and R2 coupled to the supply voltage VDD and the ground voltage; the phase detector 130 includes a first phase detector 130_1 and a second phase detector 130_2, wherein the second phase detector 130_2 is a replica circuit of the first phase detector 130_1, wherein the first phase detector 130_1 includes a plurality of switches SW3 and capacitors C1 and C2 for sampling the feedback signal CK _ FB output by the first buffer 140_1 by using the reference clock signal CK _ REF to generate a first phase detection result Vsam (including the differential signals Vsamp and Vsamp), and the second phase detector 130_2 includes a plurality of switches SW3 'and capacitors C1' and C2 'for directly using the feedback signal CK _ FB as the second phase detection result Vsam' (including the differential signals Vsamp 'and Vsamp'). The slew rate control circuit 160 comprises a peak detection circuit 410, a comparator 420, a counter 430 and a frequency divider 440, wherein the peak value Vpk of the second phase detection result Vsam' is detected by the peak detection circuit 410, the peak value Vpk is compared with a reference value Vpkref by the comparator 420 to generate a comparison result, and the counter 430 counts the comparison result using the divided frequency signal generated by the frequency divider 440 dividing the reference frequency signal CK _ REF, to generate a slew rate control signal S _ code to control slew rates in the first buffer 140_1 and the second buffer 140_2, for example, the amount of current flowing into the snubber circuit 402 or the snubber circuit 404 in FIG. 4 is adjusted or the equivalent resistance of the switch resistor is adjusted, to control the amplitudes of the first and second phase detection results Vsam and Vsam' such that equation 2 shows.

Maintained at a default value.

It should be noted that the purpose of the first buffer 140_1 and the second buffer 140_2 and the first phase detector 130_1 and the second phase detector 130_2 in fig. 4 is to provide the sub-sampling phase-locked loop 100 with background correction during normal operation to adjust the slew rate in the first buffer 140_1 and the second buffer 140_ 2.

As described above, the slew rate control circuit 160 and the pulse width control circuit 170 in the above embodiment can make the gain _ SSPD and (KVCO τ _ pul) in the formula (1) be a fixed value, so that the bandwidth of the sub-sampling phase-locked loop 100 is not affected by the process, voltage and temperature offset.

It should be noted that, although the slew rate control circuit 160 and the pulse width control circuit 170 are included in the embodiment shown in fig. 1, this feature is not a limitation of the present invention, and in other embodiments of the present invention, the sub-sampling phase-locked loop 100 may include only one of the slew rate control circuit 160 and the pulse width control circuit 170, which may also improve the bandwidth offset problem of the sub-sampling phase-locked loop 100, and these related variations all fall into the scope of the present invention.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made within the scope of the claims of the present invention should be covered by the present invention.

[ notation ] to show

100-time sampling phase-locked loop

110 pulse signal generating circuit

120 first charge pump

130 phase detector

130_1 first phase detector

130_2 second phase detector

140 buffer

140_1 first buffer

140_2 second buffer

150 oscillator

160 slew rate control circuit

170 pulse width control circuit

180 coarse frequency selection circuit

192 phase frequency detector

194 second charge pump

196. 310, 440 frequency divider

200. 202, 204, 206 steps

320. 430 counter

330 calculating circuit

340 lookup circuit

402. 404 buffer circuit

410 peak detection circuit

420 comparator

CP, CS, C1, C2, C1 'and C2' capacitors

RS, R1, R2 resistance

CK _ REF reference frequency signal

CK _ out output frequency signal

CK _ outp, CK _ outn differential signals

CK _ FB feedback signal

CK _ div, CK _ out' frequency-divided output frequency signal

CK' frequency signal

B _ code coarse frequency handle

P _ code pulse width control signal

S _ code slew rate control signal

SW1, SW2, SW3 and SW 3' switches

Vp pulse signal

Vpkref reference value

V1 first signal

V2 second signal

Vsam first phase detection result

Vsam' second phase detection result

Vsamp, Vsamp differential signal

Vsamp ', Vsamp' differential signal

V _ tune control signal

Maximum voltage of VH

Minimum voltage VL

VDD supply voltage

KVCO gain.

Claims

1. A sub-sampling phase-locked loop includes:

a first phase detector for sampling a feedback signal using a reference clock signal to generate a first phase detection result;

a first charge pump, coupled to the first phase detector, for generating a first signal according to the first phase detection result and a pulse signal;

an oscillator, coupled to the first charge pump, for generating an output clock signal according to the first signal; and

the first buffer is coupled to the oscillator and used for receiving the output frequency signal and generating the feedback signal, and the first buffer generates the slew rate of the feedback signal according to a slew rate control signal.

2. The subsampling phase locked loop of claim 1, further comprising:

a second buffer for receiving the output clock signal and generating another feedback signal according to the slew rate control signal;

a second phase detector for sampling the other feedback signal using the reference clock signal to generate a second phase detection result; and

a slew rate control circuit for generating the slew rate control signal according to the second phase detection result.

3. The subsampled pll of claim 2, wherein the second buffer is a replica of the first buffer and the second phase detector is a replica of the first phase detector.

4. The sub-sampling phase-locked loop of claim 2, wherein the slew rate control circuit detects a peak value of the second phase detection result to generate the slew rate control signal.

5. The subsampling phase locked loop of claim 1, further comprising:

a pulse signal generating circuit for generating the pulse signal according to the reference clock signal; and

and the pulse width control circuit is used for generating a pulse width control signal to the pulse signal generating circuit according to the output frequency signal so as to control the pulse width of the pulse signal.

6. The sub-sampling PLL of claim 5, wherein the PWM control circuit generates a plurality of first signals with different voltage levels to the oscillator during a calibration phase to enable the oscillator to generate a plurality of output clock signals with different frequencies, calculates a gain of the oscillator according to the plurality of first signals and the plurality of output clock signals, and determines the pulse width of the pulse signal according to the gain of the oscillator.

7. The sub-sampling PLL of claim 6, wherein the pulse width control circuit determines the pulse width of the pulse signal according to the gain of the oscillator such that the product of the gain of the oscillator and the pulse width of the pulse signal is a predetermined value.

8. The subsampling phase locked loop of claim 1, further comprising:

a phase frequency detector for receiving the reference frequency signal and a divided output frequency signal to generate a phase frequency detection result; and

a second charge pump, coupled to the phase frequency detector, for generating a second signal according to the phase frequency detection result;

the oscillator generates an output frequency signal according to the first signal and the second signal.

9. A sub-sampling phase-locked loop includes:

a phase detector for sampling a feedback signal using a reference clock signal to generate a phase detection result;

a pulse signal generating circuit for generating a pulse signal according to the reference clock signal;

a charge pump, coupled to the phase detector, for generating a control signal according to the phase detection result and the pulse signal;

an oscillator, coupled to the charge pump, for generating an output frequency signal according to the control signal; and

10. The sub-sampling pll of claim 9, wherein the pwm control circuit generates a plurality of control signals with different voltage levels to the oscillator during a calibration phase, such that the oscillator generates a plurality of output clock signals with different frequencies, calculates the gain of the oscillator according to the plurality of control signals and the plurality of output clock signals, and determines the pulse width of the pulse signal according to the gain of the oscillator.