CN112736059A

CN112736059A - Semiconductor package and method of manufacturing the same

Info

Publication number: CN112736059A
Application number: CN201910973702.0A
Authority: CN
Inventors: 呂文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2019-10-14
Filing date: 2019-10-14
Publication date: 2021-04-30

Abstract

Embodiments of the present disclosure relate to a semiconductor package including a substrate, conductive pillars, and a metal layer. The substrate has a first surface, a second surface opposite the first surface, and an opening extending from the first surface to the second surface. The opening has a side wall, and the guide pillar is disposed in the opening. The metal layer is disposed in the substrate. The metal layer is at substantially the same level as the conductive pillars. Another embodiment of the present disclosure relates to a method of manufacturing a semiconductor package.

Description

Semiconductor package and method of manufacturing the same

Technical Field

The present invention relates to semiconductor packages and methods of fabricating the same, and more particularly, to semiconductor packages having a metal layer and an insulating layer encapsulating the metal layer.

Background

As the demand for high line density per unit volume increases, line Width/Space (L/S) reduction is a method of increasing line density per unit volume. However, as the line width is reduced, short circuits may be caused by the inevitable edge-bulging effect (drum-side effect) during solder bonding, which is often ignored in the past for wider-spaced (e.g., greater than 20 μm) structures.

Disclosure of Invention

Embodiments of the present disclosure relate to a semiconductor package. The semiconductor package includes a substrate, conductive pillars, and a metal layer. The substrate has a first surface, a second surface opposite the first surface, and an opening extending from the first surface to the second surface. The opening has a side wall, and the guide pillar is disposed in the opening. The metal layer is disposed in the substrate. The metal layer is at substantially the same level as the conductive pillars.

Embodiments of the present disclosure relate to a semiconductor package. The semiconductor package includes a substrate, an insulating layer, and a metal layer. The substrate has a first surface, a second surface opposite the first surface, and an opening extending from the first surface to the second surface. The opening has a sidewall. The insulating layer has a first surface substantially coplanar with the first surface of the substrate. The metal layer is disposed in the substrate and is in contact with the insulating layer.

Embodiments of the present disclosure relate to a method of manufacturing a semiconductor package, including providing a carrier; forming an insulating layer on the carrier; forming a metal layer on the insulating layer; forming a substrate on the carrier to cover the insulating layer and the metal layer; and forming a first opening in the substrate to expose a portion of the surface of the carrier.

Drawings

Various aspects of at least one embodiment are discussed below with reference to the accompanying drawings, which are not intended to be drawn to scale. Where technical features in the figures, embodiments or any claims are accompanied by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the figures, embodiments or claims. Accordingly, the absence or presence of a reference sign is not intended to have a limiting effect on the scope of any claim element. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. The figures are provided for purposes of illustration and explanation and are not to be construed as a definition of the limits of the present invention. In the figure:

fig. 1 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure;

fig. 2 illustrates a perspective view of a semiconductor package according to some embodiments of the present disclosure;

fig. 3 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure;

fig. 4 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure;

FIGS. 5A-5M illustrate one or more stages in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure; and

fig. 6A and 6B illustrate various types of semiconductor packages according to some embodiments of the present disclosure.

Detailed Description

According to some embodiments, the present invention provides a semiconductor package that combines fine pitch interconnect structures embedded within a single dielectric layer and separated from conductive contacts by an insulating layer with coarse pitch interconnect structures. Therefore, the generation of tin bridge can be avoided. In addition, the circuit density per unit volume can be improved by using only a single dielectric layer without using a multi-layer structure, which reduces the thickness and manufacturing cost of the semiconductor packaging device and can avoid the warping (warping) phenomenon caused by the increase of the thickness.

Referring to fig. 1, fig. 1 illustrates a cross-sectional view of a semiconductor package 1 according to some embodiments of the present disclosure. The semiconductor package 1 includes a substrate 10, conductive contacts 11, a seed layer 12, a metal layer 13, conductive pillars 14, a metal layer 15, electrical connectors 16, electronic components 17, underfills 18, a package body 19, and an insulating layer 101.

In some embodiments, the substrate 10 may include, but is not limited to, solder mask (PI), Polyimide (PI), ABF substrate (ABF), molding compound (molding compound), pre-impregnated composite fibers (e.g., prepreg), borosilicate glass (BPSG), silicon oxide (silicon oxide), silicon nitride (silicon nitride), silicon oxynitride (silicon oxide), doped silicate glass (USG), combinations thereof, or the like. Examples of molding compounds may include, but are not limited to, epoxy resins (containing fillers dispersed therein). Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating a plurality of prepregs and/or sheets (sheets).

The substrate 10 has a surface 10a, a surface 10b opposite to the surface 10a, and a surface 10s connecting the surface 10a and the surface 10 b. Surface 10a forms an internal chamfered corner 10c with surface 10 s. In some embodiments, the internal lead angle 10c is between 0 degrees and 90 degrees. In some embodiments, the internal lead angle 10c is less than 80 degrees. In some embodiments, the internal lead angle 10c is less than 70 degrees. In some embodiments, the internal lead angle 10c is less than 65 degrees. The substrate 10 has an opening extending through it from the surface 10a to the surface 10b, the surface 10s forming the side walls of said opening. In some embodiments, surface 10s has a single slope, e.g., surface 10s has a substantially equal slope from surface 10a to surface 10 b. In some embodiments, the opening tapers from surface 10b to surface 10 a. For example, the opening width of the surface 10b is larger than that of the surface 10 a. In some embodiments, the substrate 10 may have a thickness of about 2.5 microns to about 10 microns.

The conductive pillars 14 are disposed in the openings of the substrate 10. For example, the conducting pillar 14 is located between the surface 10a and the surface 10b, is in contact with the surface 10s, and is surrounded by the surface 10 s. The conducting post 14 is spaced a distance from the surface 10 a. The conductive pillars 14 comprise

layers

14a, 14b, and 14c in a direction from the surface 10b to the surface 10 a. In some embodiments, any of

layers

14a, 14b, and 14c may include, but are not limited to, copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys. For example, layer 14a may be a tie layer comprising copper, gold, silver, or aluminum. Layer 14b may be a buffer layer comprising nickel, titanium, or tungsten. Layer 14c may be a solder layer (solder layer) comprising tin, copper, gold, silver, or aluminum.

Conductive contacts 11 are formed on surface 10a and are electrically connected to conductive posts 14. Conductive contact 11 includes a portion 11a and a portion 11 b. The portion 11a is surrounded by the substrate 10 and is in contact with the sidewall 10s, and the portion 11b protrudes from the surface 10a and the portion 11 a. The conductive contacts 11 are surrounded by and in contact with the inner chamfered corners 10 c. In some embodiments, conductive contacts 11 may include, but are not limited to, solder balls or Land Grid Array (LGA) packaging.

Metal layer 15 is located in substrate 10 and at substantially the same level as conductive pillars 14. For example, the metal layer 15 and the conductive pillars 14 are located between the

surfaces

10a and 10 b. The metal layer 15 is spaced a distance from the surface 10 a. The metal layer 15 and the conductive pillars 14 are surrounded by the substrate 10 (e.g., the same substrate 10, a single substrate 10) and are spaced apart from each other by a distance. For example, a portion of substrate 10 is located between metal layer 15 and conductive pillar 14. In the direction from the surface 10b to the surface 10a, the metal layer 15 includes a layer 15a and a layer 15 b. In some embodiments, either of

layers

15a and 15b may include, but is not limited to, copper, gold, silver, aluminum, nickel, titanium, tungsten, tin, or other metals or alloys. In some embodiments, the pitch (e.g., L/S) of the metal layers 15 is less than the pitch of the seed layer 12 and the metal layer 13 embedded within the package 19. In some embodiments, the pitch (e.g., L/S) of the metal layers 15 is less than 7/7 microns, less than 2/2 microns, or less. In some embodiments, the metal layer 15 may form a redistribution layer (RDL).

The insulating layer 101 is located between the surface 10a of the substrate 10 and the metal layer 15. The insulating layer 101 and the substrate 10 surround the metal layer 15. The insulating layer 101 insulates and separates the metal layer 15 and the conductive contact 11 from each other. The insulating layer 101 has a surface 101a substantially coplanar with the surface 10a of the substrate 10 and a surface 101b opposite the surface 101 a. The metal layer 15 is in contact with the surface 101 b. The metal layer 15 is located between the surface 101b and the surface 10b of the substrate 10. In some embodiments, the insulating layer 101 may be of a material as listed above for the substrate 10, such as an epoxy resin containing a filler, which may be, for example, of the type in particulate form, network form, cross-grid form, and the like.

The insulating layer 101 may have the same or different material as the substrate 10. In some embodiments, an interface 101i is formed between the insulating layer 101 and the substrate 10, and is substantially coplanar with a side surface of the metal layer 15. For example, the insulating layer 101 and the metal layer 15 are substantially equal in width. In some embodiments, the insulating layer 101 may have a thickness of about 1 micron to about 3 microns. In some embodiments, the insulating layer 101 and the metal layer 15 may have a thickness of about 1 micron to about 3 microns.

With continued reference to fig. 1, a seed layer 12 and a metal layer 13 are located on the surface 10b and electrically connected to the conductive pillars 14. In some embodiments, seed layer 12 and metal layer 13 may be of materials as listed above for metal layer 15. The seed layer 12 and the metal layer 13 may be completely covered or encapsulated by the package 19, as shown in fig. 1. In some embodiments, a portion of the seed layer 12 and the metal layer 13 may be exposed from the encapsulant 19, and the exposed portion may be further connected to other electronic components or other lines.

An electronic component 17 is disposed on the surface 10b of the substrate 10. The electronic components 17 may be active components, passive components, or a combination thereof. The active component may be an Integrated Chip (IC) or a die. The passive component may be a capacitor, a resistor, or an inductor. The electronic component 17 may be electrically connected to the remaining one or more electronic components, the substrate 10 (e.g., connecting RDLs), or the conductive pillars 14. The electrical connections may be made by flip chip or wire bonding techniques. For example, the electrical connector 16 electrically connects the electronic component 17 and the metal layer 13. The electronic component 17 is electrically connected to the conductive pillars 14 through the electrical connection members 16 and the metal layer 13.

One or more electrical connections 16 are attached to a surface of an electronic component 17. The electrical connections 16 may be, for example, conductive pads, solder balls, copper pillars, micro bumps (μ Bump), other possible electrical connections, or combinations thereof. The electrical connections 16 may be covered or encapsulated by an underfill 18.

The underfill 18 may include, but is not limited to, an epoxy, a molding compound (e.g., an epoxy molding compound or other molding compound), a PI, a phenolic compound or material, a material including silicone dispersed therein, a non-conductive paste (NCP), or a non-conductive film (NCF).

The electronic component 17 is covered or encapsulated by an encapsulation 19. The electronic component 17 may be covered or encapsulated by the package 19 with a top portion exposed from the package 19, as shown at 1. In some embodiments, the electronic component 17 may be completely covered or encapsulated by the package 19 with a top portion thereof not exposed by the edge-by-package 19.

In some embodiments, the encapsulant 19 comprises an epoxy, a molding compound (e.g., an epoxy molding compound or other molding compound), a PI, a phenolic compound or material, a material comprising silicone dispersed therein, an NCP, or an NCF. In some embodiments, the encapsulant 19 is of the same material as the underfill 18. In some embodiments, the encapsulant 19 and the underfill 18 are of different materials.

Although the figures of the present disclosure depict a single dielectric layer (e.g., a single layer of substrate 10), the semiconductor package of the present invention may have more than one dielectric layer, e.g., an interposer (interposer) between the substrate 10 and the package body 19, and any number of layers of RDLs may be included in the interposer.

Referring to fig. 2, fig. 2 illustrates a perspective view of a semiconductor package 2 according to some embodiments of the present disclosure. In the drawings of the present disclosure, the same or similar elements are denoted by the same reference numerals, and detailed description thereof will not be repeated.

As shown in fig. 2, the substrate 10 has a surface 10a and a surface 10b opposite to the surface 10 a. The substrate 10 has a relatively upper layer and a relatively lower layer. The metal layer 15 is located in a relatively lower layer of the substrate 10 and covers or encapsulates the insulating layer 101 and the substrate 10. The conductive line 21w is located on the surface 10b of the substrate 10 and connected to the contact 21a and the contact 21 b. The contacts 21a and/or 21b may further be electrically connected to other electronic components (e.g., the electronic component 17 shown in fig. 1, not shown in fig. 2) and the conductive contacts 11.

Metal layer 15 forms a line (e.g., RDL) in substrate 10, and insulating layer 101 extends with metal layer 15, e.g., insulating layer 101 covers the bottom of metal layer 15.

The metal layer 15 extends in a lower layer and has an end connected to the contact 21a through a conductive via (conductive via), and the contact 21a is connected to the contact 21b through a wire 21 w. The arrangement of lines and components shown in fig. 2 is an illustrative example only, and the present invention is not limited thereto. The configuration of the insulating layer 101 and the metal layer 15 may vary according to requirements and device specifications. For example, in other embodiments, the metal layer 15 may be directly connected to the contact 21b at the opposite lower layer. In other embodiments, the metal layer 15 may be directly connected to the conductive contact 11 at the opposite lower layer.

Referring to fig. 3, fig. 3 illustrates a cross-sectional view of a semiconductor package 3 according to some embodiments of the present disclosure. The semiconductor package 3 of fig. 3 is similar to the semiconductor package 1 of fig. 1, except that the inner concave lead 10c of the semiconductor package 1 of fig. 1 is an acute angle, and the inner concave lead 10c of the semiconductor package 3 of fig. 3 has a rounded corner or a rounded corner-like shape. For example, the portion contacting the conductive contact 11 is arc-shaped, or has an end point of arc-shape. The rounded design helps to avoid stress concentration at the tip of the lead-in fillet 10c and improves resistance to lateral stress. The lead angle 10c of the semiconductor package 3 may be shaped by dry etching (dry etching), ion bombardment (ion bumping), or other feasible methods.

Referring to fig. 4, fig. 4 illustrates a cross-sectional view of a semiconductor package 4 according to some embodiments of the present disclosure. The semiconductor package 4 of fig. 4 is similar to the semiconductor package 1 of fig. 1, and differs therefrom in that the metal layer 15 of the semiconductor package 1 of fig. 1 is a relatively small-sized trace (trace), and the metal layer 15 of the semiconductor package 4 of fig. 4 is a relatively large-sized pad (pad). The dimensions of the metal layer 15 may vary according to requirements and device specifications. Since the metal layer 15 is isolated from the conductive contact 11 by the insulating layer 101, the short circuit between the metal layer 15 and the conductive contact 11 can be avoided, so the distance between the metal layer 15 and the conductive contact 11 can be smaller, and the size of the metal layer 15 can be designed to obtain a larger flexible space.

Referring to fig. 5A through 5M, fig. 5A through 5M illustrate one or more stages in a method of manufacturing a semiconductor package according to some embodiments of the present disclosure.

Referring to fig. 5A, a carrier 20 is provided, and an insulating layer 101 is formed on the carrier 20. The carrier 20 may be a printed circuit board such as a paper-based copper foil laminate (copper-based) or a composite copper foil laminate (polymer-impregnated glass-based copper foil laminate). In some embodiments, the carrier 20 may be a copper plate or other conductive carrier. In some embodiments, the carrier 20 may be non-conductive but have a metal foil on its upper surface. In some embodiments, the carrier 20 may include an internal connection structure, such as an RDL.

Referring to fig. 5B, a layer (e.g., seed layer) 15a and a layer 15B of the metal layer 15 are formed on the insulating layer 101. In some embodiments, layer 15a may be formed by sputtering (sputtering) titanium and copper (Ti/Cu) or TiW. In some embodiments, the layer 15a may be formed by electroless plating (electroless plating) of Ni or Cu. Layer 15b is formed on layer 15a, and in some embodiments, layer 15b may be formed by electroplating (plating) Ni, Cu, Ag, Au, or other metals. In some embodiments, layer 15b may be formed by electroless plating of Ni, Pb, or other metals. In some embodiments, layer 15b may be formed by printing (printing) Cu, Ag, Au, or other metals.

Referring to fig. 5C, the metal layer 15 and the insulating layer 101 are patterned and the substrate 10 is coated to cover or encapsulate the patterned metal layer 15 and the insulating layer 101. The surface 10a of the substrate 10 contacts the carrier 20. In some embodiments, the metal layer 15 and the insulating layer 101 may be patterned by photoresist (photoresist) and photolithography (photolithography techniques).

Referring to fig. 5D, an opening 10r1 is formed in the substrate 10 to expose a portion of the carrier 20. In some embodiments, the opening 10r1 may be formed through a photoresist and using photolithography techniques. The opening 10r1 is spaced apart from the patterned metal layer 15 and the insulation 101. The opening 10r1 tapers from the body surface 10b to the body surface 10 a. In some embodiments, the exposed portion of the surface of the support 20 is a conductive surface. A seed layer is not formed along the exposed portion of the surface of the carrier 20 and the sidewalls of the opening 10r1 prior to forming the sacrificial layer 14d in fig. 5E, so that the subsequent horizontal stack of the sacrificial layer 14d and the

layers

14a, 14b, and 14c of the conductive pillar 14 is formed. Referring to fig. 5E, a sacrificial layer 14d is formed on the exposed portion of the carrier 20 in the opening 10r1, and the conductive pillar 14 is formed on the sacrificial layer 14d in the opening 10r 1. In some embodiments, the sacrificial layer 14d may include, but is not limited to, copper, gold, silver, aluminum, nickel, titanium, or other metals or alloys. The conductive pillars 14 include a layer 14a, a layer 14b, and a layer 14 c. In some embodiments, the conductive pillars 14 may be formed by applying a voltage to the carrier 20 to plate a conductive material in the openings 10r 1.

Referring to fig. 5F, a seed layer 12 is formed on the conductive pillars 14 and the carrier 20. The seed layer 12 is conformally (conformally) deposited over the conductive pillars 14 and the carrier 20. In some embodiments, seed layer 12 may be formed using, for example, a layer 15a that forms metal layer 15.

Referring to fig. 5G, a photoresist 13p is formed on the seed layer 12.

Referring to fig. 5H, the photoresist 13p is patterned such that portions of the seed layer 12 are exposed from the photoresist 13 p. A metal layer 13 is formed on the exposed portion of the seed layer 12. In some embodiments, metal layer 13 may be formed using, for example, layer 15b that forms metal layer 15.

Referring to fig. 5I, the photoresist 13p is removed.

Referring to fig. 5J, an electrical connection is formed on the metal layer 13, which includes a portion 16a and a portion 16 b. Either of

portions

16a and 16b may be, for example, conductive pads, solder balls, copper pillars, micro-bumps, other possible electrical connections, or a combination thereof. In some embodiments, electrical connections may be formed on the exposed metal layer 13 through a photoresist and using photolithography techniques.

Referring to fig. 5K, electronic component 17 is connected to portion 16a and portion 16b, forming electrical connection 16 therebetween. An underfill 18 is formed to encapsulate the electrical connectors 16. An encapsulation 19 is formed on the substrate 10 to encapsulate the electronic component 17. In some embodiments, the package body 19 and the underfill 18 are integrally formed, for example, using the same material and in the same process step and by the same process technology. In some embodiments, the package body 19 and the underfill 18 are formed in different process steps by the same or different process techniques. The underfill 18 may be formed by a capillary tube. The package body 19 may be formed by a molding technique such as a transfer molding or a press molding.

Referring to fig. 5L, the carrier 20 and the sacrificial layer 14d are removed to form an aperture 10r2 and an inner-recessed guide 10c, and the conductive pillar 14 is exposed from the substrate 10. In some embodiments, the aperture 10r2 may be formed by an etching technique, a drilling technique, or a laser drilling technique.

Referring to fig. 5M, conductive contact 11 is formed on conductive post 14 in aperture 10r2, conductive contact 11 including portion 11a and portion 11 b. The portion 11a is surrounded by the substrate 10. A separation (singulation) step is performed to separate the individual semiconductor packages. That is, the separation step is through the package 19 and the substrate 10. The separation step may be accomplished by a dicing saw, laser, or other suitable cutting technique.

Referring to fig. 6A and 6B, fig. 6A and 6B illustrate various types of semiconductor packages according to some embodiments of the present disclosure.

As shown in fig. 6A, a plurality of chips 60 and/or dies are disposed on a square carrier 61. In some embodiments, the chip 60 may include the semiconductor packages 1-4 shown in fig. 1, 2, 3, and 4. In some embodiments, carrier 61 may comprise an organic material (e.g., BT Resin (bissmeimide Triazine Resin), polypropylene (PP), ABF) or an inorganic material (e.g., glass, silicon, ceramic, metal, etc.).

As shown in fig. 6B, a plurality of chips 60 and/or dies are disposed on a circular carrier 62. In some embodiments, the carrier 62 may comprise an organic material (e.g., BT Resin (bissmeimide Triazine Resin), polypropylene (PP), ABF) or an inorganic material (e.g., glass, silicon, ceramic, metal, etc.).

It is to be understood that the embodiments of the methods and apparatus discussed herein are not limited in application to the details of construction and the arrangement of components set forth in the following description or illustrated in the following drawings. The methods and apparatus are capable of other embodiments and of being practiced or of being carried out in various ways. Examples of specific implementations are provided herein for illustrative purposes only and are not intended to be limiting. In particular, acts, elements, and features discussed in connection with any one or more embodiments are not intended to be excluded from a similar role in any other embodiments.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. Any reference to an embodiment or element or act of the systems and methods herein referred to in the singular may also include embodiments comprising a plurality of such elements, and any reference to any embodiment or element or act herein in the plural may also include embodiments comprising only a single element. References in the singular or plural form are not intended to limit the presently disclosed systems or methods, components, acts or elements thereof. The use of "including," "comprising," "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. References to "or" may be considered inclusive such that any item using "or" may indicate a single, more than one, and all of the described items. Any reference to front and back, left and right sides, top and bottom, upper and lower, and vertical and horizontal is intended for convenience of description, without limiting the present systems and methods, or components thereof, to any one position or spatial orientation.

Having thus described several aspects of at least one embodiment, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the scope of the invention. Accordingly, the foregoing description and drawings are by way of example only, and the scope of the invention should be determined from the proper construction of the appended claims and their equivalents.

Description of the symbols

1 semiconductor package

2 semiconductor package

3 semiconductor package

4 semiconductor package

10 substrate

10a surface

10b surface

10c inner concave lead angle

10r1 opening

10r2 pore space

10s surface

11 conductive contact

Part 11a

Part 11b

12 seed layer

13 Metal layer

13p photoresist

14 conductive post

14a layer

14b layer

14c layer

14d sacrificial layer

15 Metal layer

Part 15a

Part 15b

16 electric connector

Part 16a

Part 16b

17 electronic assembly

18 underfill

19 Package

20 vector

21a contact

21b contact

21w conductor

60 chip

61 Carrier

62 Carrier

101 insulating layer

101a surface

101b surface

101i interface

Claims

1. A semiconductor package comprising:

a substrate having a first surface, a second surface opposite the first surface, and an opening extending from the first surface to the second surface, wherein the opening has a sidewall;

a guide post disposed in the opening; and

a metal layer disposed in the substrate;

wherein the metal layer is at substantially the same level as the conductive pillars.

2. The semiconductor package of claim 1, wherein the metal layer is located between the first surface of the substrate and the second surface of the substrate.

3. The semiconductor package of claim 1, further comprising an insulating layer having a first surface substantially coplanar with a first surface of the substrate and a second surface opposite the first surface, wherein the second surface contacts the metal layer.

4. A semiconductor package as recited in claim 3, wherein the insulating layer and the substrate have an interface therebetween that is substantially coplanar with a side surface of the metal layer.

5. The semiconductor package of claim 1, wherein the metal layer and the conductive pillar are surrounded by a single substrate and are spaced a distance from each other.

6. The semiconductor package of claim 1, wherein the sidewalls contact and surround the conductive pillars.

7. The semiconductor package of claim 1, wherein the opening is tapered from the second surface of the substrate to a first surface of the substrate.

8. The semiconductor package of claim 1, further comprising:

a carrier in contact with the first surface of the substrate.

9. The semiconductor package of claim 8, wherein the carrier comprises a conductive material.

10. A semiconductor package, comprising:

an insulating layer having a first surface substantially coplanar with the first surface of the substrate; and

a metal layer disposed in the substrate and in contact with the insulating layer.

11. The semiconductor package of claim 10, further comprising:

a guide post disposed in the opening;

wherein the conductive pillars are located at substantially the same level as the metal layer.

12. The semiconductor package of claim 11, wherein the metal layer and the conductive pillar are surrounded by a single substrate and are spaced a distance from each other.

13. The semiconductor package of claim 11, further comprising:

a conductive contact having a first portion disposed in the opening and a second portion protruding from the first surface.

14. The semiconductor package of claim 10, wherein the metal layer is located in a direction between the first surface of the insulating layer and the second surface of the substrate.

15. A method for manufacturing a semiconductor package includes:

providing a vector;

forming an insulating layer on the carrier;

forming a metal layer on the insulating layer;

forming a substrate on the carrier to cover the insulating layer and the metal layer; and

a first opening is formed in the substrate to expose a portion of the surface of the carrier.

16. The method of manufacturing a semiconductor package according to claim 15, further comprising:

forming a sacrificial layer in the first opening on the exposed surface of the carrier; and

and forming a transmission guide pillar on the sacrificial layer.

17. The method of claim 16, wherein forming the conductive pillars comprises applying a voltage to the carrier and plating a conductive material in the first openings.

18. The method of manufacturing a semiconductor package according to claim 16, further comprising:

a seed layer is formed on the conductive pillar and the substrate.

19. The method of manufacturing a semiconductor package according to claim 16, further comprising:

forming a packaging layer on the substrate; and

and removing the sacrificial layer.

20. The method of manufacturing a semiconductor package according to claim 19, further comprising:

forming a conductive contact on an opposite side of the substrate relative to the encapsulation layer, wherein the conductive contact is in contact with the conductive post, the conductive contact being partially surrounded by the substrate.