CN112732632A

CN112732632A - System, method and medium for fast access of optical module of switch

Info

Publication number: CN112732632A
Application number: CN202110059511.0A
Authority: CN
Inventors: 郭雷
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2021-01-18
Filing date: 2021-01-18
Publication date: 2021-04-30

Abstract

The invention discloses a rapid access system for an optical module of a switch, which comprises a CPU, a BMC, a switch chip, an expansion chip module and a plurality of optical modules, wherein the BMC is used for storing a plurality of optical modules; the BMC is connected with the expansion chip through the switch chip, and the expansion chip module is connected with the plurality of optical modules; the method realizes that the BMC acquires the information of a plurality of optical modules; the CPU is connected with the enabling end of the switch chip to control the opening and closing of the switch chip; the CPU is connected with the BMC to acquire the information of the plurality of optical modules through the BMC; by the mode, each group of optical modules can be hung under different IIC buses of the BMC, and when the BMC accesses the optical modules, multithreading is used, so that the access time of the whole optical module can be shortened to be less than one fourth, and the access time is reduced.

Description

System, method and medium for fast access of optical module of switch

Technical Field

The invention relates to the field of switch design, in particular to a system, a method and a medium for quickly accessing an optical module of a switch.

Background

The TOR switches are often arranged in a server cabinet to realize interconnection among servers in the cabinet, and the servers are different from personal PCs and have large data transmission capacity, so that the switches and the servers often use AOC cables for high-speed communication. The number of ports of TOR switches typically varies between 30 and 60.

The AOC is composed of an optical module EEPROM and optical fibers, wherein the optical module EEPROM is used for storing basic information such as manufacturer models, transmission rates, transmission distances and the like and also storing relevant information of working states of the optical module EEPROM, such as information of temperature, alarm and the like. During the normal operation of the switch, the CPU polls the optical module EEPROM at regular time through the IIC bus to acquire the hardware information and the working state of the optical module EEPROM, so that the working state of each module in the switch is adjusted, the data volume of the EEPROM is large, and the access time of the EEPROM of a single optical module is more than 1 second. Since the IIC bus is low-speed communication, the IIC addresses of the internal EEPROMs are 0x50 and 0x51 as defined by the optical module EEPROM standard, and the addresses of the IIC devices cannot be repeated in the same IIC bus. Therefore, in the current design, an IIC extension chip is usually used to realize that all optical module EEPROMs are in different channels, and a CPU only accesses one channel at the same time. Because the number of the ports of the TOR switch is large, the IIC communication rate is low, and the IIC communication rate is limited by IIC resources of the CPU, when the optical module EEPROM is accessed, only one optical module EEPROM can be accessed, and the IIC extended chip is combined to operate, so that the polling of all the optical module EEPROMs is time-consuming. Some manufacturers make IIC channel extension through a CPLD chip or directly acquire an optical module EEPROM through an FPGA chip, but both the two ways can increase the complexity of hardware design and improve the BOM cost of the switch.

Disclosure of Invention

The invention mainly solves the problems that in the prior art, the speed of accessing the optical module EEPROM by the CPU is low, the time for accessing all the optical module EEPROMs is very long, and the cost is increased if the design complexity of hardware is increased by the CPLD or the FPGA.

In order to solve the technical problems, the invention adopts a technical scheme that: provided is a switch optical module quick access system, comprising: the system comprises a CPU, a BMC, a switch chip, an expansion chip module and a plurality of optical modules;

the BMC is connected with the expansion chip module through the switch chip;

the CPU is respectively connected with the BMC, the switch chip and the expansion chip module;

the expansion chip module is connected with the plurality of optical modules;

the BMC acquires information of a plurality of optical modules through the expansion chip module;

the CPU controls the switch chip to be opened and closed, and the CPU acquires information of the plurality of optical modules through the BMC or the expansion chip module.

Preferably, when the CPU controls the switch chip to be closed, the CPU obtains information of the plurality of optical modules through the extended chip module;

and when the CPU controls the switch chip to be started, the CPU acquires the information of the plurality of optical modules through the BMC.

Preferably, the expansion chip module comprises a first expansion chip and a plurality of second expansion chips; the first extension chip is connected with the plurality of second extension chips through a first bus respectively, and the plurality of second extension chips are connected with the plurality of optical modules.

Preferably, the CPU is connected to the first expansion chip through a first bus, and an input/output pin of the CPU is connected to an enable end of the switch chip; and the CPU is connected with the BMC through a second bus.

Preferably, the BMC is connected to the switch chip through a plurality of third buses, and the switch chip is connected to the plurality of second expansion chips through a plurality of fourth buses.

Preferably, the first bus, the third bus and the fourth bus are IIC buses; the second bus is an LPC bus, and the first extension chip and the second extension chip are IIC extension chips; the input and output pin is GPIO.

The invention also provides a method for quickly accessing the optical module of the switch, which comprises the following steps:

writing the access optical module into the BMC in a multithread manner, and executing an access strategy according to the state of a CPU control switch chip;

the access policy is:

when the CPU controls the state of the switch chip to be on, the CPU acquires the information of the optical module through the BMC;

and when the CPU fails to acquire the optical module information through the BMC, the CPU controls the state of the switch chip to be closed, and the CPU acquires the optical module information through an extension chip.

Preferably, the step of acquiring the optical module information by the CPU through the BMC further includes:

the CPU closes the connection with the expansion chip module;

the BMC accesses the optical module in a multithread mode through the access optical module and acquires data;

the BMC parses the data into structured data;

and the CPU communicates with the BMC through an IPMI protocol and acquires the structured data.

Preferably, when the CPU fails to acquire the optical module information through the BMC, the step of: the CPU communicates with the BMC through an IPMI protocol, and if the CPU receives an abnormal value, the CPU fails to acquire the optical module information through the BMC.

The present invention also provides a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of a method for fast access to a switch optical module as described above.

The invention has the beneficial effects that:

1. the rapid access system for the optical module of the switch can realize the indirect access of data in the optical module through the CPU, reserve the channel of the optical module accessed by the CPU through the IIC of the CPU, close the switch chip if the CPU needs to access independently, avoid the problem that the dual hosts of the BMC and the CPU exist on the IIC bus at the same time, avoid the IIC bus from being hung dead, and ensure the reliability of the operation of the BMC and the CPU from the hardware level.

2. The method for quickly accessing the optical module of the switch can realize that the task of polling the EEPROM of the optical module is handed to the BMC, the IIC resource of the BMC is fully utilized to acquire the data in the optical module, the efficiency is improved, whether the data in the optical module is acquired successfully or not is judged through the abnormal value, the state can be displayed more conveniently, whether the data in the optical module is acquired successfully or not can be checked in real time, and if the data in the optical module is acquired unsuccessfully, the BMC breaks down, so that the fault reason is conveniently detected.

3. The computer-readable storage medium can create multiple threads to acquire the EEPROM data of the optical module, and can greatly reduce the access time of the optical module.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram of a fast access system architecture of an optical module of a switch according to embodiment 1 of the present invention;

fig. 2 is a flow of a fast access method for an optical module of a switch according to embodiment 2 of the present invention;

fig. 3 is a schematic diagram of a computer-readable storage medium architecture according to embodiment 3 of the present invention.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "first", "second", "third", and "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

It is noted that in the description of the present invention

The TOR (Top of Rack) switch refers to that 1 to 2 switches are deployed on each server cabinet, and a server directly accesses to the switch of the local cabinet to realize interconnection between the server and the switch in the cabinet, although literally, Top of Rack refers to "Top of cabinet", the core of an actual TOR lies in that the switch is deployed in the server cabinet, and can be deployed at the Top of the cabinet, or at the Middle (Middle of Rack) or Bottom (Bottom of Rack) of the cabinet, generally speaking, it is most beneficial to route the switch at the Top of the cabinet, so this architecture is most applied.

BOM (Bill of Material) is a bill of materials.

The IIC bus is a simple, bi-directional two-wire synchronous serial bus developed by Philips corporation. It requires only two wires to transfer information between devices connected to the bus.

The CPLD is a programmable logic device with high density, high speed and low power consumption.

An eeprom (electrically Erasable Programmable read only memory) refers to a charged Erasable Programmable read only memory, and is a memory chip with no data loss after power failure.

FPGA (field Programmable Gate array) is a field Programmable Gate array.

AOC (active Optical cables) is an active Optical cable.

Bmc (baseboard Manager controller) is a baseboard management controller.

It should be noted that the BMC is an independent system, and is not dependent on other hardware (such as CPU, memory, etc.) on the system, nor on the BIOS, OS, etc. (however, the BMC may interact with the BIOS and the OS, which may play a better role in platform management, and system management software under the OS may cooperate with the BMC to achieve a better management effect).

GPIO (general Purpose Input output) general Purpose Input/output port.

The SPI (serial Peripheral interface) interface is a serial Peripheral interface, which is a synchronous Peripheral interface and can make the single-chip microcomputer communicate with various Peripheral equipment in a serial mode to exchange information.

The UART (Universal Asynchronous Receiver/Transmitter) interface is a Universal Asynchronous Receiver/Transmitter, which is an Asynchronous Receiver/Transmitter.

An ipmi (intelligent Platform Management interface) is an industrial standard adopted by peripheral devices of an enterprise system with an Intel architecture.

The LPC Bus Low pin count Bus is the Bus used in IBM PC compatible machines to connect Low bandwidth devices to the CPU.

Structured data, simply referred to as a database. The method is easier to understand when being combined into typical scenes, such as enterprise ERP, financial systems; a medical HIS database; an education all-purpose card; government administration approval; other core databases and the like basically comprise high-speed storage application requirements, data backup requirements, data sharing requirements and data disaster tolerance requirements.

The pop () function may execute a shell command in a program and return the result of the command execution. There are two modes of operation, read and write respectively. In the read mode, the program can read the output of the command, one of which is to obtain the parameters of the network interface. In write mode, it is most often used to create a new file or open other services, etc.

And the Pread () function is used for reading data from the file atomically with offset.

pthread is provided in a pthread library, and creating multiple threads can be performed through pthread functions.

Example 1

An embodiment of the present invention provides a system for quickly accessing an optical module of a switch, please refer to fig. 1, including: the system comprises a CPU, a BMC, an IIC expansion chip module and a plurality of optical module EEPROMs;

an IIC interface is arranged in the CPU and is connected with the IIC expansion chip module through the IIC interface; the IIC expansion chip is connected with the plurality of optical module EEPROMs; the BMC is connected with the IIC expansion chip; the CPU is connected with the BMC through an LPC bus,

the TOR switch is used as network equipment on a sink node, has very strict requirements on the reliability of the TOR switch, is very complex in hardware design, the core control device comprises a CPU, a switching chip and a BMC, the CPU is used for operating a network operating system, the switching chip is configured according to the setting of operation and maintenance personnel, and also can operate a plurality of two-layer and three-layer protocols, so that certain requirements on the performance of a CPU processor are met, in the TOR switch, a high-performance CPU processor is usually used, the CPU has high operation frequency and multiple cores, and has abundant high-speed communication interfaces, but the low-speed communication interfaces are as follows: IIC, SPI and UART interface resources are limited.

The CPU focuses on running a network operating system and configuring a switching chip; the BMC manages the operating state of each hardware in the TOR switch as a coprocessor, such as: the temperature in the exchanger, the working voltage and the working current of the power supply module and the rotating speed lamp of the fan are correspondingly regulated and controlled; and the BMC chip such as AST2520 has abundant IIC resources, and the number of IIC interfaces is up to 14. In the work division of the switch, the BMC and the CPU are decoupled, namely the running services cannot be crossed by the chips managed by the BMC and the CPU.

The IIC extended chip module comprises a first IIC extended chip to an eighth IIC extended chip;

the CPU is connected with the first IIC expansion chip through an IIC interface connection IIC bus, and the first IIC expansion chip is respectively connected with the second IIC expansion chip to the eighth IIC expansion chip; the second IIC extended chip to the eighth IIC extended chip are respectively connected with 8 optical module EEPROMs;

the CPU accesses the physical link of the optical module EEPROM, on one hand, the reliability of the system can be improved, and when the CPU fails to acquire the optical module EEPROM through the BMC, the IIC bus of the CPU is used; on the other hand, if the product requirement is acquired by the IIC bus of the CPU, the design is compatible;

the IIC interfaces and IIC buses of a conventional BMC chip have 14, the number of optical ports of a TOR switch is usually about 50,

the IIC addresses of the EEPROM of the optical modules are the same, the EEPROM of each optical module has two addresses 0x50 and 0x51, 50 optical modules are arranged under the condition that the port of the switch is full, the IIC addresses among the 50 optical modules are the same, and the internal addresses of the 50 optical modules are 0x50 and 0x 51;

the BMC cannot meet the condition that an IIC bus is butted with an optical module EEPROM, so an IIC extension chip is adopted to meet the requirement of use, 8 channels can be expanded by one IIC extension chip, and the access efficiency is improved;

the BMC is provided with a first IIC interface to an eighth IIC interface, and the first IIC interface to the eighth IIC interface in the BMC are respectively connected with a second IIC expansion chip to an eighth IIC expansion chip through a 16-channel switch chip;

an IIC interface of the BMC is connected with only one IIC expansion chip through an IIC bus, namely, one IIC interface accesses 8 optical module EEPROMs through one IIC bus; reserving other residual IIC interfaces of the BMC for managing other IIC devices in the system; meanwhile, the design of accessing the optical module EEPROM through the IIC bus of the CPU is compatible, so that when the BMC or the CPU accesses the optical module EEPROM, the normal work of the other party is not interfered;

the 16 switch chips are provided with control enabling ends, GPIO pins in the CPU are connected with the control enabling ends, and the 16 switch chips can be controlled to be opened and closed, so that reading of the light module EEPROM by the BMC is controlled.

Example 2

An embodiment of the present invention further provides a method for quickly accessing an optical module of a switch, please refer to fig. 2, which includes the following steps:

s100, environment deployment is carried out, a system environment for quickly accessing an EEPROM of an optical module of a switch is built, an embedded Linux system is operated in a BMC chip, a BMC develops a plurality of threads aiming at an IIC interface connected with each EEPROM of the optical module, and the optical module EEPROM is accessed by using the plurality of threads, wherein the operation modes of the plurality of threads are executed in parallel, so that the access efficiency is improved; data in an optical module EEPROM is thrown out at a driving layer, read and written according to character equipment, the EEPROM data is read through a pop function or a pread function at a BMC, and a plurality of threads are created by programming a plurality of threads through a pthread function;

executing an access strategy according to the state of the CPU control switch chip;

the access policy is: when the CPU controls the switch chip to be on, the CPU obtains the information of the optical module through the BMC; and when the CPU controls the switch chip to be in a closed state, the CPU acquires the information of the optical module through the expansion chip.

S200, when the CPU does not directly access the optical module EEPROM, the CPU acquires optical module information through a BMC (baseboard management controller), the CPU controls a first IIC (inter-integrated circuit) expansion chip, all interfaces of the first IIC expansion chip are closed, collision between the BMC and the CPU on an IIC bus is avoided, the BMC accesses a plurality of optical module EEPROMs in parallel through a plurality of IIC interfaces by using a plurality of threads, the BMC acquires data in the optical module EEPROMs and then analyzes the data into structured data, the CPU communicates with the BMC through an IPMI (intelligent power management interface) protocol to acquire the structured data, and the CPU directly uses the data;

s300, when the CPU obtains the communication with the BMC through the IPMI protocol and fails to obtain the structured data, returning to an abnormal value of the CPU, and when the structured data is successfully obtained, not returning to the abnormal value of the CPU;

if the CPU receives the abnormal value, the acquisition of the structured data fails, the CPU acquires the information of the optical module through the expansion chip, a GPIO pin connected with a 16-channel switch chip in the CPU is enabled, the 16-channel switch chip is controlled to be closed, the connection between an IIC interface of the BMC and the plurality of optical modules is disconnected, and therefore the BMC stops accessing the EEPROM of the plurality of optical modules; and the CPU accesses the plurality of optical module EEPROMs through the first IIC extended chip.

Example 3

Based on the same inventive concept as the method in the foregoing embodiment, an embodiment of the present specification further provides a computer-readable storage medium 401, please refer to fig. 3, where a computer program 402 is stored on the computer-readable storage medium 401, and when the computer program 402 is executed by a processor, the steps of the method for fast accessing an optical module of a switch as disclosed in the foregoing are implemented.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, and a program that can be implemented by the hardware and can be instructed by the program to be executed by the relevant hardware may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic or optical disk, and the like.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A switch optical module quick access system, comprising: the system comprises a CPU, a BMC, a switch chip, an expansion chip module and a plurality of optical modules;

the BMC is connected with the expansion chip module through the switch chip;

the expansion chip module is connected with the plurality of optical modules;

2. The switch optical module quick access system of claim 1, wherein:

when the CPU controls the switch chip to be closed, the CPU obtains the information of the plurality of optical modules through the expansion chip module;

3. The switch optical module quick access system of claim 1, wherein: the expansion chip module comprises a first expansion chip and a plurality of second expansion chips; the first extension chip is connected with the plurality of second extension chips through a first bus respectively, and the plurality of second extension chips are connected with the plurality of optical modules.

4. The switch optical module quick access system of claim 3, wherein: the CPU is connected with the first expansion chip through a first bus, and an input/output pin in the CPU is connected with an enabling end of the switch chip; and the CPU is connected with the BMC through a second bus.

5. The switch optical module quick access system of claim 4, wherein: the BMC is connected with the switch chip through a plurality of third buses, and the switch chip is connected with a plurality of second expansion chips through a plurality of fourth buses.

6. The switch optical module quick access system of claim 5, wherein: the first bus, the third bus and the fourth bus are IIC buses; the second bus is an LPC bus, and the first extension chip and the second extension chip are IIC extension chips; the input and output pin is GPIO.

7. A method for quickly accessing an optical module of a switch is characterized by comprising the following steps:

the access policy is:

8. The switch optical module quick access method according to claim 7, wherein: the step of acquiring the optical module information by the CPU through the BMC further includes:

the CPU closes the connection with the expansion chip module;

the BMC parses the data into structured data;

9. The method for fast access of the optical module of the switch according to claim 8, wherein: when the CPU fails to acquire the optical module information through the BMC, the step of: the CPU communicates with the BMC through an IPMI protocol, and if the CPU receives an abnormal value, the CPU fails to acquire the optical module information through the BMC.

10. A computer-readable storage medium, having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of a switch optical module quick access method according to any of claims 7-9.