CN112732223A - Data processing method and system for half-precision floating-point number divider - Google Patents
Data processing method and system for half-precision floating-point number divider Download PDFInfo
- Publication number
- CN112732223A CN112732223A CN202011641150.2A CN202011641150A CN112732223A CN 112732223 A CN112732223 A CN 112732223A CN 202011641150 A CN202011641150 A CN 202011641150A CN 112732223 A CN112732223 A CN 112732223A
- Authority
- CN
- China
- Prior art keywords
- data
- bit
- module
- separation
- bit separation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 18
- 238000000926 separation method Methods 0.000 claims abstract description 216
- 238000004364 calculation method Methods 0.000 claims description 43
- 230000010354 integration Effects 0.000 claims description 43
- 238000006073 displacement reaction Methods 0.000 claims description 9
- 238000002156 mixing Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 7
- 230000003750 conditioning effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 5
- 238000013527 convolutional neural network Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013528 artificial neural network Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/535—Dividing only
Abstract
The invention provides a data processing method of a half-precision floating-point number divider, which comprises the steps of respectively carrying out bit separation processing on first data and second data to respectively obtain first bit separation data and second bit separation data, carrying out data adjustment on the second bit separation data to obtain adjustment data, carrying out iterative computation processing on the adjustment data to obtain iteration data, carrying out mixed operation on the first bit separation data and the iteration data to obtain mixed bit separation data, and carrying out data reset adjustment on the mixed bit separation data to obtain computation result data. The data processing method of the half-precision floating-point number divider reduces the operation period and improves the operation efficiency through iterative computation processing. The invention also provides a data processing system of the half-precision floating-point number divider, which realizes the data processing method of the half-precision floating-point number divider.
Description
Technical Field
The invention relates to the field of half-precision floating-point number dividers, in particular to a data processing method and system of a half-precision floating-point number divider.
Background
In the design of Convolutional Neural Networks (CNN), the number of layers of a network model is gradually increasing as the number of pixels of an image to be processed and the number of discrimination types increase.
From the perspective of easy design, most of convolutional neural network designs process data in a fixed point number mode, the mathematical operation speed is high, the algorithm circuit design is mature, the fixed point division circuit is also successfully applied to the CNN neural network design, but the out-of-range error is continuously increased along with the increase of the number of layers, the final classification judgment of images is easy, and the practical floating point number mode has a large representation range and a small possibility of generating the out-of-range error, so that the floating point number mode is calculated in the industry.
At present, floating point number calculation circuits are mature, but the divider has the problems of too many operation periods and too long operation time, for example, in the divider of the Xilinx FPGA, division by FP16 requires 17 clock periods, which is long in period and low in operation efficiency.
Therefore, there is a need to provide a novel data processing method and system for a half-precision floating-point divider to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a data processing method and a data processing system for a half-precision floating-point number divider, which reduce the operation period and improve the operation efficiency.
In order to achieve the above object, the data processing method of the half-precision floating-point number divider of the present invention includes the following steps:
s1: respectively carrying out bit separation processing on the first data and the second data to respectively obtain first bit separation data and second bit separation data:
s2: performing data adjustment on the second bit of separated data to obtain adjusted data;
s3: performing iterative computation processing on the adjustment data to obtain iteration data;
s4: performing mixed operation on the first bit of separation data and the iteration data to obtain mixed bit of separation data;
s5: and carrying out data resetting adjustment on the mixed bit separation data to obtain calculation result data.
The data processing method of the half-precision floating point number divider has the beneficial effects that: and performing iterative computation processing on the adjustment data to obtain iterative data, performing mixed operation on the first bit separation data and the iterative data to obtain mixed bit separation data, and performing data reset adjustment on the mixed bit separation data to obtain calculation result data.
Preferably, the second bit separation data includes first bit separation sub data, second bit separation sub data, and third bit separation sub data, and the adjustment data includes the first bit separation sub data, the second bit separation shift data, and the third bit separation operation data, and the data adjustment includes the following steps:
s21: restoring the third bit of separation sub-data to obtain restored data;
s22: shifting the restored data to obtain second bit separation shifted data, wherein the second bit separation shifted data is located in a threshold interval;
s23: and performing addition processing or subtraction processing on the second bit separation sub data and the bit number subjected to the shift processing according to the type of the shift processing to obtain third bit separation operation data.
Further preferably, the threshold interval includes a first end value and a second end value, an absolute value of a difference between the first end value and the restored data is smaller than an absolute value of a difference between the second end value and the restored data, and the second displacement data is displacement data closest to the first end value.
Further preferably, the iterative data includes the first bit-separated sub-data, the second bit-separated shift data, and iterative operation result data, and the iterative computation process includes the steps of:
s31: performing iterative operation on the third bit separation operation data according to the first iterative threshold, the second iterative threshold, the third iterative threshold and the fourth iterative threshold to obtain operation result data;
s32: judging whether the difference value between the first iteration threshold and the operation result data is greater than 1;
s33: if the difference is greater than 1, the operation result data is used as a new first iteration threshold, the step S31 and the step S32 are re-executed until the difference is less than or equal to 1, and then the operation result data obtained by executing the step S31 for the last time is output as the iteration operation result data. The beneficial effects are that: the iteration times are convenient to control, and further the operation period is reduced.
Further preferably, the first bit of separated data includes a fourth bit of separated sub data, a fifth bit of separated sub data, and a sixth bit of separated sub data, the mixed bit of separated data includes a first bit of separated and integrated data, a second bit of separated and integrated data, and a third bit of separated and integrated data, and the mixing operation includes the following steps:
performing an exponentiation operation on the fourth bit-separated subdata and the first bit-separated subdata to obtain the first bit-separated integrated data;
adding and subtracting the fifth bit separation sub data, the second bit separation displacement data and an addition and subtraction threshold value to obtain second bit separation and integration data;
and performing multiplication and division operation on the sixth bit of separation subdata, the iterative operation result data and a multiplication and division threshold value to obtain the third bit of separation and integration data. The beneficial effects are that: and mixed bit separation data can be obtained through calculation conveniently.
Further preferably, the calculation result data includes first bit of separated integrated data, second bit of data and third bit of data, and the data reset adjustment includes the steps of:
s51: judging whether the third bit separation and integration data is smaller than a first reset adjustment threshold value or not;
s52: if the third bit of separation and integration data is smaller than the first reset adjustment threshold, moving the third bit of separation and integration data to the left by a minimum number of bits to enable the third bit of separation and integration data to be larger than or equal to the first reset adjustment threshold;
s53: and subtracting the minimum number of the left-moving bits of the third bit of the separated and integrated data and the third bit of the separated and integrated data to obtain the third bit of data. The beneficial effects are that: and the semi-precision floating point number is convenient to obtain.
Further preferably, the data reset adjustment further comprises the following steps:
s51 a: judging whether the third bit separation and integration data is larger than a second reset adjustment threshold value or not;
s52 a: if the third bit separation and integration data is larger than the second reset adjustment threshold, moving the third bit separation and integration data to the right by the least number of bits, so that the third bit separation and integration data is smaller than or equal to the first reset adjustment threshold;
s53 a: and adding the third bit of separated and integrated data and the least bit of shifted third bit of separated and integrated data to obtain the third bit of data. The beneficial effects are that: and the semi-precision floating point number is convenient to obtain.
The invention also provides a data processing system of the half-precision floating point number divider, which comprises a first bit separation module, a second bit separation module, an adjustment module, an iteration module, a mixed operation module and a reset adjustment module, wherein the first bit separation module is connected with the mixed operation module, the second bit separation module is connected with the adjustment module and the mixed operation module, the adjustment module is connected with the mixed operation module, the mixed operation module is connected with the reset adjustment module, the first bit separation module is used for performing bit separation processing on first data to obtain first bit separation data, the second bit separation module is used for performing bit separation processing on second data to obtain second bit separation data, the adjustment module is used for performing data adjustment on the second bit separation data to obtain adjustment data, the iterative module is used for performing iterative computation processing on the adjustment data to obtain iterative data, the mixed operation module is used for performing mixed operation on the first bit separation data and the iterative data to obtain mixed bit separation data, and the reset adjustment module is used for performing data reset adjustment on the mixed bit separation data to obtain computation result data.
The half-precision floating point number divider data processing system has the advantages that: the iterative module is used for performing iterative computation processing on the adjustment data to obtain iterative data, the mixed operation module is used for performing mixed operation on the first bit separation data and the iterative data to obtain mixed bit separation data, the reset adjustment module is used for performing data reset adjustment on the mixed bit separation data to obtain computation result data, and through the iterative computation processing, the computation period is reduced, and the computation efficiency is improved.
Preferably, the adjusting module includes a data restoring unit, a data shifting unit and a first data operation unit, an input end of the data restoring unit is connected to the second output end of the second bit separation module, an output end of the data restoring unit is connected to the data shifting unit, a first output end of the data shifting unit is connected to the first input end of the first data operation unit, and a second input end of the first data operation unit is connected to the third output end of the second bit separation module.
Further preferably, the iterative module includes an iterative operation unit, a judgment unit and an assignment unit, a first input end of the iterative operation unit is connected with an output end of the first data operation unit, an output end of the iterative operation unit is connected with an input end of the judgment unit, a first output end of the judgment unit is connected with an input end of the assignment unit, and an output end of the assignment unit is connected with a second input end of the iterative operation unit.
Further preferably, the hybrid operation module includes a second data operation unit, a third data operation unit and a fourth data operation unit, a first input end of the second data operation unit is connected to a first output end of the first bit separation module, a second input end of the second data operation unit is connected to a first output end of the second bit separation module, a first input end of the third data operation unit is connected to a second output end of the first bit separation module, a second input end of the third data operation unit is connected to a second output end of the data shift unit, a first input end of the fourth data operation unit is connected to a third output end of the first bit separation module, and a second input end of the fourth data operation unit is connected to a second output end of the judgment unit.
Preferably, the half-precision floating-point number divider data processing system further includes a first cache module, one end of the first cache module is connected to the first bit separation module, and the other end of the first cache module is connected to the hybrid operation module.
Further preferably, the half-precision floating-point number divider data processing system further includes a second cache module, one end of the second cache module is connected to the second bit separation module, and the other end of the second cache module is connected to the hybrid operation module.
Further preferably, the first buffer module includes at least 1 first buffer unit, when the number of the first buffer units is greater than 1, the first buffer units are connected in series, the second buffer module includes at least 1 second buffer unit, and when the number of the second buffer units is greater than 1, the second buffer units are connected in series.
Further preferably, the number of the first buffer units is the same as the number of the second buffer units.
Further preferably, the iteration module includes at least 2 iteration calculation units and at least 1 assignment calculation unit, the number of the assignment calculation units is less than that of the iteration calculation units by 1, and the iteration calculation units are connected through one assignment calculation unit.
Drawings
FIG. 1 is a flow chart of a data processing method of a half-precision floating-point divider according to the present invention;
FIG. 2 is a flow chart of data adjustment according to the present invention;
FIG. 3 is a flow chart of an iterative computation process of the present invention;
FIG. 4 is a flow chart of data reset adjustment in some embodiments of the present invention;
FIG. 5 is a flow chart of data reset adjustment in further embodiments of the present invention;
FIG. 6 is a block diagram of a half-precision floating-point divider data processing system according to the present invention;
FIG. 7 is a block diagram of an adjustment module according to the present invention;
FIG. 8 is a block diagram of an iteration module of the present invention;
FIG. 9 is a block diagram of a half precision floating point divider data processing system in accordance with still further embodiments of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides a data processing method for a half-precision floating-point number divider, and referring to fig. 1, the data processing method for the half-precision floating-point number divider includes the following steps:
s1: respectively carrying out bit separation processing on the first data and the second data to respectively obtain first bit separation data and second bit separation data:
s2: performing data adjustment on the second bit of separated data to obtain adjusted data;
s3: performing iterative computation processing on the adjustment data to obtain iteration data;
s4: performing mixed operation on the first bit of separation data and the iteration data to obtain mixed bit of separation data;
s5: and carrying out data resetting adjustment on the mixed bit separation data to obtain calculation result data.
The first data is used as dividend, and the second data is used as divisor.
In some embodiments, the second bit separation data includes first bit separation sub data, second bit separation sub data, and third bit separation sub data, and the adjustment data includes the first bit separation sub data, the second bit separation shift data, and the third bit separation operation data, in step S2, the first bit separation sub data is not processed, and the second bit separation sub data and the third bit separation sub data are respectively processed to obtain the second bit separation shift data and the third bit separation operation data. Specifically, referring to fig. 2, the data adjustment includes the following steps:
s21: restoring the third bit of separation sub-data to obtain restored data;
s22: shifting the restored data to obtain second bit separation shifted data, wherein the second bit separation shifted data is located in a threshold interval;
s23: and performing addition processing or subtraction processing on the second bit separation sub data and the bit number subjected to the shift processing according to the type of the shift processing to obtain third bit separation operation data. Specifically, if the shift processing is left shift, the subtraction processing is performed in step S23, and if the shift processing is right shift, the addition processing is performed in step S23.
In some embodiments, the second bit-split sub-data is a half-precision floating point number, the first bit-split sub-data is a sign bit of the half-precision floating point number, the second bit-split sub-data is a rank bit of the half-precision floating point number, and the third bit-split sub-data is a mantissa of the half-precision floating point number.
In some embodiments, the threshold interval includes a first end value and a second end value, an absolute value of a difference between the first end value and the restored data is less than an absolute value of a difference between the second end value and the restored data, and the second bit-separated shifted data is shifted data closest to the first end value. Specifically, if the first end value is 512, the second end value is 1024; the first end value is 1024, and the second end value is 512.
Specifically, for example, the restored data is 129, 200 is shifted left by 1 bit to obtain 258, 258 is shifted left by 1 bit to obtain 516, 516 is located between 512 and 1024, and 516 is shifted data closest to 512 after shifting, that is, the bit number of the shift processing is 2, and the second bit separation data and the bit number of the shift processing are subtracted according to the type of the shift processing to obtain the third bit separation operation data.
Specifically, for example, the restored data is 8176, 8176 is shifted to the right by 1 bit to obtain 4088, 4088 is shifted to the right by 1 bit to obtain 2044, 2044 is shifted to the right by 1 bit to obtain 1022, 1022 is located between 512 and 1024, and 1022 is shifted data closest to 1024 after shifting, that is, the number of bits to be shifted is 3, and the second bit-separated data and the shifted number of bits are added according to the type of the shift processing to obtain the third bit-separated operation data.
In some embodiments, the iterative data includes the first bit-separated sub data, the second bit-separated shift data, and iterative operation result data. Specifically, referring to fig. 3, the iterative computation process includes the steps of:
s31: performing iterative operation on the third bit separation operation data according to the first iterative threshold, the second iterative threshold, the third iterative threshold and the fourth iterative threshold to obtain operation result data;
s32: judging whether the difference value between the first iteration threshold and the operation result data is greater than 1;
s33: if the difference is greater than 1, the operation result data is used as a new first iteration threshold, the step S31 and the step S32 are re-executed until the difference is less than or equal to 1, and then the operation result data obtained by executing the step S31 for the last time is output as the iteration operation result data. Specifically, in step S32, the operation result data is subtracted from the first iteration threshold.
In some embodiments, when the steps S31 and S32 are executed for the first time, the first iteration threshold is 1, the second iteration threshold is 2048, the third iteration threshold is 1024, and the fourth iteration threshold is 1024, where the iterative operation specifically includes:
multiplying the first iteration threshold value by the third bit separation operation data to obtain first third bit separation operation data; dividing the first third bit of separation operation data by the third iteration threshold to obtain second third bit of separation operation data; subtracting the second third bit separation operation data from the second iteration threshold to obtain third bit separation operation data; multiplying the third bit separation operation data by the first iteration threshold to obtain fourth bit separation operation data; and dividing the fourth iteration threshold by the fourth third bit separation operation data to obtain the operation result data.
In some embodiments, the first bit-separated data includes a fourth bit-separated sub-data, a fifth bit-separated sub-data, and a sixth bit-separated sub-data, the mixed bit-separated data includes a first bit-separated integrated data, a second bit-separated integrated data, and a third bit-separated integrated data, and the mixing operation includes performing an exponentiation operation on the fourth bit-separated sub-data and the first bit-separated sub-data to obtain the first bit-separated integrated data; adding and subtracting the fifth bit separation sub data, the second bit separation displacement data and an addition and subtraction threshold value to obtain second bit separation and integration data; and performing multiplication and division operation on the sixth bit of separation subdata, the iterative operation result data and a multiplication and division threshold value to obtain the third bit of separation and integration data. Specifically, the first bit-separated sub data is exponentiated as an exponent of the fourth bit-separated sub data; the addition and subtraction threshold is 15, the fifth bit separation sub data is subtracted by the second bit separation shift data, and then the addition and subtraction threshold 15 is added to obtain the second bit separation integration data; the multiplication and division threshold is 1024, the sixth separated subdata is multiplied by the iterative operation result data, and then the multiplication and division threshold is 1024, so that the third separated and integrated data is obtained.
In some embodiments, the first bit of separated data is a half-precision floating point number, the fourth bit of separated sub-data is a sign bit of the half-precision floating point number, the fifth bit of separated sub-data is a rank bit of the half-precision floating point number, and the sixth bit of separated sub-data is a mantissa of the half-precision floating point number.
In some embodiments, the calculation result data includes first bit separation and integration data, second bit displacement data and third bit data, wherein the first bit separation and integration data is a sign bit of the calculation result data, the second bit displacement data is an order bit of the calculation result data, and the third bit data is a mantissa of the calculation result data. Referring to fig. 4, the data reset adjustment includes the steps of:
s51: judging whether the third bit separation and integration data is smaller than a first reset adjustment threshold value or not;
s52: if the third bit of separation and integration data is smaller than the first reset adjustment threshold, moving the third bit of separation and integration data to the left by a minimum number of bits to enable the third bit of separation and integration data to be larger than or equal to the first reset adjustment threshold;
s53: and subtracting the minimum number of the left-moving bits of the third bit of the separated and integrated data and the third bit of the separated and integrated data to obtain the third bit of data. Specifically, the third split-integration data is subtracted by the least number of bits of the third split-integration data shifted to the left to obtain the third bit data.
Specifically, the first reset adjustment threshold is 1024, for example, the third separated and integrated data is 500, 500 is shifted left by 1 bit to obtain 1000, 1000 is shifted left by 1 bit to obtain 2000, 2000 is greater than 1024, that is, the third separated and integrated data is shifted left by 2 bits and then is greater than the second reset adjustment threshold, that is, the third separated and integrated data is shifted left by the minimum number of bits to be 2.
In some embodiments, referring to fig. 5, the data reset adjustment further comprises the steps of:
s51 a: judging whether the third bit separation and integration data is larger than a second reset adjustment threshold value or not;
s52 a: if the third bit separation and integration data is larger than the second reset adjustment threshold, moving the third bit separation and integration data to the right by the least number of bits, so that the third bit separation and integration data is smaller than or equal to the first reset adjustment threshold;
s53 a: and adding the third bit of separated and integrated data and the least bit of shifted third bit of separated and integrated data to obtain the third bit of data. Specifically, the third bit of the separate and integrated data plus the minimum number of bits of the third bit of the separate and integrated data shifted to the right are added to obtain the third bit of data.
Specifically, the second reset adjustment threshold is 2048, for example, the third separated and integrated data is 10000, 10000 is shifted to the right by 1 bit to obtain 5000, 500 is shifted to the right by 1 bit to obtain 2500, 2500 is shifted to the right by 1 bit to obtain 1250, 1250 is smaller than 2048, that is, the third separated and integrated data is shifted to the right by 3 bits and then is smaller than the second reset adjustment threshold, that is, the minimum number of bits of the third separated and integrated data that has moved to the right is 3.
FIG. 6 is a block diagram of a half-precision floating-point divider data processing system according to some embodiments of the present invention. Referring to fig. 6, the half-precision floating-point number divider data processing system 100 includes a first bit separation module 10, a second bit separation module 20, an adjustment module 30, an iteration module 40, a blending module 50, and a reset adjustment module 60, where the first bit separation module 10 is connected to the blending module 50, the second bit separation module 20 is connected to the adjustment module 30 and the blending module 50, the adjustment module 30 is connected to the blending module 50, and the blending module 50 is connected to the reset adjustment module 60, where the first bit separation module 10 is configured to perform bit separation processing on first data to obtain first bit separated data, the second bit separation module 20 is configured to perform bit separation processing on second data to obtain second bit separated data, and the adjustment module 30 is configured to perform data adjustment on the second bit separated data, the iteration module 40 is configured to perform iterative computation on the adjustment data to obtain iterative data, the mixed operation module 50 is configured to perform mixed operation on the first-bit separation data and the iterative data to obtain mixed-bit separation data, and the reset adjustment module 60 is configured to perform data reset adjustment on the mixed-bit separation data to obtain calculation result data.
In some embodiments, referring to fig. 7, the adjusting module 30 includes a data restoring unit 301, a data shifting unit 302, and a first data operating unit 303, an input end of the data restoring unit 301 is connected to a second output end of the second bit separating module (not shown), an output end of the data restoring unit 301 is connected to the data shifting unit 302, a first output end of the data shifting unit 302 is connected to a first input end of the first data operating unit 303, and a second input end of the first data operating unit 303 is connected to a third output end of the second bit separating module. The data restoring unit 301 restores the third bit of separated sub data to obtain restored data, the data shifting unit 302 receives the restored data, shifts the restored data to obtain the second bit of separated shifted data, the second bit of separated shifted data is located within a threshold interval, the first data arithmetic unit 303 receives the second bit of separated sub data and the shifted bits, and adds or subtracts the second bit of separated sub data and the shifted bits according to the type of the shift processing to obtain the third bit of separated arithmetic data.
In some embodiments, referring to fig. 8, the iterative module 40 includes an iterative operation unit 401, a determination unit 402, and an assignment unit 403, a first input of the iterative operation unit 401 is connected to an output of the first data operation unit (not shown in the figure), an output of the iterative operation unit 401 is connected to an input of the determination unit 402, a first output of the determination unit 402 is connected to an input of the assignment unit 403, and an output of the assignment unit 403 is connected to a second input of the iterative operation unit 401. Wherein, the iterative operation unit 401 receives the third bit separation operation data, performs iterative operation on the third bit separation operation data according to the first iterative threshold, the second iterative threshold, the third iterative threshold and the fourth iterative threshold, to obtain the operation result data, the determining unit 402 receives the operation result data, determines whether the difference between the first iteration threshold and the operation result data is greater than 1, and if the difference is greater than 1, the judging unit 402 transmits the operation result data to the assigning unit 403, the assigning unit 403 assigns the operation result data to the first iteration threshold, and transmits the first iteration threshold after being assigned to the iteration operation unit 401, if the difference is less than or equal to 1, the judgment unit 402 outputs the operation result data as the iterative operation result data.
In some embodiments, the hybrid operation module includes a second data operation unit, a third data operation unit, and a fourth data operation unit, a first input end of the second data operation unit is connected to the first output end of the first bit separation module, a second input end of the second data operation unit is connected to the first output end of the second bit separation module, a first input end of the third data operation unit is connected to the second output end of the first bit separation module, a second input end of the third data operation unit is connected to the second output end of the data shift unit, a first input end of the fourth data operation unit is connected to the third output end of the first bit separation module, and a second input end of the fourth data operation unit is connected to the second output end of the judgment unit. The second data operation unit receives the fourth bit separation sub data and the first bit separation sub data, performs an exponentiation operation on the fourth bit separation sub data and the first bit separation sub data to obtain the first bit separation integration data, the second data operation unit receives the fifth bit separation sub data and the second bit separation shift data, performs an addition and subtraction processing on the fifth bit separation sub data, the second bit separation shift data and an addition and subtraction threshold value to obtain the second bit separation integration data, the fourth data operation unit receives the sixth bit separation sub data and the iterative operation result data, performs a multiplication and division operation on the sixth bit separation sub data, the iterative operation result data and the multiplication and division threshold value to obtain the third bit separation integration data, and the reset adjustment module receives the first bit separation integration data, the second bit separation sub data and the first bit separation sub data, and the second bit separation shift data, and performs a multiplication and division operation on the sixth bit separation, And the second place separation and integration data and the third place separation and integration data perform data resetting adjustment on the first place separation and integration data, the second place separation and integration data and the third place separation and integration data to obtain calculation result data.
FIG. 9 is a block diagram of a half-precision floating-point divider data processing system according to yet further embodiments of the present invention. Referring to fig. 9, the half-precision floating-point number divider data processing system 100 further includes a first cache module 70 and a second cache module 80, one end of the first cache module 70 is connected to the first bit separation module 10, the other end of the first cache module 70 is connected to the hybrid operation module 50, one end of the second cache module 80 is connected to the second bit separation module 20, and the other end of the second cache module 80 is connected to the hybrid operation module 50.
In some embodiments, the first cache module includes at least 1 first cache unit, when the number of the first cache units is greater than 1, the first cache units are connected in series, the second cache module includes at least 1 second cache unit, when the number of the second cache units is greater than 1, the second cache units are connected in series, the iteration module includes at least 2 iteration calculation units and at least 1 assignment calculation unit, the number of the assignment calculation units is less than 1, and the iteration calculation units are connected by one assignment calculation unit. Preferably, the number of the first buffer units, the number of the second buffer units and the number of the iterative processing units are the same. Preferably, the first cache module includes 5 first cache units, the second cache module includes 5 second cache units, and the iteration module includes at least 5 iteration calculation units and at least 4 assignment calculation units.
In some embodiments, taking 2 iterative computation units and 1 assignment computation unit as examples, two iterative computation units are a first iterative computation unit and a second iterative computation unit respectively, a first input terminal of the first iterative computation unit is connected to an output terminal of the first data operation unit, the second input end of the first iterative computation unit is used for inputting a first iterative threshold value, the first output end of the first iterative computation unit is connected with the first input end of the assignment computation unit, a second output of the first iterative computation unit is connected to a second input of the assignment computation unit, a first output of the assignment calculation unit is connected to a first input of the second iterative calculation unit, and the second output end of the assignment calculation unit is connected with the second input end of the second iterative calculation unit, and the first output end of the second iterative calculation unit is connected with the hybrid calculation module. Wherein the first iteration unit and the second iteration unit are used for performing iterative operation, a first output end of the first iteration unit and a first output end of the second iteration calculation unit output operation result data, the second output end of the first iteration unit is used for outputting third bit separation operation data, the assignment calculation unit is used for assigning values, so that the second iterative computation unit performs iterative computation using the computation result data output by the first iterative computation unit as a first iterative threshold, the first output end of the assignment calculation unit is used for outputting operation result data as a first iteration threshold value, the second end of the assignment computation unit is configured to separate the third bit received by the first iterative computation unit from the operation data, the second iterative computation unit is used for outputting operation result data as iterative operation result data.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (16)
1. A data processing method of a half-precision floating point number divider is characterized by comprising the following steps:
s1: respectively carrying out bit separation processing on the first data and the second data to respectively obtain first bit separation data and second bit separation data:
s2: performing data adjustment on the second bit of separated data to obtain adjusted data;
s3: performing iterative computation processing on the adjustment data to obtain iteration data;
s4: performing mixed operation on the first bit of separation data and the iteration data to obtain mixed bit of separation data;
s5: and carrying out data resetting adjustment on the mixed bit separation data to obtain calculation result data.
2. The method of half precision floating point number divider data processing according to claim 1, wherein said second bit separation data comprises first bit separation sub-data, second bit separation sub-data, and third bit separation sub-data, and wherein said data conditioning comprises said first bit separation sub-data, second bit separation shift data, and third bit separation operation data, said data conditioning comprising the steps of:
s21: restoring the third bit of separation sub-data to obtain restored data;
s22: shifting the restored data to obtain second bit separation shifted data, wherein the second bit separation shifted data is located in a threshold interval;
s23: and performing addition processing or subtraction processing on the second bit separation sub data and the bit number subjected to the shift processing according to the type of the shift processing to obtain third bit separation operation data.
3. The method of half precision floating point number divider data processing according to claim 2, wherein said threshold interval includes a first end value and a second end value, an absolute value of a difference between said first end value and said reduced data is less than an absolute value of a difference between said second end value and said reduced data, and said second displacement data is the displacement data closest to said first end value.
4. The method of half precision floating point number divider data processing according to claim 3, wherein said iterative data includes said first bit separated sub-data, said second bit separated shift data and iterative operation result data, said iterative computation processing including the steps of:
s31: performing iterative operation on the third bit separation operation data according to the first iterative threshold, the second iterative threshold, the third iterative threshold and the fourth iterative threshold to obtain operation result data;
s32: judging whether the difference value between the first iteration threshold and the operation result data is greater than 1;
s33: if the difference is greater than 1, the operation result data is used as a new first iteration threshold, the step S31 and the step S32 are re-executed until the difference is less than or equal to 1, and then the operation result data obtained by executing the step S31 for the last time is output as the iteration operation result data.
5. The half-precision floating point number divider data processing method of claim 4, wherein said first bit separated data includes a fourth bit separated sub-data, a fifth bit separated sub-data, and a sixth bit separated sub-data, and said mixed bit separated data includes a first bit separated integrated data, a second bit separated integrated data, and a third bit separated integrated data, said mixing operation including the steps of:
performing an exponentiation operation on the fourth bit-separated subdata and the first bit-separated subdata to obtain the first bit-separated integrated data;
adding and subtracting the fifth bit separation sub data, the second bit separation displacement data and an addition and subtraction threshold value to obtain second bit separation and integration data;
and performing multiplication and division operation on the sixth bit of separation subdata, the iterative operation result data and a multiplication and division threshold value to obtain the third bit of separation and integration data.
6. The half-precision floating point number divider data processing method of claim 5, wherein said calculation result data includes first bit separated integration data, second bit shifted data, and third bit data, and wherein said data reset adjustment comprises the steps of:
s51: judging whether the third bit separation and integration data is smaller than a first reset adjustment threshold value or not;
s52: if the third bit of separation and integration data is smaller than the first reset adjustment threshold, moving the third bit of separation and integration data to the left by a minimum number of bits to enable the third bit of separation and integration data to be larger than or equal to the first reset adjustment threshold;
s53: and subtracting the minimum number of the left-moving bits of the third bit of the separated and integrated data and the third bit of the separated and integrated data to obtain the third bit of data.
7. The half-precision floating point number divider data processing method of claim 6, wherein said data reset adjustment further comprises the steps of:
s51 a: judging whether the third bit separation and integration data is larger than a second reset adjustment threshold value or not;
s52 a: if the third bit separation and integration data is larger than the second reset adjustment threshold, moving the third bit separation and integration data to the right by the least number of bits, so that the third bit separation and integration data is smaller than or equal to the first reset adjustment threshold;
s53 a: and adding the third bit of separated and integrated data and the least bit of shifted third bit of separated and integrated data to obtain the third bit of data.
8. A data processing system of a half-precision floating-point divider is used for realizing the data processing method of the half-precision floating-point divider according to any one of claims 1 to 7, and is characterized by comprising a first bit separation module, a second bit separation module, an adjustment module, an iteration module, a mixed operation module and a reset adjustment module, wherein the first bit separation module is connected with the mixed operation module, the second bit separation module is connected with the adjustment module and the mixed operation module, the adjustment module is connected with the mixed operation module, and the mixed operation module is connected with the reset adjustment module, wherein the first bit separation module is used for performing bit separation processing on first data to obtain first bit separated data, the second bit separation module is used for performing bit separation processing on second data to obtain second bit separated data, the adjusting module is used for performing data adjustment on the second bit separation data to obtain adjustment data, the iteration module is used for performing iterative computation processing on the adjustment data to obtain iteration data, the mixed operation module is used for performing mixed operation on the first bit separation data and the iteration data to obtain mixed bit separation data, and the reset adjusting module is used for performing data reset adjustment on the mixed bit separation data to obtain calculation result data.
9. The half-precision floating-point number divider data processing system of claim 8, wherein said scaling module comprises a data reduction unit, a data shifting unit, and a first data arithmetic unit, an input of said data reduction unit being coupled to said second output of said second bit separation module, an output of said data reduction unit being coupled to said data shifting unit, a first output of said data shifting unit being coupled to said first input of said first data arithmetic unit, a second input of said first data arithmetic unit being coupled to said third output of said second bit separation module.
10. The half-precision floating-point number divider data processing system according to claim 9, wherein said iteration module comprises an iteration operation unit, a determination unit, and an assignment unit, a first input of said iteration operation unit being connected to an output of said first data operation unit, an output of said iteration operation unit being connected to an input of said determination unit, a first output of said determination unit being connected to an input of said assignment unit, and an output of said assignment unit being connected to a second input of said iteration operation unit.
11. The half-precision floating point number divider data processing system of claim 10, the mixed operation module comprises a second data operation unit, a third data operation unit and a fourth data operation unit, a first input end of the second data operation unit is connected with a first output end of the first bit separation module, the second input end of the second data operation unit is connected with the first output end of the second bit separation module, the first input end of the third data operation unit is connected with the second output end of the first bit separation module, a second input terminal of the third data arithmetic unit is connected with a second output terminal of the data shift unit, a first input end of the fourth data operation unit is connected with a third output end of the first bit separation module, and a second input end of the fourth data operation unit is connected with a second output end of the judgment unit.
12. The half-precision floating-point number divider data processing system of claim 8, further comprising a first cache module, one end of said first cache module being coupled to said first bit separation module, the other end of said first cache module being coupled to said hybrid arithmetic module.
13. The half-precision floating-point number divider data processing system of claim 12, further comprising a second cache module, one end of said second cache module being coupled to said second bit separation module, the other end of said second cache module being coupled to said blending operation module.
14. The half precision floating point number divider data processing system of claim 13, wherein said first cache module includes at least 1 first cache units, said first cache units being connected in series when the number of said first cache units is greater than 1, and said second cache module includes at least 1 second cache units, said second cache units being connected in series when the number of said second cache units is greater than 1.
15. The half-precision floating point number divider data processing system of claim 14, wherein the number of first cache units is the same as the number of second cache units.
16. The half-precision floating-point number divider data processing system according to claim 9, wherein said iteration module includes at least 2 iteration calculation units and at least 1 assignment calculation unit, and the number of said assignment calculation units is less than the number of said iteration calculation units by 1, said iteration calculation units being connected by one of said assignment calculation units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011641150.2A CN112732223A (en) | 2020-12-31 | 2020-12-31 | Data processing method and system for half-precision floating-point number divider |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011641150.2A CN112732223A (en) | 2020-12-31 | 2020-12-31 | Data processing method and system for half-precision floating-point number divider |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112732223A true CN112732223A (en) | 2021-04-30 |
Family
ID=75609104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011641150.2A Pending CN112732223A (en) | 2020-12-31 | 2020-12-31 | Data processing method and system for half-precision floating-point number divider |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112732223A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5341321A (en) * | 1993-05-05 | 1994-08-23 | Hewlett-Packard Company | Floating point arithmetic unit using modified Newton-Raphson technique for division and square root |
| US20110131262A1 (en) * | 2009-12-02 | 2011-06-02 | Satoshi Nakazato | Floating point divider and information processing apparatus using the same |
| CN103092561A (en) * | 2013-01-18 | 2013-05-08 | 北京理工大学 | Goldschmidt division implementation method based on divisor mapping |
| US20160026437A1 (en) * | 2014-07-24 | 2016-01-28 | Arm Limited | Apparatus and method for performing floating-point square root operation |
| CN105389157A (en) * | 2015-10-29 | 2016-03-09 | 中国人民解放军国防科学技术大学 | Goldschmidt algorithm-based floating-point divider |
| US20160110163A1 (en) * | 2014-10-17 | 2016-04-21 | Imagination Technologies, Limited | Small multiplier after initial approximation for operations with increasing precision |
| CN107992284A (en) * | 2017-11-27 | 2018-05-04 | 中国航空无线电电子研究所 | A kind of division function implementation method of programming device |
| US20200065066A1 (en) * | 2018-08-22 | 2020-02-27 | Imagination Technologies Limited | Float Division by Constant Integer |
-
2020
- 2020-12-31 CN CN202011641150.2A patent/CN112732223A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5341321A (en) * | 1993-05-05 | 1994-08-23 | Hewlett-Packard Company | Floating point arithmetic unit using modified Newton-Raphson technique for division and square root |
| US20110131262A1 (en) * | 2009-12-02 | 2011-06-02 | Satoshi Nakazato | Floating point divider and information processing apparatus using the same |
| CN103092561A (en) * | 2013-01-18 | 2013-05-08 | 北京理工大学 | Goldschmidt division implementation method based on divisor mapping |
| US20160026437A1 (en) * | 2014-07-24 | 2016-01-28 | Arm Limited | Apparatus and method for performing floating-point square root operation |
| US20160110163A1 (en) * | 2014-10-17 | 2016-04-21 | Imagination Technologies, Limited | Small multiplier after initial approximation for operations with increasing precision |
| CN105389157A (en) * | 2015-10-29 | 2016-03-09 | 中国人民解放军国防科学技术大学 | Goldschmidt algorithm-based floating-point divider |
| CN107992284A (en) * | 2017-11-27 | 2018-05-04 | 中国航空无线电电子研究所 | A kind of division function implementation method of programming device |
| US20200065066A1 (en) * | 2018-08-22 | 2020-02-27 | Imagination Technologies Limited | Float Division by Constant Integer |
Non-Patent Citations (1)
| Title |
|---|
| 焦永;: "一种单精度浮点倒数开方运算的硬件实现", 电脑知识与技术, no. 09, pages 2243 - 2263 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3674883B1 (en) | Multiplication circuit, system on chip, and electronic device | |
| CN107305484B (en) | Nonlinear function operation device and method | |
| CN110688088A (en) | General nonlinear activation function computing device and method for neural network | |
| US9552189B1 (en) | Embedded floating-point operator circuitry | |
| CN111240746B (en) | Floating point data inverse quantization and quantization method and equipment | |
| CN112035796B (en) | Optimizing method of ultra-low-delay integer power computing circuit for integrated circuit | |
| CN110187866B (en) | Hyperbolic CORDIC-based logarithmic multiplication computing system and method | |
| CN111813371A (en) | Floating-point division operation method, system and readable medium for digital signal processing | |
| US6182100B1 (en) | Method and system for performing a logarithmic estimation within a data processing system | |
| US7400688B2 (en) | Path metric normalization | |
| WO2018196750A1 (en) | Device for processing multiplication and addition operations and method for processing multiplication and addition operations | |
| CN112732223A (en) | Data processing method and system for half-precision floating-point number divider | |
| CN111984226A (en) | Cube root solving device and solving method based on hyperbolic CORDIC | |
| CN110135563B (en) | Convolution neural network binarization method and operation circuit | |
| CN111753951A (en) | Information processor, information processing method, and storage medium | |
| CN110837624A (en) | Approximate calculation device for sigmoid function | |
| Yang et al. | A low-power approximate multiply-add unit | |
| Liu et al. | An efficient architecture of the sign-error LMS adaptive filter | |
| CN111897513B (en) | Multiplier based on reverse polarity technology and code generation method thereof | |
| US11494165B2 (en) | Arithmetic circuit for performing product-sum arithmetic | |
| CN112783469A (en) | Method and device for executing floating-point exponential operation | |
| CN107977587A (en) | A kind of square root function implementation method | |
| Jalaja et al. | Retime Low Power Approximate Multiplier for Image Sharpening and Smoothing | |
| CN111752532B (en) | Method, system and device for realizing 32-bit integer division with high precision | |
| Kapgate et al. | Design and implementation of complex arithmetic operations using binary logarithmic number system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |