CN112731150B - Voltage sag state estimation method, device, computer equipment and storage medium - Google Patents
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Abstract
The application relates to a voltage sag state estimation method, a voltage sag state estimation device, computer equipment and a storage medium. The method comprises the following steps: obtaining actual measurement voltage sag frequency on a first bus in a power grid to be measured to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the voltage sag of the first bus and the second bus can be caused by the fault of the preset fault point; establishing an optimization model according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point; and estimating the voltage sag frequency on the second bus according to the fault frequency matrix. By adopting the method, the model can be simplified, so that the data calculation amount in the estimated voltage sag frequency can be reduced, and the calculation efficiency can be improved.
Description
Technical Field
The present disclosure relates to the field of power systems, and in particular, to a method and apparatus for estimating a voltage sag state, a computer device, and a storage medium.
Background
The Voltage Sag (Voltage Sag) is a phenomenon that the effective value of the power frequency Voltage at a certain point in a power system is reduced to 10% -90% of the rated Voltage and is generally kept for 10 ms-1 min and then restored to a normal level, and is an important factor affecting the quality of electric energy. When the voltage sag is severe, short circuit faults of buses in the power grid can be caused, normal operation of sensitive equipment is affected, and huge economic losses are brought to power enterprises and users. The voltage sag state can be represented by the voltage sag frequency, the voltage sag frequency is monitored and analyzed in real time, technicians can take effective measures in time to reduce the frequency of occurrence of the voltage sag, the problem of electric energy quality is improved, and then economic loss caused by the voltage sag is reduced.
In the traditional technology, a numerical solution is adopted to estimate the voltage sag frequency of the whole network bus by using limited voltage sag frequency monitoring data.
However, the mathematical model of the numerical solution is complex, the calculation amount is large, and the calculation efficiency is low.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a voltage sag state estimation method, apparatus, computer device, and storage medium.
A voltage sag state estimation method, comprising:
obtaining actual measurement voltage sag frequency on a first bus in a power grid to be measured to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the first bus and the second bus are likely to generate voltage sag when the preset fault point generates a fault;
establishing an optimization model according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point;
and estimating the voltage sag frequency on the second bus according to the fault frequency matrix.
In one embodiment, the frequency of failure matrix established based on the preset failure point is equal to the product of the sparse base matrix and the sparse representation coefficient matrix; the sparse base matrix is a sparse base constant matrix used for selected sparse conversion, and the fault frequency matrix and the sparse representation coefficient matrix are both unknown quantity matrices.
In one embodiment, according to a measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, and a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, an optimization model is established, and the fault frequency matrix is determined according to the optimization model, including:
based on the sparse property of the sparse representation coefficient, an optimization model is established through a non-convex tracking algorithm in the compressed sensing theory:
wherein,,
as an objective function, H=Aθ is a constraint condition, p is more than or equal to 0<1，‖θ‖ p Indicating lp norm, argmin indicating the choice of +.>
The minimum sparse representation coefficient matrix theta is used as a target solution of the sparse representation coefficient matrix theta; />
A target solution for sparsely representing the coefficient matrix theta; the preset voltage sag state estimation model is H=MX, H is a measurement matrix, X is a fault frequency matrix, and M is a relation matrix constant between the measurement matrix H and the fault frequency matrix X determined by the network topology of the power grid to be tested; a is a sensing matrix constant, a=mψ;
and determining a fault frequency matrix according to the optimization model.
In one embodiment, determining the failure frequency matrix according to the optimization model includes:
according to the iterative re-weighting least square method theory, the objective function is made to be 
=weighted l2 norm->
Obtaining a target optimization model:
wherein θ i Is a sparse tableShowing the ith element in coefficient matrix θ; omega i A weighting coefficient that is a weighted l2 norm;
according to the target optimization model, an iterative solution formula of the sparse representation coefficient matrix theta is obtained:
θ (n) ＝Q n A T (AQ n A T ) -1 H；
wherein,,
ω i ＝|θ (n-1) | p-2 ；
setting a sparse initial value for the sparse representation coefficient matrix theta, iterating, and when the absolute value theta is equal to the absolute value of the sparse representation coefficient matrix theta (n) -θ (n-1) |<When epsilon, obtaining a target solution of the sparse representation coefficient matrix theta; wherein epsilon is a preset iteration ending threshold;
and carrying the target solution of the sparse representation coefficient matrix theta into X=ψθ to obtain a fault frequency matrix X.
In one embodiment, estimating the voltage sag frequency on the second bus according to the failure frequency matrix includes:
short circuit calculation is carried out on a preset fault point corresponding to the fault frequency which is not 0 in the fault frequency matrix so as to determine whether voltage sag occurs on the second bus;
if yes, determining that the fault frequency corresponding to the preset fault point in the fault frequency matrix is the estimated initial voltage sag frequency on the second bus;
and determining the estimated voltage sag frequency on the second bus according to the estimated initial voltage sag frequency on the second bus.
In one embodiment, performing short circuit calculation on a corresponding preset fault point in the fault frequency matrix to determine whether a voltage sag occurs on the second bus includes:
Calculating the voltage on the second bus corresponding to the preset fault point when the corresponding preset fault point in the fault frequency matrix is short-circuited;
acquiring the ratio of the voltage on the second bus to the normal voltage;
if the ratio is smaller than a preset ratio threshold, determining that voltage sag occurs on the second bus;
if the ratio is not less than the ratio threshold, it is determined that no voltage dip occurs on the second bus.
In one embodiment, determining the estimated voltage dip frequency on the second bus based on the estimated initial voltage dip frequency on the second bus includes:
and obtaining the sum of the initial voltage sag frequencies on the same second bus to obtain the estimated voltage sag frequency on the second bus.
A voltage sag state estimation device, comprising:
the data acquisition module is used for acquiring the actual measurement voltage sag frequency on the first bus in the power grid to be measured to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the first bus and the second bus are likely to generate voltage sag when the preset fault point generates a fault;
The fault estimation module is used for establishing an optimization model according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point;
and the dip estimation model is used for estimating the voltage dip frequency on the second bus according to the fault frequency matrix.
A computer device comprising a memory storing a computer program and a processor which when executing the computer program performs the steps of:
obtaining actual measurement voltage sag frequency on a first bus in a power grid to be measured to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the fault of the preset fault point can lead the first bus and the second bus to generate the voltage sag;
Establishing an optimization model according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point;
and estimating the voltage sag frequency on the second bus according to the fault frequency matrix.
A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of:
obtaining actual measurement voltage sag frequency on a first bus in a power grid to be measured to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the first bus and the second bus are likely to generate voltage sag when the preset fault point generates a fault;
establishing an optimization model according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point;
And estimating the voltage sag frequency on the second bus according to the fault frequency matrix.
According to the voltage sag state estimation method, the device, the computer equipment and the storage medium, the measurement matrix is obtained by obtaining the actual measurement voltage sag frequency on the first bus of the power grid to be measured; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the first bus and the second bus are likely to generate voltage sag when the preset fault point generates a fault; establishing an optimization model according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point; and estimating the voltage sag frequency on the second bus according to the fault frequency matrix to simplify the model, reduce the data calculation amount in the estimated voltage sag frequency and improve the calculation efficiency.
Drawings
FIG. 1 is a flow chart of a voltage sag state estimation method according to an embodiment;
FIG. 2 is a flow chart illustrating determining a failure frequency matrix according to one embodiment;
FIG. 3 is a flowchart of another embodiment of a method for estimating a voltage sag state;
FIG. 4 is a block diagram of a voltage sag state estimation device according to one embodiment;
fig. 5 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
The power grid to be tested comprises a plurality of power grid buses, wherein a voltage sag monitoring device is arranged on part of the power grid buses, namely the first bus, actual measurement voltage sag frequency of voltage sag on the first bus can be directly detected and obtained through the voltage sag monitoring device, and the frequency of voltage sag on the second bus cannot be directly obtained if the voltage sag monitoring device is not arranged on part of the buses, namely the second bus. According to the voltage sag state estimation method, the voltage sag frequency on the second bus can be estimated according to the actually measured voltage sag frequency on the first bus, so that the voltage sag state on the second bus can be determined. In this embodiment, as shown in fig. 1, the method includes the following steps:
S110, obtaining the actual measurement voltage sag frequency on a first bus in the power grid to be measured, and obtaining a measurement matrix.
The power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the fault of the preset fault point may lead to the voltage sag of the first bus and the second bus. The power grid to be tested comprises at least one preset fault point, at least one first bus and at least one second bus.
Optionally, the preset fault point is a specific position on a line connected to the grid bus in the to-be-tested power grid, and may also be a specific position of a device connected to the grid bus in the to-be-tested power grid. The preset fault points can be correspondingly connected with a plurality of power grid buses, and each fault point can cause voltage sag of the corresponding connected power grid buses.
Specifically, the computer equipment obtains actual measurement voltage dip frequencies on a first bus without a voltage dip monitoring device in the power grid to be measured, each actual measurement voltage dip frequency corresponds to a first bus, and n actual measurement voltage dip frequencies h are obtained i And correspondingly forming an n multiplied by 1 measurement matrix H.
S120, an optimization model is built according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix built based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix which are related to the fault frequency matrix, and the fault frequency matrix is determined according to the optimization model.
The fault frequency matrix comprises fault frequencies corresponding to each preset fault point in the preset number of preset fault points. For example, the frequency x of faults corresponding to each of the z preset fault points is included i A zx1 failure frequency matrix X is formed. The preset voltage sag state estimation model is used for estimating a fault frequency matrix formed by preset fault points which possibly generate faults according to an actual measurement voltage sag frequency matrix on the first bus, and the fault frequency matrix has sparse priori and can be determined by a sparse base matrix and a sparse representation coefficient matrix.
The computer equipment replaces a fault frequency matrix in the voltage sag state estimation model, the fault frequency matrix is represented by a sparse basis matrix and a sparse representation coefficient matrix to obtain a relational expression about the measurement matrix, the sparse basis matrix and the sparse representation coefficient matrix, the measurement matrix is input into the relational expression, the sparse representation coefficient matrix is obtained through solving, and the fault frequency matrix is determined according to the relation among the fault frequency matrix, the sparse basis matrix and the sparse representation coefficient matrix.
S130, estimating the voltage sag frequency on the second bus according to the fault frequency matrix.
Specifically, the computer equipment determines whether voltage sag occurs on the corresponding power grid bus when each preset fault point fails according to the obtained fault frequency matrix. If yes, the computer equipment determines that the fault frequency corresponding to the preset fault point is the estimated voltage sag frequency on the power grid bus which is corresponding to the preset fault point and is subjected to voltage sag. For example, the preset fault point a corresponds to the second buses 1 to 3, after calculation, it is determined that if the preset fault point a fails, voltage sag occurs in the second buses 1 and 3, and if the fault frequency of the preset fault point a is 5 times, the estimated voltage sag frequency on the corresponding second buses 1 and 3 is also 5 times.
In this embodiment, the computer device obtains the measured voltage sag frequency on the first bus on which the voltage sag monitoring device is installed in the power grid to be measured, obtains the measurement matrix, establishes a failure frequency matrix of a preset failure point based on the preset failure point according to the measurement matrix and the preset voltage sag state estimation model, establishes an optimization model according to the sparse base matrix and the sparse representation coefficient matrix related to the failure frequency matrix, determines the failure frequency matrix according to the optimization model, and predicts the voltage sag frequency on the second bus on which the voltage sag monitoring device is not set according to the failure frequency matrix. By the method, the sparse priori property of the fault frequency matrix is utilized, the fault frequency matrix in the voltage sag state estimation model is replaced by the sparse base matrix and the sparse representation coefficient matrix, the model is simplified, the data calculation amount in the estimated voltage sag frequency is reduced, and the calculation efficiency is improved.
In one embodiment, the fault frequency matrix may be solved by using a non-convex-based tracking algorithm in the compressed sensing theory, as shown in fig. 2, S120 includes:
s210, based on the sparse property of the sparse representation coefficient, establishing an optimization model through a non-convex tracking algorithm in the compressed sensing theory:
wherein,,
as an objective function, H=Aθ is a constraint condition, p is more than or equal to 0<1，‖θ‖ p Indicating lp norm, argmin indicating the choice of +.>
The minimum sparse representation coefficient matrix theta is used as a target solution of the sparse representation coefficient matrix theta; />
A target solution for sparsely representing the coefficient matrix theta; the preset voltage sag state estimation model is h=mx, and H is the quantityThe measurement matrix, X is a fault frequency matrix, M is a relation matrix constant between a measurement matrix H and the fault frequency matrix X, which are determined by the network topology of the power grid to be measured; a is the sensing matrix constant, a=mψ.
Specifically, the voltage sag state estimation model satisfies h=mx, and the computer device decomposes the fault frequency matrix X into a sparse base matrix ψ and a sparse representation coefficient matrix θ by using the sparse priori of the fault frequency matrix X, so as to obtain a sparse expression x=ψθ of the fault frequency matrix X, i.e. the fault frequency matrix X is equal to the product of the sparse base matrix ψ and the sparse representation coefficient matrix θ. The sparse base matrix ψ is a sparse base constant matrix used for the selected sparse conversion, and the fault frequency matrix X and the sparse representation coefficient matrix theta are both unknown quantity matrices. The computer device replaces X in the voltage sag state estimation model h=mx with x=ψθ, resulting in h=aθ.
S220, determining a fault frequency matrix according to the optimization model.
Specifically, the computer device makes the objective function according to the iterative re-weighted least square theory
Obtaining a target optimization model:
wherein θ i An ith element in the sparse representation coefficient matrix theta; omega i Is the weighting coefficient of the l2 norm.
According to the optimization model, the iterative solving formula of theta can be obtained as follows:
θ (n) ＝Q n A T (AQ n A T ) -1 H
where n is the number of iterations, Q n Is a diagonal matrix, and the expression is:
to meet the requirements
Is a first order approximation of the weighting coefficient omega i θ according to the previous iteration (n-1) And (3) calculating:
ω i ＝|θ (n-1) | p-2
the computer equipment sets a sparse initial value for theta, and carries out iteration in the target optimization model when the initial value is |theta (n) -θ (n-1) |<And when epsilon, the outputted theta is the target solution of the sparse representation coefficient matrix theta. Wherein epsilon is a preset iteration end threshold.
The computer equipment utilizes the sparse expression X=ψθ of the fault frequency matrix X to bring the target solution of the sparse representation coefficient matrix θ obtained by solving into the X=ψθ to obtain the fault frequency matrix X.
In this embodiment, the computer device converts the voltage sag state estimation model h=mx into the target estimation model h=aθ by using the sparse expression x=ψθ of the failure frequency matrix X, constructs the target optimization model, and solves the failure frequency matrix by using the non-convex basis tracking algorithm in the compressed sensing theory, thereby simplifying the model, reducing the data calculation amount, and further improving the calculation efficiency.
In one embodiment, to improve the accuracy of the estimated voltage sag frequency on the second bus where the voltage sag monitoring device is not provided, as shown in fig. 3, S130 includes:
s330, carrying out short circuit calculation on a preset fault point corresponding to the fault frequency which is not 0 in the fault frequency matrix so as to determine whether voltage sag occurs on the second bus.
The voltage sag of the second bus corresponding to the preset fault point is not necessarily caused by the fault of the preset fault point, and when the computer equipment needs to be short-circuited according to the preset fault point, the voltage on each second bus is specifically determined whether the voltage sag can occur on the second bus.
Specifically, the computer device calculates the failure frequency of the failure frequency matrix to be not 0 pairsWhen the corresponding preset fault point is short-circuited, the voltage on the second bus corresponding to the preset fault point is obtained, the ratio of the voltage on the corresponding second bus to the normal voltage value on the second bus is obtained, and whether the voltage sag occurs on the second bus is determined according to the ratio and the preset ratio threshold. If the obtained ratio is smaller than the ratio threshold, the computer equipment determines that voltage sag can occur on the second bus; if the ratio is not less than the ratio threshold, the computer device determines that no voltage sag occurs on the second bus. For example, the failure frequency matrix X includes failure frequencies X corresponding to the preset failure points B1 to B5, respectively 1 ～x 5 Wherein x is 1 ＝0，x 2 ＝0，x 3 ＝3，x 4 ＝0，x 5 Computer equipment calculates x in failure frequency matrix 3 When the preset fault point B3 corresponding to=3 is short-circuited, the voltage U on the second bus corresponding to the preset fault point B3 3 And then according to the voltage U 3 And normal voltage value U 0 It is determined whether a voltage sag will occur to the second bus. Wherein the second buses comprise 3, namely the second buses 1-3 respectively, and after short circuit calculation is carried out on a preset fault point B3, the voltage U of the second buses 1-3 is correspondingly obtained 3-1 ，U 3-2 And U 3-3 And get the sum U 0 And finally comparing the obtained ratio with a preset ratio threshold value of 90% to determine whether voltage sag occurs on the second buses 1-3. For example, if U 3-1 /U 0 =95%, no voltage dip is determined to occur on the corresponding second bus 1, if U 3-2 /U 0 =75%, determining that a voltage dip will occur on the second net bus 2, if U 3-3 /U 0 =60%, and voltage sag is determined to occur for the second bus 3.
And S320, if so, determining that the fault frequency corresponding to the preset fault point in the fault frequency matrix is the estimated initial voltage sag frequency on the second bus.
Specifically, if a voltage sag occurs on the second bus, the computer device determines that the failure frequency corresponding to the preset failure point in the failure frequency matrix is the estimated initial voltage sag on the second bus Down-converting. For example, after the computer device determines that a voltage sag occurs on the second bus 2 and 3, determining the failure frequency x corresponding to the preset failure point B3 3 =3 is the estimated initial voltage dip frequency on the second bus bars 2 and 3.
S330, determining the estimated voltage sag frequency on the second bus according to the estimated initial voltage sag frequency on the second bus.
The second bus corresponding to the different preset fault points may have repetition, for example, the preset fault point C1 corresponds to the second bus 1,2,3, the preset fault point C2 corresponds to the second bus 2 and 5, and the preset fault point C3 corresponds to the second bus 4,5,6. The computer device then adds up the initial voltage dip frequencies of the same second bus to calculate the estimated voltage dip frequency on each second bus.
Specifically, the computer device obtains the sum of the estimated initial voltage sag frequencies in the same second bus to obtain the estimated voltage sag frequency of each second bus. For example, the second buses corresponding to the preset fault point C1 include 3 second buses 1,2 and 3, respectively, the second buses 2 and 5 corresponding to the preset fault point C2, and the second buses 4,5 and 6 corresponding to the preset fault point C3. After calculation, the computer determines that voltage sag will occur in the second buses 2,5 and 6, the failure frequency of the preset failure point C1 is 2, the initial voltage sag frequency of the second bus 2 is 2, the failure frequency of the preset failure point C2 is 5, the initial voltage sag frequencies of the second buses 2 and 5 are both 5, the failure frequency of the preset failure point C3 is 11, the initial voltage sag frequencies of the second buses 5 and 6 are both 11, the final estimated voltage sag frequency of the second bus 2 is 2+5=7, the estimated voltage sag frequency of the second bus 5 is 5+11=16, and the estimated voltage sag frequency of the second bus 6 is 11.
In this embodiment, the computer device performs short-circuit calculation on a preset fault point corresponding to a fault frequency which is not 0 in the fault frequency matrix, so as to determine whether a voltage dip occurs on the second bus, and uses the fault frequency as an initial voltage dip of the second bus where the voltage dip occurs, so as to obtain a sum of initial voltage dips on the same second bus where the voltage dip occurs, so as to obtain a predicted voltage dip frequency on each second bus, thereby improving the accuracy of predicting the voltage dip frequency of each power grid bus.
It should be understood that, although the steps in the flowcharts of fig. 1-3 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1-3 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of the steps or stages in other steps or other steps.
In one embodiment, as shown in fig. 4, there is provided a voltage sag state estimation apparatus including: a data acquisition module 401, a fault estimation module 402, and a dip estimation module 403, wherein:
the data acquisition module 401 is configured to acquire a measured voltage sag frequency on a first bus in a power grid to be measured, so as to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the first bus and the second bus are likely to generate voltage sag when the preset fault point generates a fault;
the fault estimation module is used for establishing an optimization model according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point;
And the dip estimation model is used for estimating the voltage dip frequency on the second bus according to the fault frequency matrix.
In one embodiment, the frequency of failure matrix established based on the preset failure point is equal to the product of the sparse base matrix and the sparse representation coefficient matrix; the sparse base matrix is a sparse base constant matrix used for selected sparse conversion, and the fault frequency matrix and the sparse representation coefficient matrix are both unknown quantity matrices.
In one embodiment, the fault estimation module 402 is specifically configured to:
based on the sparse property of the sparse representation coefficient, an optimization model is established through a non-convex tracking algorithm in the compressed sensing theory:
wherein,,
as an objective function, H=Aθ is a constraint condition, p is more than or equal to 0<1，‖θ‖ p Indicating lp norm, argmin indicating the choice of +.>
The minimum sparse representation coefficient matrix theta is used as a target solution of the sparse representation coefficient matrix theta; />
A target solution for sparsely representing the coefficient matrix theta; the preset voltage sag state estimation model is H=MX, H is a measurement matrix, X is a fault frequency matrix, and M is a relation matrix constant between the measurement matrix H and the fault frequency matrix X determined by the network topology of the power grid to be tested; a is a sensing matrix constant, a=mψ; and determining a fault frequency matrix according to the optimization model.
In one embodiment, the fault estimation module 402 is specifically configured to:
according to the iterative re-weighted least square theory, orderIn a standard function
=weighted l2 norm->
Obtaining a target optimization model:
wherein θ i An ith element in the sparse representation coefficient matrix theta; omega i A weighting coefficient that is a weighted l2 norm;
according to the target optimization model, an iterative solution formula of the sparse representation coefficient matrix theta is obtained:
θ (n) ＝Q n A T (AQ n A T ) -1 H；
wherein,,
ω i ＝|θ (n-1) | p-2 ；
setting a sparse initial value for the sparse representation coefficient matrix theta, iterating, and when the absolute value theta is equal to the absolute value of the sparse representation coefficient matrix theta (n) -θ (n-1) |<When epsilon, obtaining a target solution of the sparse representation coefficient matrix theta; wherein epsilon is a preset iteration ending threshold;
and carrying the target solution of the sparse representation coefficient matrix theta into X=ψθ to obtain a fault frequency matrix X.
In one embodiment, the dip estimation module 403 is specifically configured to:
short circuit calculation is carried out on a preset fault point corresponding to the fault frequency which is not 0 in the fault frequency matrix so as to determine whether voltage sag occurs on the second bus; if yes, determining that the fault frequency corresponding to the preset fault point in the fault frequency matrix is the estimated initial voltage sag frequency on the second bus; and determining the estimated voltage sag frequency on the second bus according to the estimated initial voltage sag frequency on the second bus.
In one embodiment, the dip estimation module 403 is specifically configured to:
calculating the voltage on the second bus corresponding to the preset fault point when the corresponding preset fault point in the fault frequency matrix is short-circuited; acquiring the ratio of the voltage on the second bus to the normal voltage value; if the ratio is smaller than a preset ratio threshold, determining that voltage sag occurs on the second bus; if the ratio is not less than the ratio threshold, it is determined that no voltage dip occurs on the second bus.
In one embodiment, the dip estimation module 403 is specifically configured to:
and obtaining the sum of the initial voltage sag frequencies on the same second bus to obtain the estimated voltage sag frequency on the second bus.
For specific limitation of the estimating device of the dip frequency, reference may be made to the limitation of the estimating method of the dip frequency hereinabove, and the description thereof will not be repeated here. All or part of each module in the estimated device of the voltage sag frequency can be realized by software, hardware and a combination thereof. The above modules may be embedded in hardware or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
In one embodiment, a computer device is provided, which may be a terminal, and the internal structure of which may be as shown in fig. 5. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless mode can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a method of estimating a state of a pressure dip. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It will be appreciated by those skilled in the art that the structure shown in fig. 5 is merely a block diagram of some of the structures associated with the present application and is not limiting of the computer device to which the present application may be applied, and that a particular computer device may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided comprising a memory and a processor, the memory having stored therein a computer program, the processor when executing the computer program performing the steps of:
obtaining actual measurement voltage sag frequency on a first bus in a power grid to be measured to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the first bus and the second bus are likely to generate voltage sag when the preset fault point generates a fault; establishing an optimization model according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point; and estimating the voltage sag frequency on the second bus according to the fault frequency matrix.
In one embodiment, the frequency of failure matrix established based on the preset failure point is equal to the product of the sparse base matrix and the sparse representation coefficient matrix; the sparse base matrix is a sparse base constant matrix used for selected sparse conversion, and the fault frequency matrix and the sparse representation coefficient matrix are both unknown quantity matrices.
In one embodiment, the processor when executing the computer program further performs the steps of:
based on the sparse property of the sparse representation coefficient, an optimization model is established through a non-convex tracking algorithm in the compressed sensing theory:
wherein,,
as an objective function, H=Aθ is a constraint condition, p is more than or equal to 0<1，‖θ‖ p Indicating lp norm, argmin indicating the choice of +.>
The minimum sparse representation coefficient matrix theta is used as a target solution of the sparse representation coefficient matrix theta; />
A target solution for sparsely representing the coefficient matrix theta; the preset voltage sag state estimation model is H=MX, H is a measurement matrix, X is a fault frequency matrix, and M is a relation matrix constant between the measurement matrix H and the fault frequency matrix X determined by the network topology of the power grid to be tested; a is a sensing matrix constant, a=mψ; and determining a fault frequency matrix according to the optimization model.
In one embodiment, the processor when executing the computer program further performs the steps of:
According to the iterative re-weighting least square method theory, the objective function is made to be
=weighted l2 norm->
Obtaining a target optimization model:
wherein θ i An ith element in the sparse representation coefficient matrix theta; omega i A weighting coefficient that is a weighted l2 norm;
according to the target optimization model, an iterative solution formula of the sparse representation coefficient matrix theta is obtained:
θ (n) ＝Q n A T (AQ n A T ) -1 H；
wherein,,
ω i ＝|θ (n-1) | p-2 ；
setting a sparse initial value for the sparse representation coefficient matrix theta, iterating, and when the absolute value theta is equal to the absolute value of the sparse representation coefficient matrix theta (n) -θ (n-1) |<When epsilon, obtaining a target solution of the sparse representation coefficient matrix theta; wherein epsilon is a preset iteration ending threshold; and carrying the target solution of the sparse representation coefficient matrix theta into X=ψθ to obtain a fault frequency matrix X.
In one embodiment, the processor when executing the computer program further performs the steps of:
short circuit calculation is carried out on a preset fault point corresponding to the fault frequency which is not 0 in the fault frequency matrix so as to determine whether voltage sag occurs on the second bus; if yes, determining that the fault frequency corresponding to the preset fault point in the fault frequency matrix is the estimated initial voltage sag frequency on the second bus; and determining the estimated voltage sag frequency on the second bus according to the estimated initial voltage sag frequency on the second bus.
In one embodiment, the processor when executing the computer program further performs the steps of:
calculating the voltage on the second bus corresponding to the preset fault point when the corresponding preset fault point in the fault frequency matrix is short-circuited; acquiring the ratio of the voltage on the second bus to the normal voltage value; if the ratio is smaller than a preset ratio threshold, determining that voltage sag occurs on the second bus; if the ratio is not less than the ratio threshold, it is determined that no voltage dip occurs on the second bus.
In one embodiment, the processor when executing the computer program further performs the steps of:
and obtaining the sum of the initial voltage sag frequencies on the same second bus to obtain the estimated voltage sag frequency on the second bus.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of:
obtaining actual measurement voltage sag frequency on a first bus in a power grid to be measured to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the first bus and the second bus are likely to generate voltage sag when the preset fault point generates a fault; establishing an optimization model according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on preset fault points, a sparse base matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point; and estimating the voltage sag frequency on the second bus according to the fault frequency matrix.
In one embodiment, the frequency of failure matrix established based on the preset failure point is equal to the product of the sparse base matrix and the sparse representation coefficient matrix; the sparse base matrix is a sparse base constant matrix used for selected sparse conversion, and the fault frequency matrix and the sparse representation coefficient matrix are both unknown quantity matrices.
In one embodiment, the computer program when executed by the processor further performs the steps of:
based on the sparse property of the sparse representation coefficient, an optimization model is established through a non-convex tracking algorithm in the compressed sensing theory:
wherein,,
as an objective function, H=Aθ is a constraint condition, p is more than or equal to 0<1，‖θ‖ p Indicating lp norm, argmin indicating the choice of +.>
The minimum sparse representation coefficient matrix theta is used as a target solution of the sparse representation coefficient matrix theta; />
A target solution for sparsely representing the coefficient matrix theta; the preset voltage sag state estimation model is H=MX, H is a measurement matrix, X is a fault frequency matrix, and M is a relation matrix constant between the measurement matrix H and the fault frequency matrix X determined by the network topology of the power grid to be tested; a is a sensing matrix constant, a=mψ; and determining a fault frequency matrix according to the optimization model.
In one embodiment, the computer program when executed by the processor further performs the steps of:
According to the iterative re-weighting least square method theory, the objective function is made to be
=weighted l2 norm->
Obtaining a target optimization model:
wherein θ i An ith element in the sparse representation coefficient matrix theta; omega i A weighting coefficient that is a weighted l2 norm;
according to the target optimization model, an iterative solution formula of the sparse representation coefficient matrix theta is obtained:
θ (n) ＝Q n A T (AQ n A T ) -1 H；
wherein,,
ω i ＝|θ (n-1) | p-2 ；
setting a sparse initial value for the sparse representation coefficient matrix theta, iterating, and when the absolute value theta is equal to the absolute value of the sparse representation coefficient matrix theta (n) -θ (n-1) |<When epsilon, obtaining a target solution of the sparse representation coefficient matrix theta; wherein epsilon is a preset iteration ending threshold; and carrying the target solution of the sparse representation coefficient matrix theta into X=ψθ to obtain a fault frequency matrix X.
In one embodiment, the computer program when executed by the processor further performs the steps of:
short circuit calculation is carried out on a preset fault point corresponding to the fault frequency which is not 0 in the fault frequency matrix so as to determine whether voltage sag occurs on the second bus; if yes, determining that the fault frequency corresponding to the preset fault point in the fault frequency matrix is the estimated initial voltage sag frequency on the second bus; and determining the estimated voltage sag frequency on the second bus according to the estimated initial voltage sag frequency on the second bus.
In one embodiment, the computer program when executed by the processor further performs the steps of:
calculating the voltage on the second bus corresponding to the preset fault point when the corresponding preset fault point in the fault frequency matrix is short-circuited; acquiring the ratio of the voltage on the second bus to the normal voltage value; if the ratio is smaller than a preset ratio threshold, determining that voltage sag occurs on the second bus; if the ratio is not less than the ratio threshold, it is determined that no voltage dip occurs on the second bus.
In one embodiment, the computer program when executed by the processor further performs the steps of:
and obtaining the sum of the initial voltage sag frequencies on the same second bus to obtain the estimated voltage sag frequency on the second bus.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, or the like. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory. By way of illustration, and not limitation, RAM can be in the form of a variety of forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), and the like.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method of voltage sag state estimation, the method comprising:
obtaining actual measurement voltage sag frequency on a first bus in a power grid to be measured to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the first bus and the second bus are likely to generate the voltage sag when the preset fault point generates the fault;
According to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on the preset fault points, a sparse base matrix and a sparse representation coefficient matrix which are related to the fault frequency matrix, an optimization model is established by using a non-convex base tracking algorithm in a compressed sensing theory, and the fault frequency matrix is determined according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point, and the fault frequency matrix established based on the preset fault points is equal to the product of the sparse base matrix and the sparse representation coefficient matrix; the sparse base matrix is a sparse base constant matrix used for the selected sparse conversion, and the fault frequency matrix and the sparse representation coefficient matrix are both unknown quantity matrices;
carrying out short circuit calculation on the preset fault points corresponding to the fault frequency which is not 0 in the fault frequency matrix so as to determine whether voltage sag occurs on the second bus;
if yes, determining that the fault frequency corresponding to the preset fault point in the fault frequency matrix is the estimated initial voltage sag frequency on the second bus;
and determining the estimated voltage sag frequency on the second bus according to the estimated initial voltage sag frequency on the second bus.
2. The method of claim 1, wherein the establishing an optimization model from the measurement matrix, a preset voltage sag state estimation model, a failure frequency matrix established based on the preset failure points, and a sparse basis matrix and a sparse representation coefficient matrix associated with the failure frequency matrix, and determining the failure frequency matrix from the optimization model comprises:
based on the sparse property of the sparse representation coefficient, the optimization model is established through a non-convex tracking algorithm in the compressed sensing theory:
wherein,,
as an objective function, H=Aθ is a constraint condition, p is more than or equal to 0<1，‖θ‖ p Indicating lp norm, argmin indicating the choice of +.>
The smallest sparse representation coefficient matrix theta is used as a target solution of the sparse representation coefficient matrix theta; />
A target solution of the sparse representation coefficient matrix theta; the preset voltage sag state estimation model is h=mx, H is the measurement matrix, X is the failure frequency matrix, M is a relation matrix constant between the measurement matrix H and the failure frequency matrix X, which are determined by the network topology of the power grid to be tested; a is a sensing matrix constant, a=mψ;
and determining the fault frequency matrix according to the optimization model.
3. The method of claim 2, wherein said determining said failure frequency matrix from said optimization model comprises:
according to the iterative re-weighted least square theory, the objective function is made to be
Obtaining a target optimization model:
wherein θ i An ith element in the sparse representation coefficient matrix theta; omega i A weighting coefficient for the weighted l2 norm;
obtaining an iterative solution formula of the sparse representation coefficient matrix theta according to the target optimization model:
θ (n) ＝Q n A T (AQ n A T ) -1 H；
wherein,,
ω i ＝|θ (n-1) | p-2 ；
setting a sparse initial value for the sparse representation coefficient matrix theta, iterating, and when the absolute value theta is equal to the absolute value of the sparse representation coefficient matrix theta (n) -θ (n-1) |<When epsilon, obtaining a target solution of the sparse representation coefficient matrix theta; wherein epsilon is a preset iteration ending threshold;
and carrying the target solution of the sparse representation coefficient matrix theta into X=ψθ to obtain the fault frequency matrix X.
4. The method of claim 1, wherein the performing a short circuit calculation on the corresponding preset fault point in the fault frequency matrix to determine whether a voltage sag will occur on the second bus comprises:
calculating the voltage on the second bus corresponding to the preset fault point when the corresponding preset fault point in the fault frequency matrix is short-circuited;
Acquiring the ratio of the voltage on the second bus to the normal voltage value;
if the ratio is smaller than a preset ratio threshold, determining that voltage sag occurs on the second bus;
and if the ratio is not smaller than the ratio threshold, determining that no voltage sag occurs on the second bus.
5. The method of claim 1, wherein the determining the estimated voltage sag frequency on the second bus from the estimated initial voltage sag frequency on the second bus comprises:
and obtaining the sum of the initial voltage sag frequencies on the same second bus to obtain the estimated voltage sag frequency on the second bus.
6. A voltage sag state estimation device, the device comprising:
the data acquisition module is used for acquiring the actual measurement voltage sag frequency on the first bus in the power grid to be measured to obtain a measurement matrix; the power grid to be tested comprises a preset fault point, a first bus and a second bus, wherein the first bus comprises at least one power grid bus provided with a voltage sag monitoring device, the second bus comprises at least one power grid bus not provided with the voltage sag monitoring device, the preset fault point is a position which is set in the power grid to be tested and is likely to generate a fault, and the first bus and the second bus are likely to generate the voltage sag when the preset fault point generates the fault; the fault frequency matrix established based on the preset fault points is equal to the product of the sparse base matrix and the sparse representation coefficient matrix; the sparse base matrix is a sparse base constant matrix used for the selected sparse conversion, and the fault frequency matrix and the sparse representation coefficient matrix are both unknown quantity matrices;
The fault estimation module is used for establishing an optimization model by utilizing a non-convex basis tracking algorithm in a compressed sensing theory according to the measurement matrix, a preset voltage sag state estimation model, a fault frequency matrix established based on the preset fault points, a sparse basis matrix and a sparse representation coefficient matrix related to the fault frequency matrix, and determining the fault frequency matrix according to the optimization model; the fault frequency matrix comprises fault frequencies corresponding to each preset fault point;
the dip estimation model is used for carrying out short circuit calculation on the preset fault points corresponding to the fault frequency which is not 0 in the fault frequency matrix so as to determine whether voltage dip occurs on the second bus; if yes, determining that the fault frequency corresponding to the preset fault point in the fault frequency matrix is the estimated initial voltage sag frequency on the second bus; and determining the estimated voltage sag frequency on the second bus according to the estimated initial voltage sag frequency on the second bus.
7. The apparatus of claim 6, wherein the fault prediction module is further configured to:
based on the sparse property of the sparse representation coefficient, the optimization model is established through a non-convex tracking algorithm in the compressed sensing theory:
Wherein,,
as an objective function, H=Aθ is a constraint condition, p is more than or equal to 0<1，‖θ‖ p Indicating lp norm, argmin indicating the choice of +.>
The smallest sparse representation coefficient matrix theta is used as a target solution of the sparse representation coefficient matrix theta; />
A target solution of the sparse representation coefficient matrix theta; the preset voltage sag state estimation model is h=mx, H is the measurement matrix, X is the failure frequency matrix, M is a relation matrix constant between the measurement matrix H and the failure frequency matrix X, which are determined by the network topology of the power grid to be tested; a is a sensing matrix constant, a=mψ;
and determining the fault frequency matrix according to the optimization model.
8. The apparatus of claim 7, wherein the fault prediction module is further configured to:
according to the iterative re-weighted least square theory, the objective function is made to be
Obtaining a target optimization model:
wherein θ i An ith element in the sparse representation coefficient matrix theta; omega i A weighting coefficient for the weighted l2 norm;
obtaining an iterative solution formula of the sparse representation coefficient matrix theta according to the target optimization model:
θ (n) ＝Q n A T (AQ n A T ) -1 H；
wherein,,
ω i ＝|θ (n-1) | p-2 ；
setting a sparse initial value for the sparse representation coefficient matrix theta, iterating, and when the absolute value theta is equal to the absolute value of the sparse representation coefficient matrix theta (n) -θ (n-1) |<When epsilon, obtaining a target solution of the sparse representation coefficient matrix theta; wherein epsilon is a preset iteration ending threshold;
and carrying the target solution of the sparse representation coefficient matrix theta into X=ψθ to obtain the fault frequency matrix X.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements the steps of the method of any one of claims 1 to 5 when the computer program is executed.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 1 to 5.
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