CN112730960B - Peak protection circuit - Google Patents
Peak protection circuit Download PDFInfo
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- CN112730960B CN112730960B CN202110090703.8A CN202110090703A CN112730960B CN 112730960 B CN112730960 B CN 112730960B CN 202110090703 A CN202110090703 A CN 202110090703A CN 112730960 B CN112730960 B CN 112730960B
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- 238000005070 sampling Methods 0.000 claims abstract description 40
- 238000001514 detection method Methods 0.000 claims abstract description 36
- 239000003990 capacitor Substances 0.000 claims description 105
- 238000007599 discharging Methods 0.000 claims description 24
- 230000010355 oscillation Effects 0.000 claims description 21
- 230000010354 integration Effects 0.000 claims description 18
- 238000006243 chemical reaction Methods 0.000 claims description 16
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 230000000087 stabilizing effect Effects 0.000 claims description 6
- 230000002265 prevention Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000003245 working effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
- G01R19/1658—AC voltage or recurrent signals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/18—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using conversion of DC into AC, e.g. with choppers
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
- H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
- H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses a peak protection circuit, which comprises a control unit, an inversion unit, a sampling detection unit, a timing starting unit and a control unit, wherein an input end, an output end and a reference voltage end are arranged on the control unit, the sampling detection unit and the timing starting unit are electrically connected with the input end, the output end is electrically connected with the inversion unit, the inversion unit is electrically connected with the sampling detection unit, the output end is further electrically connected with the timing starting unit, the timing starting unit is electrically connected with the reference voltage end, the overcurrent and instantaneous high peak value of the inversion circuit can be detected, the inversion output can be effectively stopped after the set reference voltage is exceeded, the circuit is protected, and the peak protection circuit has a timing self-starting function and has the advantages of safety and high efficiency.
Description
Technical Field
The invention belongs to the technical field of electronic equipment, and particularly relates to a peak protection circuit.
Background
The inverter is a converter for converting direct current energy into alternating current with fixed frequency and fixed voltage or frequency and voltage. The existing inverter consists of an inverter bridge, control logic and a filter circuit, wherein the output end of the inverter bridge is connected with a load end to provide working voltage for the load, if the load connected with the inverter bridge fails or a short circuit condition occurs, the inverter bridge can be abnormal, the existing inverter bridge protection circuit can cut off output after the abnormality occurs, but after the fault is eliminated, the inverter cannot be started automatically, the working efficiency is lower, in addition, the phenomenon that the peak voltage of the output end of the inverter is overlarge can occur at a certain time point in the working process of the inverter, the inverter bridge can work abnormally due to the larger peak voltage, and the peak detection protection is absent in the existing inverter.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a peak protection circuit.
The specific scheme of the invention is as follows:
the peak protection circuit comprises a control unit, an inversion unit, a sampling detection unit, a timing starting unit and a reference voltage end, wherein the control unit is provided with an input end, an output end and the reference voltage end, the sampling detection unit and the timing starting unit are electrically connected with the input end, the output end is electrically connected with the inversion unit, the inversion unit is electrically connected with the sampling detection unit, the output end is further electrically connected with the timing starting unit, and the timing starting unit is electrically connected with the reference voltage end.
The input end comprises a reverse input end and a same-direction input end, the reverse input end is electrically connected with a sampling detection unit, the sampling detection unit comprises a sampling resistor R0, a detection diode D23, a first current-limiting resistor R64, an integration capacitor C52 and an integration resistor R63, the inversion unit is connected with a power supply ground through the sampling resistor R0, the inversion unit is further connected with the detection diode D23, and the detection diode D23 is electrically connected with the reverse input end through the first current-limiting resistor R64, the integration capacitor C52 and the integration resistor R63.
The output end comprises a PWM output end and a compensation output end, wherein the PWM output end is electrically connected with the inversion unit, the compensation output end is electrically connected with the timing starting unit, the timing starting unit comprises a timing capacitor C51, a first voltage dividing resistor R61 and a second voltage dividing resistor R62, one end of the first voltage dividing resistor R61 is electrically connected with one end of the timing capacitor C51, one end of the timing capacitor C51 is electrically connected with the homodromous input end, the other end of the timing capacitor C51 is electrically connected with the compensation output end, one end of the first voltage dividing resistor R61 is also electrically connected with the reference voltage end 16 through the second voltage dividing resistor R62, and the other end of the first voltage dividing resistor R61 is electrically connected with ground.
The PWM output end comprises a first PWM output end and a second PWM output end, the inversion unit comprises an upper bridge inversion unit and a lower bridge inversion unit, wherein the first PWM output end is electrically connected with the upper bridge inversion unit, and the second PWM output end is electrically connected with the lower bridge inversion unit.
The upper bridge inversion unit and the lower bridge inversion unit comprise an inverter circuit, a bootstrap circuit and an inverter circuit, wherein the inverter circuit is electrically connected with the inverter circuit through the bootstrap circuit, and the inverter circuit are electrically connected with the PWM output end.
The inverter circuit comprises an inverter triode, a second current-limiting resistor, a third current-limiting resistor and a fourth current-limiting resistor, wherein the base electrode of the inverter triode is electrically connected with the PWM output end through the second current-limiting resistor, the base electrode of the inverter triode is also electrically connected with the emitter electrode of the inverter triode through the third current-limiting resistor, the emitter electrode of the inverter triode is electrically connected with a power supply, a first power supply and a backflow-preventing diode are arranged on the collector electrode of the inverter triode, and the first power supply is electrically connected with the collector electrode of the inverter triode through the backflow-preventing diode and the fourth current-limiting resistor.
The bootstrap circuit comprises a bootstrap capacitor and a voltage stabilizing diode, the inverter bridge circuit comprises a driving MOS tube, a conversion MOS tube, an accelerating diode, a fifth current limiting resistor, a sixth current limiting resistor, a seventh current limiting resistor, a first bias resistor, a second bias resistor, a decoupling capacitor and an output backflow preventing diode, wherein one end of the bootstrap capacitor is electrically connected with the backflow preventing diode, the other end of the bootstrap capacitor is electrically connected with an anode of the output backflow preventing diode, the anode of the output backflow preventing diode is electrically connected with a source electrode of the conversion MOS tube, a source electrode of the conversion MOS tube is electrically connected with a grid electrode of the conversion MOS tube through the voltage stabilizing diode and the second bias resistor, a cathode of the voltage stabilizing diode is connected with a grid electrode of the conversion MOS tube, a drain electrode of the conversion MOS tube is electrically connected with a collector electrode of the inversion triode through the seventh current limiting resistor, a second power supply is arranged on a drain electrode of the conversion MOS tube, the second power supply is connected with a decoupling capacitor in a bypass mode, and the second power supply and the decoupling capacitor are both connected with a drain electrode of the conversion MOS tube.
The cathode of the output backflow prevention diode is connected with the drain electrode of the driving MOS tube, the drain electrode of the driving MOS tube is electrically connected with the output end of the inversion unit, the source electrode of the driving MOS tube is electrically connected with the sampling resistor R0 and the detection diode D23 respectively, the source electrode on the driving MOS tube is connected with the grid electrode on the driving MOS tube through the first bias resistor, and the grid electrode on the driving MOS tube is electrically connected with the PWM output end through the accelerating diode, the fifth current limiting resistor and the sixth current limiting resistor.
The control unit is further provided with a power input end, a control end and a soft start end, the soft start end is provided with a soft start circuit, the soft start circuit comprises a discharging triode Q11, a third voltage dividing resistor RR, a fourth voltage dividing resistor RA, an eighth current limiting resistor R45 and a second timing capacitor C18, one end of the fourth voltage dividing resistor RA is electrically connected with a reference voltage end, the other end of the fourth voltage dividing resistor RA is electrically connected with an emitter of the discharging triode Q11 through the third voltage dividing resistor RR and the second timing capacitor C18, the emitter of the discharging triode Q11 is connected with the ground, a third voltage dividing resistor RR and the second timing capacitor C18 are connected between the emitter and a collector of the discharging triode Q11 in parallel, and a base of the discharging triode Q11 is electrically connected with a source of a driving MOS tube through the eighth current limiting resistor R45.
The power input end comprises a high-level end, a ground end and a PWM power supply end, wherein the high-level end and the PWM power supply end are electrically connected with a first power supply, the ground end is electrically connected with ground, a filter capacitor C110 is arranged between the high-level end and the ground end, the high-level end is electrically connected with the ground end through the filter capacitor C110, the control end comprises a synchronous end, an oscillator output end, an oscillation capacitor access end, an oscillation resistor access end, a discharging end and a locking control end, the synchronous end and the oscillator output end are in a suspended state, a third timing capacitor C17 is arranged on the oscillation capacitor access end, a timing resistor R50 is arranged on the oscillation capacitor access end, a discharging resistor R51 is arranged on the discharging end, the oscillation capacitor access end is electrically connected with ground through the third timing capacitor C17, the oscillation resistor access end is electrically connected with ground through the timing resistor R50, the discharging end is electrically connected with ground through the third timing capacitor C17, and the locking control end is electrically connected with ground.
The invention discloses a peak protection circuit, which is characterized in that the magnitude of a current value passing through an MOS tube in an inversion unit is acquired through a sampling resistor, the sampling resistor converts the current value into a sampling voltage value, a control unit controls the output of PWM waveforms through the magnitude of the sampling voltage value so as to control the work or stop of the inversion unit, a reference voltage is arranged on the control unit, the sampling voltage is compared with the reference voltage, if the sampling voltage exceeds the reference voltage value, the control unit stops the output of the PWM waveforms so as to stop the work of the inversion unit, and thus, when the current flowing through the MOS tube in the inversion unit is overlarge, the MOS tube can stop working, the MOS tube is effectively protected, and the safety of the circuit is improved; moreover, the detection diode, the integration capacitor and the integration resistor can be matched to extract a voltage peak value at the output end of the inversion unit, if the voltage peak value exceeds a reference voltage value, the control unit can stop PWM output, so that the inversion unit stops working, damage to equipment caused by excessive peak voltage at the moment of power-on is prevented, and the safety is further improved;
in addition, the circuit is also provided with a timing starting unit, the circuit stops outputting PWM waves due to high peak value or large current, the voltage at two ends of the timing capacitor in the timing starting unit can be used for charging the timing capacitor through the reference voltage in the control unit, when the timing capacitor is charged to meet the starting voltage, the circuit starts to perform inversion output from starting, meanwhile, a soft starting circuit on the control unit can accelerate the circuit starting, and the circuit has the advantages of improving the safety performance of the circuit and improving the working efficiency.
Drawings
Fig. 1 is a block diagram of the overall structure of the present invention.
Fig. 2 is a schematic circuit configuration diagram of the control unit, the sampling detection unit, and the timing start unit.
Fig. 3 is a schematic circuit configuration of the inverter unit.
Fig. 4 is a schematic circuit diagram of the upper bridge inverter unit and the lower bridge inverter unit.
Fig. 5 is a schematic diagram of the overall structure of the peak protection circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. It is apparent that the described embodiments are only some, but not all, implementations of the present invention, and that all other embodiments, which may be derived by persons having ordinary skill in the art without making or carrying out inventive efforts, are intended to fall within the scope of protection of the present invention.
As shown in fig. 1, the peak protection circuit comprises a control unit 21, an inversion unit 20, a sampling detection unit 17 and a timing starting unit 18, wherein an input end 19, an output end 22 and a reference voltage end 16 are arranged on the control unit 21, the sampling detection unit 17 and the timing starting unit 18 are electrically connected with the input end 19, the output end 22 is electrically connected with the inversion unit 20, the inversion unit 20 is electrically connected with the sampling detection unit 17, the output end 22 is also electrically connected with the timing starting unit 18, and the timing starting unit 18 is electrically connected with the reference voltage end 16. The control unit 21 is an IC chip in this embodiment, which is preferably SG3525.
As shown in fig. 2, the input terminal 19 includes a reverse input terminal 1 and a same-direction input terminal 2, the reverse input terminal 1 is electrically connected with the sampling detection unit 17, the sampling detection unit 17 includes a sampling resistor R0, a detection diode D23, a first current limiting resistor R64, an integration capacitor C52 and an integration resistor R63, the inverter unit 20 is connected with a power supply ground through the sampling resistor R0, the inverter unit 20 is further connected with the detection diode D23, and the detection diode D23 is electrically connected with the reverse input terminal 1 through the first current limiting resistor R64, the integration capacitor C52 and the integration resistor R63.
In this embodiment, the resistance of the sampling resistor R0 is preferably 0.1 ohm, and the sampling resistor is a noninductive resistor, which has the characteristics of low resistance and high precision. The sampling resistor R0 can collect the magnitude of the current value flowing through the MOS transistor in the inverter unit 20.
The detector diode D23 performs half-wave rectification on the ac signal output by the inverter unit 20, and the half-wave rectified signal charges the integrating capacitor C52 to maintain the peak value of the rectified pulsating dc signal, so as to obtain a gentle dc signal, where the magnitude of the gentle dc signal is the peak value of the ac signal output by the inverter unit 20 instantaneously, and inputs the peak value into the peak value control unit 21.
The output end 22 comprises a PWM output end 24 and a compensation output end 9, wherein the PWM output end 24 is electrically connected with the inversion unit 20, the compensation output end 9 is electrically connected with the timing starting unit 18, the timing starting unit 18 comprises a timing capacitor C51, a first voltage dividing resistor R61 and a second voltage dividing resistor R62, one end of the first voltage dividing resistor R61 is electrically connected with one end of the timing capacitor C51, one end of the timing capacitor C51 is electrically connected with the homodromous input end 2, the other end of the timing capacitor C51 is electrically connected with the compensation output end 9, one end of the first voltage dividing resistor R61 is also electrically connected with the reference voltage end 16 through the second voltage dividing resistor R62, and the other end of the first voltage dividing resistor R61 is electrically connected with the ground.
As shown in fig. 2 to 3, the PWM output terminal 24 includes a first PWM output terminal 14 and a second PWM output terminal 11, and the inverter unit 20 includes an upper bridge inverter unit 25 and a lower bridge inverter unit 26, wherein the first PWM output terminal 14 is electrically connected to the upper bridge inverter unit 25, and the second PWM output terminal 11 is electrically connected to the lower bridge inverter unit 26. Since the first PWM output terminal 14 and the second PWM output terminal 11 output PWM waveforms with a phase difference of 180 degrees, the upper bridge inverter unit 25 and the lower bridge inverter unit 26 may alternately operate under the driving of the first PWM output terminal 14 and the second PWM output terminal 11.
In this embodiment, the voltage at the reference voltage terminal 16 is preferably 5V, the voltage at the 5V is divided by the first voltage dividing resistor R61 and the second voltage dividing resistor R62, the voltage at both ends of the first voltage dividing resistor R61 after the voltage division is 1.1V, since one end of the first voltage dividing resistor R61 is connected to the unidirectional input terminal 2 of the control unit, the voltage at the unidirectional input terminal 2 is also 1.1V, the control unit 21 includes a comparator, the voltage at the unidirectional input terminal 1 and the unidirectional input terminal 2 are two input terminals of the comparator, wherein the voltage at the unidirectional input terminal 2 is 1.1V, the 1.1V is the reference voltage in the control unit 21, and if the input voltage at the unidirectional input terminal 1 exceeds 1.1V, the control unit 21 stops PWM output and compensation output.
In the normal working state, the compensation output end 9 outputs 5V voltage, and since one end of the timing capacitor C51 is electrically connected with the unidirectional input end 2 and the other end of the timing capacitor C51 is electrically connected with the compensation output end 9, the voltage at the unidirectional input end 2 is 1.1V, and therefore, in the normal working state, the voltage difference between the two ends of the timing capacitor C51 is 3.9V.
If the input voltage value at the inverting input terminal 1 exceeds the reference voltage value at the equidirectional input terminal 2, i.e. exceeds 1.1V, the control unit 21 stops outputting the PWM wave, at this time, the inverter unit 20 stops operating due to the lack of PWM driving, and at the same time, the output voltage at the compensating output terminal 9 is reduced from 5V to 0V, and since the voltage across the capacitor does not undergo abrupt change, the voltage at the equidirectional input terminal 2 is changed from 1.1V to-3.9V when the voltage at the compensating output terminal 9 is changed from 5V to 0V, so that the voltage across the timing capacitor C51 is still 3.9V.
At the moment that the voltage at the unidirectional input terminal 2 becomes-3.9V, the reference voltage terminal 16 starts to charge the timing capacitor C51 through the second voltage dividing resistor R62, so that the voltage at the unidirectional input single-ended 2 gradually rises to the reference voltage value, i.e. 1.1V, at this time, the timing capacitor C51 is in a charging state, so that the voltage at the unidirectional input terminal 2 rises from-3.9V to 1.1V, and the time from-3.9V to 1.1V is started at the time instant control unit 21 again.
After restarting, the compensation output end 9 of the control unit 21 outputs a 5V voltage value again, the PWM output end outputs a PWM wave to the inversion unit 20, the sampling resistor R0 samples the current in the inversion unit 20, the detection diode D23, the first current limiting resistor R64, the integrating capacitor C52 and the integrating resistor R63 perform peak extraction, the control unit 21 compares the voltage value at the inversion input end 1 with the voltage value at the same direction input end 2 again at the opposite input end 1, if the voltage value at the inversion input end 1 is still greater than the reference voltage value, it is indicated that any short circuit or overlarge peak fault exists in the inversion unit 20, the control unit 21 stops the PWM output and the voltage output at the compensation output end 9 again, at this time, the timing capacitor C51 enters a timing charging state again, until the voltage value at the inversion input end 1 is smaller than the reference voltage value 1.1V at the same direction input end after the control unit 21 starts, the control unit normally outputs a PWM wave and a 5V voltage at the compensation output end 9, so that the inversion unit 20 has a voltage value higher than the reference voltage value 1.1V at the same direction input end, if the PWM wave level in the inversion unit 21 is higher than the PWM input end 2, and the PWM wave is higher than the normal, if the PWM signal is higher than the normal voltage value at the opposite input end 2.
As shown in fig. 3 to 4, the upper bridge inverter unit 25 and the lower bridge inverter unit 26 each include an inverter circuit 37, a bootstrap circuit 33, and an inverter circuit, wherein the inverter circuit 37 is electrically connected to the inverter circuit through the bootstrap circuit 33, and the inverter circuit 37 are electrically connected to the PWM output terminal 24.
Since the upper bridge inverter unit 25 is connected to the first PWM output terminal 14, the lower bridge inverter unit 26 is connected to the second PWM output terminal 11, and the first PWM output terminal 14 and the second PWM output terminal 11 output PWM waveforms 180 degrees out of phase, the upper bridge inverter unit 25 and the lower bridge inverter unit 26 can perform an alternate operation.
In a specific operation process, as shown in fig. 3, if the PWM wave output by the first PWM output terminal 14 makes the driving MOS Q5 in the upper bridge inverter unit 25 conductive, the PWM wave output by the second PWM output terminal 11 makes the driving MOS Q6 in the lower bridge inverter unit 26 conductive, and the gate voltage of the switching MOS Q7 in the upper bridge inverter unit 25 is turned off at a low level due to the inverter circuit, the gate voltage of the switching MOS Q8 in the lower bridge inverter unit 26 is turned on at a high level, after the PWM wave is turned on, the voltage at the drain D of the switching MOS Q8 in the lower bridge inverter unit 26 is transmitted to the output terminal 27 of the inverter unit through the source S of the switching MOS Q8, and meanwhile the driving MOS Q5 in the upper bridge inverter unit 25 is turned on, so that the drain D1 in the driving MOS Q5 is turned on with the source S1 of the driving MOS, and the output terminal 27 of the inverter unit connected with the drain D1 in the driving MOS Q5 in fig. 3 is turned on at a high level.
If the PWM wave output by the first PWM output end 14 turns off the driving MOS transistor Q5 in the upper bridge inverter unit 25, the PWM wave output by the second PWM output end 11 turns on the driving MOS transistor Q6 in the lower bridge inverter unit 26, and the inverter circuit turns on the switching MOS transistor Q7 in the upper bridge inverter unit, and the switching MOS transistor Q8 in the lower bridge inverter unit turns off, so that the level signals at two ends of the inverter unit output end 27 are inverted by cooperation of the switching MOS transistor Q7 in the upper bridge inverter unit and the driving MOS transistor Q6 in the lower bridge inverter unit.
Thus, as the PWM waves at the first PWM output terminal 14 and the second PWM output terminal 11 are continuously output, the inverter unit output terminal 27 outputs an alternating voltage signal, and the amplitude of the output alternating voltage signal is the same as the voltage value of V4 connected with the drain electrode of the switching MOS transistor.
As shown in fig. 4, the inverter circuit 37 includes an inverter transistor 41, a second current limiting resistor 42, a third current limiting resistor 43 and a fourth current limiting resistor 40, where the base of the inverter transistor 41 is connected to the first PWM output terminal 14 or the second PWM output terminal 11 through the second current limiting resistor 42, the base of the inverter transistor 41 is further electrically connected to the emitter of the inverter transistor 41 through the third current limiting resistor 43, the emitter of the inverter transistor 41 is electrically connected to a power supply, a first power supply 38 and a backflow preventing diode 39 are disposed on the collector of the inverter transistor 41, the first power supply 38 is electrically connected to the collector of the inverter transistor 41 through the backflow preventing diode 39 and the fourth current limiting resistor 40, and the base of the inverter transistor is connected to the emitter, so that the phase of the collector output terminal of the inverter transistor is 180 degrees inverted compared with the phase of the base.
The bootstrap circuit 33 includes a bootstrap capacitor 35 and a zener diode 34, the inverter bridge circuit includes a driving MOS 48, a switching MOS 31, an accelerating diode 46, a fifth current limiting resistor 45, a sixth current limiting resistor 44, a seventh current limiting resistor 36, a first bias resistor 47, a second bias resistor 32, a decoupling capacitor 29 and an output anti-backflow diode 28, where one end of the bootstrap capacitor 35 is electrically connected with the anti-backflow diode 39, the other end of the bootstrap capacitor 35 is electrically connected with the anode of the output anti-backflow diode 28, the anode of the output anti-backflow diode 28 is electrically connected with the source of the switching MOS 31, the source of the switching MOS 31 is electrically connected with the gate of the switching MOS 31 through the zener diode 34 and the second bias resistor 32, the cathode of the switching MOS 31 is electrically connected with the gate of the switching MOS 31 through the seventh current limiting resistor 36, a second power supply 30 is disposed on the drain of the switching MOS 31, the second power supply 30 is electrically connected with the decoupling capacitor 29, and the second power supply 30 is electrically connected with the drain of the decoupling capacitor 30, and the decoupling capacitor 30 can remove noise from the power supply capacitor 30. The zener diode 34 plays a role in voltage stabilization protection between the gate and the source of the switching MOS transistor 31, and protects the PN junction of the switching MOS transistor 31 from breakdown.
The inverter circuit 37 causes the waveform signal to generate phase inversion at the collector output end of the inverter triode 41, so that only one MOS transistor in the inverter circuit is conducted, specifically, if PWM waves are output to the inverter unit, the PWM waves are transmitted in two paths, as shown in fig. 4, one path of PWM waves passes through the driving MOS transistor 48, so that the driving MOS transistor 48 becomes a conducting state, and the other path of PWM waves passes through the second current limiting resistor 42 to be transmitted to the base of the inverter triode 41, and because the base of the inverter triode 41 and the emitter of the inverter triode are in a connection state, the phase of the collector output signal at the inverter triode 41 is inverted by 180 degrees, and the PWM signals of 180 degrees are inverted, so that the switching MOS transistor 31 in fig. 4 cannot be conducted because of the inversion of the level signals.
Moreover, since the first power supply 38 charges the bootstrap capacitor 35 through the anti-backflow diode 39 when the driving MOS transistor 48 is turned on and the inverter transistor 41 is turned on, the driving MOS transistor 48 and the inverter transistor 41 are both turned off at the next moment of the PWM signal, and at this time, the accumulated charging voltage at both ends of the bootstrap capacitor 35 turns on the switching MOS transistor 31 through the fourth current limiting resistor 40 and the seventh current limiting resistor 36, and the voltage at the drain of the switching MOS transistor 31 flows to the inverter unit output terminal 27 through the source electrode on the switching MOS transistor 31 and the output anti-backflow diode 28, thereby completing one-time switching of the voltage signal.
The cathode of the output anti-backflow diode 28 is connected with the drain electrode of the driving MOS tube 48, the drain electrode of the driving MOS tube 48 is electrically connected with the output end 27 of the inversion unit, the source electrode of the driving MOS tube 48 is electrically connected with the sampling resistor R0 and the detection diode D23 respectively, the source electrode on the driving MOS tube 48 is connected with the grid electrode on the driving MOS tube 48 through the first bias resistor 47, and the grid electrode on the driving MOS tube 48 is electrically connected with the PWM output end 24 through the accelerating diode 46, the fifth current limiting resistor 45 and the sixth current limiting resistor 44. The accelerating diode 46 can make the driving MOS transistor 48 have the technical effect of being turned off rapidly and turned on slowly, so as to protect the driving MOS transistor and reduce the risk of short circuit.
As shown in fig. 2, the control unit 21 is further provided with a power input end, a control end and a soft start end 8, the soft start end 8 is provided with a soft start circuit 23, the soft start circuit 23 includes a discharging triode Q11, a third voltage dividing resistor RR, a fourth voltage dividing resistor RA, an eighth current limiting resistor R45 and a second timing capacitor C18, one end of the fourth voltage dividing resistor RA is electrically connected with the reference voltage end 16, the other end of the fourth voltage dividing resistor RA is electrically connected with an emitter of the discharging triode Q11 through the third voltage dividing resistor RR and the second timing capacitor C18, the emitter of the discharging triode Q11 is connected with the ground, a third voltage dividing resistor RR and the second timing capacitor C18 are further connected in parallel between the emitter and the collector of the discharging triode Q11, the collector of the discharging triode Q11 is electrically connected with the soft start end 8, and the base of the discharging triode Q11 is electrically connected with a source of the driving MOS 48 through the eighth current limiting resistor R45.
The soft start end 8 can accelerate the start of the control unit 21, the constant current source is provided in the control unit 21 to charge the second timing capacitor C18, when the second timing capacitor C18 is charged to a predetermined voltage value, the control unit 21 starts to operate, and in this embodiment, the second timing capacitor C18 can charge the second timing capacitor C18 through the reference voltage end 16 and the fourth voltage dividing resistor RA, so that the charging time of the second timing capacitor C18 is accelerated, that is, the start time of the control unit 21 is shortened, and the working effect is improved.
If the over-current phenomenon occurs in the inverter unit 20, the voltage of the base electrode of the discharging transistor Q11 is increased, so that the discharging transistor Q11 is turned on, at this time, the second timing capacitor C18 starts to discharge through the collector and the emitter of the discharging transistor Q11, and when the second timing capacitor C18 discharges to a certain state, the control unit 21 also stops working, and further protects the circuit.
The power input end comprises a high-level end 15, a ground end 12 and a PWM power supply end 13, the high-level end 15 and the PWM power supply end 13 are electrically connected with a first power supply 38, the ground end 12 is electrically connected with ground, a filter capacitor C110 is arranged between the high-level end 15 and the ground end 12, the high-level end 15 is electrically connected with the ground end 12 through the filter capacitor C110, the control end comprises a synchronous end 3, an oscillator output end 4, an oscillation capacitor access end 5, an oscillation resistor access end 6, a discharge end 7 and a locking control end 10, wherein the synchronous end 3 and the oscillator output end 4 are in a suspended state, a third timing capacitor C17 is arranged on the oscillation capacitor access end 5, a timing resistor R50 is arranged on the oscillation resistor access end 6, a discharge resistor R51 is arranged on the discharge end 7, the oscillation capacitor access end 5 is electrically connected with ground through the third timing capacitor C17, the oscillation resistor access end 6 is electrically connected with ground through the timing resistor R50, and the oscillation resistor access end 7 is electrically connected with the ground through the third timing capacitor C17 and the third timing capacitor C51. The high level terminal 15, the ground terminal 12 and the PWM power supply terminal 13 provide proper voltage values for the normal operation of the control unit, the locking control terminal is electrically connected with the ground to ensure the normal starting of the control unit 21, and the synchronous terminal 3, the oscillator output terminal 4, the oscillation capacitor access terminal 5, the oscillation resistor access terminal 6 and the discharge terminal provide clock references for PWM waves output by the control unit 21.
Fig. 5 shows the overall circuit structure of the peak protection circuit.
The specific working process of the peak protection circuit is as follows:
during normal operation, the control unit 21 outputs two paths of PWM signals with opposite phases, the upper bridge inverter unit 25 and the lower bridge inverter unit 26 of the two paths of PWM signals with opposite phases are alternately conducted, the upper bridge inverter unit 25 drives the MOS transistor Q5 to be conducted, the switching MOS transistor Q8 in the lower bridge inverter unit 26 is conducted, the V4 voltage is transmitted to one end of the inverter unit output end 27, and when the PWM signal arrives at the next moment, the driving MOS transistor Q6 in the lower bridge inverter unit 26 conducts the switching MOS transistor Q7 in the upper bridge inverter unit 25 to be conducted, and the switching MOS transistor Q7 transmits the V4 voltage to the other end of the inverter unit output end 27. The PWM signal is periodically changed, so that the phase of the voltage signal at the output terminal 27 of the inverter unit is also alternately changed, and an alternating voltage is outputted.
If the current at the output end 27 of the inversion unit is too large, the source voltage of the driving MOS transistor Q6 or the source voltage at the driving MOS transistor Q6 is connected with the sampling detection unit 17 and the soft start circuit 23, the sampling detection unit 17 converts the current signal into the voltage signal, the voltage signal is input into the control unit 21 for comparison, if the reference voltage is exceeded, the control unit 26 stops outputting the PWM wave and the compensation output, meanwhile, the soft start circuit 23 enables the second timing capacitor C18 to discharge at the same time, the speed of the control unit stopping outputting the PWM wave and the compensation wave is accelerated, after the control unit 26 does not output the PWM wave, the inversion unit 20 stops inverting, the circuit is effectively protected, and the compensation output end 9 stops outputting, the timing start unit 18 starts charging the timing capacitor C51, so that the control unit 21 starts outputting again, meanwhile, the reference voltage end 16 also charges the second timing capacitor C18, and the start time of the control unit 26 is accelerated.
The invention can detect the overcurrent and instantaneous high peak value of the inverter circuit, can effectively stop the inverter output after exceeding the set reference voltage, protects the circuit, has a timing self-starting function, and has the advantages of safety and high efficiency.
The technical means disclosed by the scheme of the invention is not limited to the technical means disclosed by the embodiment, and also comprises the technical scheme formed by any combination of the technical features. It should be noted that modifications and adaptations to the invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (2)
1. A peak protection circuit comprising a control unit (21) and an inverter unit (20), characterized in that: the device comprises a control unit (21), and is characterized by further comprising a sampling detection unit (17) and a timing starting unit (18), wherein an input end (19), an output end (22) and a reference voltage end (16) are arranged on the control unit (21), the sampling detection unit (17) and the timing starting unit (18) are electrically connected with the input end (19), the output end (22) is electrically connected with an inversion unit (20), the inversion unit (20) is electrically connected with the sampling detection unit (17), the output end (22) is also electrically connected with the timing starting unit (18), and the timing starting unit (18) is electrically connected with the reference voltage end (16);
the input end (19) comprises a reverse input end (1) and a same-direction input end (2), the reverse input end (1) is electrically connected with the sampling detection unit (17), the sampling detection unit (17) comprises a sampling resistor (R0), a detection diode (D23), a first current limiting resistor (R64), an integration capacitor (C52) and an integration resistor (R63), the inversion unit (20) is connected with the ground of a power supply through the sampling resistor (R0), the inversion unit (20) is also connected with a detection diode (D23), the detection diode (D23) is electrically connected with the reverse input end (1) through the first current limiting resistor (R64), the integration capacitor (C52) is connected with the integration resistor (R63) in parallel, one end of the integration capacitor (C52) and one end of the integration resistor (R63) after being connected in parallel is electrically connected with the reverse input end (1), and the other end of the integration capacitor (C52) and the integration resistor (R63) after being connected in parallel is connected with the ground;
the output end (22) comprises a PWM output end (24) and a compensation output end (9), wherein the PWM output end (24) is electrically connected with the inversion unit (20), the compensation output end (9) is electrically connected with the timing starting unit (18), the timing starting unit (18) comprises a timing capacitor (C51), a first voltage dividing resistor (R61) and a second voltage dividing resistor (R62), one end of the first voltage dividing resistor (R61) is electrically connected with one end of the timing capacitor (C51), one end of the timing capacitor (C51) is electrically connected with the same-direction input end (2), the other end of the timing capacitor (C51) is electrically connected with the compensation output end (9), one end of the first voltage dividing resistor (R61) is also electrically connected with the reference voltage end (16) through the second voltage dividing resistor (R62), and the other end of the first voltage dividing resistor (R61) is electrically connected with the reference voltage end (16);
the PWM output end (24) comprises a first PWM output end (14) and a second PWM output end (11), the inversion unit (20) comprises an upper bridge inversion unit (25) and a lower bridge inversion unit (26), wherein the first PWM output end (14) is electrically connected with the upper bridge inversion unit (25), and the second PWM output end (11) is electrically connected with the lower bridge inversion unit (26);
the upper bridge inverter unit (25) and the lower bridge inverter unit (26) comprise an inverter circuit (37), a bootstrap circuit (33) and an inverter circuit, wherein the inverter circuit (37) is electrically connected with the inverter circuit through the bootstrap circuit (33), and the inverter circuit (37) are electrically connected with the PWM output end (24);
the inverter circuit (37) comprises an inverter triode (41), a second current limiting resistor (42), a third current limiting resistor (43), a fourth current limiting resistor (40), a first power supply (38) and a backflow prevention diode (39), wherein the base electrode of the inverter triode (41) is electrically connected with the PWM output end (24) through the second current limiting resistor (42), the base electrode of the inverter triode (41) is also electrically connected with the emitting electrode of the inverter triode (41) through the third current limiting resistor (43), the emitting electrode of the inverter triode (41) is electrically connected with a power supply, a first power supply (38) and the backflow prevention diode (39) are arranged on the collector electrode of the inverter triode (41), and the first power supply (38) is electrically connected with the collecting electrode of the inverter triode (41) through the backflow prevention diode (39) and the fourth current limiting resistor (40);
the bootstrap circuit (33) comprises a bootstrap capacitor (35) and a voltage stabilizing diode (34), the inverter circuit comprises a driving MOS tube (48), a conversion MOS tube (31), an accelerating diode (46), a fifth current limiting resistor (45), a sixth current limiting resistor (44), a seventh current limiting resistor (36), a first bias resistor (47), a second bias resistor (32), a decoupling capacitor (29) and an output backflow preventing diode (28), wherein one end of the bootstrap capacitor (35) is electrically connected with the cathode of the backflow preventing diode (39), the other end of the bootstrap capacitor (35) is electrically connected with the anode of the output backflow preventing diode (28), the anode of the output backflow preventing diode (28) is electrically connected with the source electrode of the conversion MOS tube (31), the source electrode of the conversion MOS tube (31) is electrically connected with the grid electrode of the conversion MOS tube (31) through the voltage stabilizing diode (34) and the second bias resistor (32), the cathode of the voltage stabilizing diode (34) is electrically connected with the grid electrode of the conversion MOS tube (31) through the current limiting resistor (31), the drain electrode of the conversion MOS tube (31) is electrically connected with the grid electrode (31) of the conversion MOS tube (31), the second power supply (30) is connected with the decoupling capacitor (29) in a bypass mode, and the second power supply (30) and the decoupling capacitor (29) are connected with the drain electrode of the conversion MOS tube (31);
the cathode of the output backflow prevention diode (28) is connected with the drain electrode of the driving MOS tube (48), the drain electrode of the driving MOS tube (48) is electrically connected with the output end (27) of the inversion unit, the source electrode of the driving MOS tube (48) is respectively electrically connected with the sampling resistor (R0) and the detection diode (D23), the source electrode on the driving MOS tube (48) is connected with the grid electrode on the driving MOS tube (48) through the first bias resistor (47), and the grid electrode on the driving MOS tube (48) is electrically connected with the PWM output end (24) through a parallel circuit consisting of the accelerating diode (46) and the fifth current limiting resistor (45) and the sixth current limiting resistor (44);
the control unit (21) is further provided with a power input end, a control end and a soft start end (8), the soft start end (8) is provided with a soft start circuit (23), the soft start circuit (23) comprises a discharging triode (Q11), a third voltage dividing resistor (RR), a fourth voltage dividing Resistor (RA), an eighth current limiting resistor (R45) and a second timing capacitor (C18), one end of the fourth voltage dividing Resistor (RA) is electrically connected with a reference voltage end (16), the other end of the fourth voltage dividing Resistor (RA) is electrically connected with an emitter of a discharging triode (Q11) through a parallel circuit formed by the third voltage dividing resistor (RR) and the second timing capacitor (C18), the emitter of the discharging triode (Q11) is connected with the ground, the third voltage dividing resistor (RR) and the second timing capacitor (C18) are further connected in parallel between the emitter and the collector of the discharging triode (Q11), the collector of the discharging triode (Q11) is electrically connected with the second timing capacitor (C18), and the base of the discharging triode (Q11) is electrically connected with a MOS (48) through the eighth current limiting resistor (R45).
2. The peak protection circuit according to claim 1, wherein: the power input end comprises a high-level end (15), a ground end (12) and a PWM power supply end (13), the high-level end (15) and the PWM power supply end (13) are electrically connected with a first power supply (38), the ground end (12) is electrically connected with ground, a filter capacitor (C110) is arranged between the high-level end (15) and the ground end (12), the high-level end (15) is electrically connected with the ground end (12) through the filter capacitor (C110), the control end comprises a synchronous end (3), an oscillator output end (4), an oscillation capacitor access end (5), an oscillation resistor access end (6), a discharge end (7) and a locking control end (10), wherein the synchronous end (3) and the oscillation capacitor output end (4) are in a suspended state, a third timing capacitor (C17) is arranged on the oscillation capacitor access end (5), a timing resistor (R50) is arranged on the discharge end (7), the oscillation capacitor access end (15) is electrically connected with the ground through the third timing capacitor (C17) and the third timing capacitor (C17), the oscillation capacitor access end (6) is electrically connected with the ground through the third timing resistor (R (17) and the third timing resistor (C50), the locking control end is electrically connected with the ground.
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