CN112714384A - Stereo output control device and method, electronic apparatus, and storage medium - Google Patents
Stereo output control device and method, electronic apparatus, and storage medium Download PDFInfo
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Abstract
The disclosure relates to a stereo output control device and method, electronic equipment and a storage medium, and belongs to the technical field of audio. The device includes: the loudspeaker comprises a first power amplifying circuit, a second power amplifying circuit, a first loudspeaker, a second loudspeaker and a delay circuit; a first power amplification circuit configured to receive an audio signal, the audio signal including a first channel signal and a second channel signal; outputting the first channel signal to a first speaker; transmitting the second channel signal to a second power amplifying circuit; a second power amplification circuit configured to output a second channel signal to a second speaker; and the delay circuit is configured to delay the channel signal of the first half clock period in one clock period from the first channel signal and the second channel signal by a delay time and output the delayed channel signal to the corresponding loudspeaker.
Description
Technical Field
The present disclosure relates to the field of audio technologies, and in particular, to a stereo output control apparatus and method, an electronic device, and a storage medium.
Background
Stereo sound refers to sound having a stereoscopic effect. In electronic devices, stereo sound is often implemented using two channels. A two-channel audio device has two loudspeakers, each loudspeaker being supplied with a signal separately from one channel. The signals of the two channels differ in phase so as to simulate the difference between human ears when they hear sound in nature.
Disclosure of Invention
The embodiment of the disclosure provides a stereo output control device and method, an electronic device and a storage medium, which can realize sound synchronization of left and right channels. The technical scheme is as follows:
according to an aspect of an embodiment of the present disclosure, there is provided a stereo output control apparatus including:
the loudspeaker comprises a first power amplifying circuit, a second power amplifying circuit, a first loudspeaker, a second loudspeaker and a delay circuit;
the first power amplification circuit configured to receive an audio signal comprising a first channel signal and a second channel signal; outputting the first channel signal to the first speaker; transmitting the second channel signal to the second power amplification circuit; the second power amplification circuit configured to output the second channel signal to the second speaker;
the first channel signal and the second channel signal each occupy half of a clock cycle of the audio signal; the first channel signal is one of a left channel signal and a right channel signal, and the second channel signal is the other of the left channel signal and the right channel signal;
the delay circuit is configured to delay a channel signal of a first half clock cycle within one clock cycle, of the first channel signal and the second channel signal, by a delay time, and output the delayed channel signal to a corresponding speaker.
Optionally, the delay circuit comprises a cable, an artificial line, an ultrasonic delay line, a charge coupled device, a micro sub-circuit or a non-gated sub-circuit.
Optionally, the apparatus comprises a plurality of delay circuits with different delay times;
the first power amplifying circuit includes: an acquisition sub-circuit configured to acquire a delay time; a control sub-circuit configured to control the first channel signal to pass through a delay circuit corresponding to a delay time acquired by the acquisition sub-circuit among the plurality of delay circuits;
alternatively, the second power amplifying circuit includes: an acquisition sub-circuit configured to acquire a delay time; a control sub-circuit configured to control the second channel signal to pass through a delay circuit corresponding to a delay time acquired by the acquisition sub-circuit among the plurality of delay circuits.
Optionally, when the first channel signal precedes the second channel signal within one clock cycle, the delay time is a sum of half a clock cycle of the audio signal and a transmission delay time;
when the first channel signal is behind the second channel signal in one clock cycle, the delay time is the difference between half clock cycle of the audio signal and transmission delay;
the transmission time delay refers to a time when the second channel signal is transmitted from the first power amplifying circuit to the second power amplifying circuit.
Optionally, the first power amplification circuit is further configured to receive a test signal; the first power amplifying circuit is also used for outputting the test signal to the second power amplifying circuit;
and the first power amplifying circuit and the second power amplifying circuit are both used for being electrically connected with an oscilloscope for detecting the transmission time delay.
According to an aspect of an embodiment of the present disclosure, there is provided a stereo output control method including:
receiving an audio signal, the audio signal comprising a first channel signal and a second channel signal; the first channel signal and the second channel signal each occupy half of a clock cycle of the audio signal; the first channel signal is one of a left channel signal and a right channel signal, and the second channel signal is the other of the left channel signal and the right channel signal;
and outputting the channel signal of the first channel signal and the second channel signal in the first half clock period in one clock period to a corresponding loudspeaker after delaying the delay time.
Optionally, the outputting, to a corresponding speaker, a channel signal of a first half clock cycle within one clock cycle, delayed by a delay time, of the first channel signal and the second channel signal, includes:
obtaining delay time;
and controlling the channel signal of the first half clock period in one clock period to pass through a delay circuit corresponding to the acquired delay time in a plurality of delay circuits, from among the first channel signal and the second channel signal.
Optionally, when the first channel signal precedes the second channel signal within one clock cycle, the delay time is a sum of half a clock cycle of the audio signal and a transmission delay time;
when the first channel signal is behind the second channel signal in one clock cycle, the delay time is the difference between half clock cycle of the audio signal and transmission delay;
the transmission time delay refers to a time when the second channel signal is transmitted from the first power amplifying circuit to the second power amplifying circuit.
Optionally, the method further comprises:
receiving a test signal;
and outputting the test signal to the first power amplifying circuit and the second power amplifying circuit, wherein the first power amplifying circuit and the second power amplifying circuit are both used for being electrically connected with an oscilloscope for detecting the transmission time delay.
According to an aspect of the embodiments of the present disclosure, there is provided an electronic apparatus including the stereo output control device as described above.
According to an aspect of the embodiments of the present disclosure, there is provided an electronic apparatus, including:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to load and execute the executable instructions to implement the stereo output control method as previously described.
According to an aspect of embodiments of the present disclosure, there is provided a computer-readable storage medium in which instructions are executable by a processor to perform the stereo output control method as described above.
In the embodiment of the disclosure, the host computer sends an audio signal to the first power amplifying circuit, wherein the audio signal comprises a left channel signal and a right channel signal, one part is provided for a first loudspeaker connected with the first power amplifying circuit, and the other part is provided for a second loudspeaker connected with the second power amplifying circuit. Since the left channel signal and the right channel signal each occupy a half cycle and there is a time delay from the first power amplifier circuit to the second power amplifier circuit, it is necessary to delay the audio signal located in the half cycle of the clock cycle, for example, the first power amplifier circuit may control the first speaker to sound after receiving the first channel signal and delaying the delay time before the right channel signal. Through the delay processing, the two loudspeakers can sound synchronously, and the quality of stereo output is ensured.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a block diagram of a stereo audio playback system provided by an embodiment of the present disclosure;
FIG. 2 is a flow chart illustrating a stereo output control method according to an exemplary embodiment;
FIG. 3 is a flow chart illustrating a stereo output control method according to an exemplary embodiment;
fig. 4 is a schematic diagram illustrating a configuration of a stereo output control apparatus according to an exemplary embodiment;
FIG. 5 is a block diagram illustrating an electronic device in accordance with an example embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
Fig. 1 is a block diagram of a stereo audio playing system provided in an embodiment of the present disclosure, and as shown in fig. 1, the system may include: the loudspeaker comprises a main machine 10, a first power amplification circuit 11, a second power amplification circuit 12, a first loudspeaker 13 and a second loudspeaker 14. Among them, the first power amplifying circuit 11, the second power amplifying circuit 12, the first speaker 13, and the second speaker 14 are generally packaged as one audio device, such as a speaker unit of an audio, an electronic device, or the like.
Here, the host 10 may be a mobile terminal, a computer host, or other electronic devices. The audio device may be part of the host 10, such as a speaker unit within a mobile terminal.
The audio signal generated by the host computer 10 is transmitted to the first power amplifier circuit 11 via an I2S (Inter-IC Sound) bus. The audio signals include a channel selection (WS) signal, a Clock (CLK) signal, an Output (OUT) signal, and an Input (IN) signal. The OUT signal includes both a left channel signal and a right channel signal, which are distinguished by the WS signal, and generally, one period of an audio signal is divided into 2 half periods, where one half period of the OUT signal is the left channel signal and the other half period of the OUT signal is the right channel signal. Illustratively, when the WS signal is 1, the corresponding OUT signal is a left channel signal; when the WS signal is 0, the corresponding OUT signal is the right channel signal. The IN signal serves as echo detection, and is input to the main unit 10 to detect a noise signal generated by a power amplifier circuit or the like.
The first power amplification circuit 11 may control the first speaker to emit sound using one of the left channel signal and the right channel signal based on the WS signal. Meanwhile, the first power amplification circuit 11 may transmit the other of the left channel signal and the right channel signal to the second power amplification circuit 12 based on the WS signal, and the second speaker sound emission is controlled by the second power amplification circuit 12. Here, the first power amplifying circuit 11 may be referred to as a master power amplifying circuit, and the second power amplifying circuit 12 may be referred to as a slave power amplifying circuit.
Illustratively, the first power amplifying circuit 11 may include a switch selecting circuit or processor that controls whether the audio signal is amplified and then output to the first speaker or the second power amplifying circuit 12 based on the WS signal.
The first power amplifying circuit 11 is used for performing energy amplification on one channel signal in the audio signals and then driving a loudspeaker to work and produce sound. The second power amplifying circuit 12 is used for performing energy amplification on another channel signal in the audio signal and then driving another loudspeaker to work and produce sound.
Due to the time difference between the left channel signal and the right channel signal and the transmission delay existing when the first power amplifying circuit 11 transmits the audio signal to the second power amplifying circuit 12, the actual audio of the left channel and the right channel is not completely synchronized, resulting in poor stereo quality.
Fig. 2 is a flow chart illustrating a stereo output control method according to an exemplary embodiment. Referring to fig. 2, the method is performed by the aforementioned audio device, the method comprising the steps of:
in step 101, an audio signal is received, the audio signal comprising a first channel signal and a second channel signal.
Wherein the audio signal is transmitted by the host. The first channel signal and the second channel signal each occupy a half period of a clock period of the audio signal; the first channel signal is one of a left channel signal and a right channel signal, and the second channel signal is the other of the left channel signal and the right channel signal.
In step 102, the first channel signal and the second channel signal, which are the first half clock cycle of the first channel signal in one clock cycle, are delayed by a delay time and then output to corresponding speakers.
In this step, the delay time is formed based on the time difference between the left channel signal and the right channel signal and the transmission delay.
For example, a first speaker plays a first channel of audio and a second speaker plays a second channel of audio.
If the first channel signal precedes the second channel signal within one period, the delay time is the sum of half the clock period of the audio signal and the propagation delay. At this time, the first power amplifying circuit controls the delay time of the first sound channel signal, and then the first sound channel signal is input to the first loudspeaker; the second power amplifying circuit controls the second channel signal to be input into the second loudspeaker, and synchronous playing of the left channel and the right channel is achieved.
If the second channel signal precedes the first channel signal within a period, the delay time is the difference between half a clock period and the propagation delay of the audio signal (the propagation delay is less than half a clock period). At this time, the second channel signal is controlled by the second power amplifying circuit to delay the delay time and then is input to the second loudspeaker; the first power amplifying circuit controls the first sound channel signal to be input into the first loudspeaker, and synchronous playing of the left sound channel and the right sound channel is achieved.
In the embodiment of the disclosure, the host computer sends an audio signal to the first power amplifying circuit, wherein the audio signal comprises a left channel signal and a right channel signal, one part is provided for a first loudspeaker connected with the first power amplifying circuit, and the other part is provided for a second loudspeaker connected with the second power amplifying circuit. Since the left channel signal and the right channel signal each occupy a half cycle and there is a time delay from the first power amplifier circuit to the second power amplifier circuit, it is necessary to delay the audio signal located in the half cycle of the clock cycle, for example, the first power amplifier circuit may control the first speaker to sound after receiving the first channel signal and delaying the delay time before the right channel signal. Through the delay processing, the two loudspeakers can sound synchronously, and the quality of stereo output is ensured.
In the embodiments of the present disclosure, the delay circuit may be employed to implement the delay processing of the channel signal. That is, the control channel signal passes through the delay circuit, and the time when the channel signal passes through the delay circuit is the delay time. The audio signal is input into a delay circuit for delay processing, and then the signal after delay processing is adopted to control a loudspeaker to sound, thereby ensuring the sound synchronization of the left and right sound channels. The scheme is realized by adopting the delay circuit, does not need additional control, and has convenient realization and good accuracy.
Optionally, outputting, to a corresponding speaker, a channel signal of a first half clock cycle within one clock cycle, delayed by a delay time, from the first channel signal and the second channel signal, the method includes:
obtaining delay time;
and controlling the channel signal of the first half clock period in one clock period to pass through a delay circuit corresponding to the acquired delay time among the plurality of delay circuits, of the first channel signal and the second channel signal.
In this implementation, delay circuits with various delay times may be set in advance in the audio device, so that the audio device may select a delay circuit capable of eliminating the current left and right channel delay in time delay. And the design can be suitable for audio signals with different periods, and the adaptability is stronger.
For example, a processor, a memory, and the like may be provided in the power amplification circuit provided in the embodiment of the present disclosure, and the processor may select the delay circuit based on the acquired delay time. For example, the delay circuit may be an inverter sub-circuit in the processor, so that the processor can conveniently select the delay processing in which the delay time is appropriate.
Optionally, the method further comprises:
receiving a test signal;
and outputting the test signal to a first power amplifying circuit and a second power amplifying circuit, wherein the first power amplifying circuit and the second power amplifying circuit are both used for being electrically connected with an oscilloscope for detecting transmission delay.
In the implementation mode, the transmission delay can be obtained by using an oscilloscope through the transmission of the test signal, so that the delay time can be conveniently determined.
It should be noted that, the aforementioned steps 101-102 and the aforementioned optional steps can be arbitrarily combined.
Fig. 3 is a flow chart illustrating a stereo output control method according to an exemplary embodiment. Referring to fig. 3, the method is performed by the aforementioned audio device, the method comprising the steps of:
in step 201, a test signal is received.
The test signal may be a pulse signal having an arbitrary waveform. The test signal here may be sent by the host.
In step 202, the test signal is output to a first power amplifier circuit and a second power amplifier circuit, both of which are electrically connected to an oscilloscope for detecting transmission delay.
After the test signal is sent to the audio equipment, the test signal sequentially reaches the first power amplifying circuit and the second power amplifying circuit. Because the first power amplifying circuit and the second power amplifying circuit are both used for being electrically connected with the oscilloscope for detecting the transmission delay, the time difference of the first power amplifying circuit and the second power amplifying circuit receiving the test signal can be determined through the oscilloscope, and the time difference is the transmission delay.
In step 203, a delay time is acquired.
The delay time is determined based on the propagation delay obtained in step 202 and the length of the half period of the audio signal.
In this step, the delay time may be obtained in various ways, for example:
a delay time input by a user is received. Illustratively, the audio device may be a smart sound having a touch input or voice input function so that a delay time of the user input may be acquired.
Or, a reception delay time. Illustratively, a latency time of the host transmission may be received.
Alternatively, the delay time may be obtained locally from the audio device, and may be received from the host in advance, or may be set by the user in advance. Illustratively, the audio device may have a memory in which the delay time is stored.
Alternatively, the transmission delay is acquired from an oscilloscope, and the delay time is calculated based on the transmission delay and the half-cycle length of the audio signal. In this implementation, the delay time is obtained in an automatic manner, i.e. the transmission delay is obtained from an oscilloscope, and then the delay time is calculated together with the half period length of the audio signal. The delay time may be calculated and stored locally.
In the disclosed embodiments, the audio signal includes a first channel signal and a second channel signal.
Wherein the first channel signal and the second channel signal each occupy half of a clock cycle of the audio signal; the first channel signal is one of a left channel signal and a right channel signal, and the second channel signal is the other of the left channel signal and the right channel signal.
If the first channel signal precedes the second channel signal within one period, the delay time is the sum of half the clock period of the audio signal and the propagation delay. If the second channel signal precedes the first channel signal within a period, the delay time is the difference between half a clock period of the audio signal and the propagation delay.
In one implementation, the timing relationship between the left channel signal and the right channel signal in the audio signal in the I2S protocol may be well defined, for example, the left channel signal always precedes the right channel signal, i.e. the left channel signal and the right channel signal are first in a period, so that in a scheme of calculating the delay time by the audio device itself, the audio device may set the calculated scheme to be the sum of the two signals or the difference of the two signals. In another implementation, the timing relationship between the left channel signal and the right channel signal in the audio signal may be random, in which case, the audio device may determine which of the left channel signal and the right channel signal is in front of which of the left channel signal and the right channel signal is in back of the right channel signal through the channel selection signal, and then select the corresponding manner to calculate the delay time.
Here, the length of the half period of the audio signal may be obtained based on a channel selection signal in the audio signal, for example, if a high level in the channel selection signal represents a left channel and a low level in the channel selection signal represents a right channel, the length of the half period of the audio signal may be obtained by determining the duration of the high level or the low level in one period.
In embodiments of the present disclosure, this step may be performed by a processor within a power amplification circuit in an audio device. The power amplifying circuit is used for outputting a set sound channel signal to a corresponding loudspeaker in the first power amplifying circuit and the second power amplifying circuit. The channel signal is set to be the first half clock cycle of the first channel signal and the second channel signal in one clock cycle.
In step 204, an audio signal is received.
The audio signal is transmitted over the I2S bus between the host and the audio device. Similarly, the audio signal is transmitted between the first power amplifying circuit and the second power amplifying circuit through the I2S bus.
In embodiments of the present disclosure, this step may be performed by a processor in a power amplification circuit in an audio device. The processor may implement this step in cooperation with the memory.
In step 205, of the first channel signal and the second channel signal, the channel signal of the first half clock cycle in one clock cycle is controlled to pass through a delay circuit corresponding to the acquired delay time among the plurality of delay circuits.
Here, delay circuits with various delay times may be set in advance in the audio device, so that the audio device may select a delay circuit capable of eliminating the current left and right channel delay when delaying. And the design can be suitable for audio signals with different periods, and the adaptability is stronger.
Illustratively, the delay circuit includes a cable, an emulation line, an ultrasound delay line, a charge coupled device, a micro sub-circuit, or a nor sub-circuit.
For example, the not gate sub-circuit can extend the transmission time of the not gate without changing the signal size through the not gate designed in pairs. Different delay times are realized by setting different logarithm of NOT gates.
In the embodiment of the disclosure, the delay circuit may be integrated in the power amplifying circuit, for example, the not gate sub-circuit may be a not gate sub-circuit in a processor of the power amplifying circuit, or may be disposed between the power amplifying circuit and the speaker. When the delay circuit is integrated in the power amplification circuit, the delay circuit may be disposed either before or after the power amplification sub-circuit of the power amplification circuit. That is, the amplification may be performed after the delay, or the amplification may be performed before the delay.
In embodiments of the present disclosure, this step may be performed by a processor in a power amplification circuit in an audio device.
Fig. 4 is a schematic diagram illustrating a configuration of a stereo output control apparatus according to an exemplary embodiment. The device has the function of realizing the audio equipment in the method embodiment, and the function can be realized by hardware or by executing corresponding software by hardware. As shown in fig. 4, the apparatus includes: a first power amplification circuit 301, a second power amplification circuit 302, a first speaker 303, and a second speaker 304;
the first power amplification circuit 301 is configured to receive an audio signal, the audio signal including a first channel signal and a second channel signal; outputting the first channel signal to a first speaker; transmitting the second channel signal to a second power amplifying circuit; the second power amplification circuit 302 is configured to output the second channel signal to a second speaker;
the first channel signal and the second channel signal each occupy a half period of a clock period of the audio signal; the first channel signal is one of a left channel signal and a right channel signal, and the second channel signal is the other of the left channel signal and the right channel signal.
The device also includes: and the delay circuit is configured to delay the channel signal of the first half clock period in one clock period from the first channel signal and the second channel signal by a delay time and output the delayed channel signal to the corresponding loudspeaker.
Optionally, the delay circuit comprises a cable, an artificial line, an ultrasonic delay line, a charge coupled device, a micro sub-circuit or a non-gated sub-circuit.
Taking fig. 4 as an example, the delay circuit 305 is disposed between the first power amplifying circuit 301 and the first speaker 303, and is configured to delay the first channel signal by a delay time and output the delayed first channel signal to the corresponding first speaker. In other implementations, the delay circuit 305 may also be disposed between the second power amplification circuit 302 and the second speaker 304. The delay circuit 305 is disposed at a position related to the timings of the aforementioned first channel signal and second channel signal.
Optionally, the apparatus comprises a plurality of delay circuits with different delay times:
the first power amplification circuit 301 includes: an acquisition sub-circuit configured to acquire a delay time; a control sub-circuit configured to control the first channel signal to pass through a delay circuit corresponding to the delay time acquired by the acquisition sub-circuit 301 among the plurality of delay circuits;
alternatively, the second power amplifier circuit 302 includes: an acquisition sub-circuit configured to acquire a delay time; a control sub-circuit configured to control the second channel signal to pass through a delay circuit corresponding to the delay time acquired by the acquisition sub-circuit 301 among the plurality of delay circuits.
Optionally, when the first channel signal precedes the second channel signal within one clock cycle, the delay time is the sum of half the clock cycle of the audio signal and the transmission delay time;
when the first channel signal is behind the second channel signal in one clock cycle, the delay time is the difference between half clock cycle of the audio signal and the transmission delay;
the transmission delay refers to a time when the second channel signal is transmitted from the first power amplifying circuit to the second power amplifying circuit.
In the embodiment of the present disclosure, in addition to the delay circuit being disposed between the power amplification circuit and the speaker as shown in the figure, the delay circuit may also be integrated in the power amplification circuit, for example, the not-gate sub-circuit may be a not-gate sub-circuit within a processor in the power amplification circuit. When the delay circuit is integrated in the power amplification circuit, the delay circuit may be disposed either before or after the power amplification sub-circuit. That is, the amplification may be performed after the delay, or the amplification may be performed before the delay.
Optionally, the first power amplification circuit 301 is further configured to receive a test signal; outputting a test signal to the second power amplifying circuit 302;
the first power amplifying circuit 301 and the second power amplifying circuit 302 are both used for being electrically connected with an oscilloscope for detecting transmission delay.
The disclosed embodiment also provides an electronic device, which comprises the stereo output control device shown in fig. 4.
Fig. 5 is a block diagram illustrating an electronic device 400, which may be a mobile terminal, a tablet, a wearable device, etc., according to an example embodiment. Electronic device 400 may include one or more of the following components: a processing component 402, a memory 404, a power component 406, a multimedia component 408, an audio component 410, an interface for input/output (I/O) 412, a sensor component 414, and a communication component 416.
The processing component 402 generally controls overall operation of the electronic device 400, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to perform all or a portion of the steps of the methods described above. Further, the processing component 402 can include one or more modules that facilitate interaction between the processing component 402 and other components. For example, the processing component 402 can include a multimedia module to facilitate interaction between the multimedia component 408 and the processing component 402.
The memory 404 is configured to store various types of data to support operations at the electronic device 400. Examples of such data include instructions for any software program or method operating on the electronic device 400, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 404 may be implemented by any type or combination of volatile or non-volatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks.
The multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and a user. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundary of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 408 includes a front facing camera and/or a rear facing camera. The front camera and/or the rear camera may receive external multimedia data when the electronic device 400 is in an operating mode, such as a shooting mode or a video mode. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.
The audio component 410 is configured to output and/or input audio signals. For example, the audio component 410 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 400 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may further be stored in the memory 404 or transmitted via the communication component 416. In some embodiments, audio component 410 also includes a speaker for outputting audio signals.
The I/O interface 412 provides an interface between the processing component 402 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a start button, and a lock button.
The sensor component 414 includes one or more sensors for providing various aspects of status assessment for the electronic device 400. For example, the sensor component 414 can detect an open/closed state of the electronic device 400, the relative positioning of components, such as a display and keypad of the electronic device 400, the sensor component 414 can also detect a change in the position of the electronic device 400 or a component of the electronic device 400, the presence or absence of user contact with the electronic device 400, orientation or acceleration/deceleration of the electronic device 400, and a change in the temperature of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging software. In some embodiments, the sensor assembly 414 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
The communication component 416 is configured to facilitate wireless communication between the electronic device 400 and other devices. In the disclosed embodiment, the communication component 416 may access a wireless network based on a communication standard, such as 2G, 3G, 4G, or 5G, or a combination thereof, so as to implement the physical downlink control signaling detection. In an exemplary embodiment, the communication component 416 receives broadcast signals or broadcast related information from an external broadcast management system via a broadcast channel. Optionally, the communication component 416 further comprises an NFC module.
In an exemplary embodiment, the electronic device 400 may be implemented by one or more software Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic components for performing the above-described stereo output control method.
In an exemplary embodiment, a non-transitory computer-readable storage medium comprising instructions, such as the memory 404 comprising instructions, that may be executed by the processor 420 of the electronic device 400 to perform the split screen display method described above is also provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.
An exemplary embodiment of the present disclosure also provides a stereo output control system including a host and an audio device connected to the host, the audio device performing the actions as described in the foregoing method embodiments.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (12)
1. A stereo output control apparatus, characterized in that the apparatus comprises:
the loudspeaker comprises a first power amplifying circuit, a second power amplifying circuit, a first loudspeaker, a second loudspeaker and a delay circuit;
the first power amplification circuit configured to receive an audio signal comprising a first channel signal and a second channel signal; outputting the first channel signal to the first speaker; transmitting the second channel signal to the second power amplification circuit; the second power amplification circuit configured to output the second channel signal to the second speaker;
the first channel signal and the second channel signal each occupy half of a clock cycle of the audio signal; the first channel signal is one of a left channel signal and a right channel signal, and the second channel signal is the other of the left channel signal and the right channel signal;
the delay circuit is configured to delay a channel signal of a first half clock cycle within one clock cycle, of the first channel signal and the second channel signal, by a delay time, and output the delayed channel signal to a corresponding speaker.
2. The apparatus of claim 1, wherein the delay circuit comprises a cable, an artificial line, an ultrasonic delay line, a charge coupled device, a micro sub-circuit, or a non-gated sub-circuit.
3. The apparatus of claim 1, wherein the apparatus comprises a plurality of delay circuits with different delay times;
the first power amplifying circuit includes:
an acquisition sub-circuit configured to acquire a delay time; a control sub-circuit configured to control the first channel signal to pass through a delay circuit corresponding to a delay time acquired by the acquisition sub-circuit among the plurality of delay circuits;
alternatively, the second power amplifying circuit includes:
an acquisition sub-circuit configured to acquire a delay time; a control sub-circuit configured to control the second channel signal to pass through a delay circuit corresponding to a delay time acquired by the acquisition sub-circuit among the plurality of delay circuits.
4. The apparatus according to any one of claims 1 to 3, wherein the delay time is a sum of a half clock period of the audio signal and a propagation delay time when the first channel signal precedes the second channel signal within one clock period;
when the first channel signal is behind the second channel signal in one clock cycle, the delay time is the difference between half clock cycle of the audio signal and transmission delay;
the transmission time delay refers to a time when the second channel signal is transmitted from the first power amplifying circuit to the second power amplifying circuit.
5. The apparatus of claim 4, wherein the first power amplification circuit is further configured to receive a test signal; outputting the test signal to the second power amplifying circuit;
and the first power amplifying circuit and the second power amplifying circuit are both used for being electrically connected with an oscilloscope for detecting the transmission time delay.
6. A stereo output control method applied to the apparatus of claim 1, the method comprising:
receiving an audio signal, the audio signal comprising a first channel signal and a second channel signal; the first channel signal and the second channel signal each occupy half of a clock cycle of the audio signal; the first channel signal is one of a left channel signal and a right channel signal, and the second channel signal is the other of the left channel signal and the right channel signal;
and outputting the channel signal of the first channel signal and the second channel signal in the first half clock period in one clock period to a corresponding loudspeaker after delaying the delay time.
7. The method according to claim 6, wherein the outputting the channel signal of the first channel signal and the second channel signal in the first half clock cycle within one clock cycle to the corresponding speaker after delaying the delay time comprises:
obtaining delay time;
and controlling the channel signal of the first half clock period in one clock period to pass through a delay circuit corresponding to the acquired delay time in a plurality of delay circuits, from among the first channel signal and the second channel signal.
8. The method according to claim 6 or 7,
when the first channel signal precedes the second channel signal within one clock cycle, the delay time is the sum of half the clock cycle of the audio signal and the transmission delay time;
when the first channel signal is behind the second channel signal in one clock cycle, the delay time is the difference between half clock cycle of the audio signal and transmission delay;
the transmission time delay refers to a time when the second channel signal is transmitted from the first power amplifying circuit to the second power amplifying circuit.
9. The method of claim 8, further comprising:
receiving a test signal;
and outputting the test signal to the first power amplifying circuit and the second power amplifying circuit, wherein the first power amplifying circuit and the second power amplifying circuit are both used for being electrically connected with an oscilloscope for detecting the transmission time delay.
10. An electronic device characterized in that it comprises a stereo output control apparatus according to any one of claims 1 to 5.
11. An electronic device, characterized in that the electronic device comprises:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to load and execute the executable instructions to implement the stereo output control method of any of claims 6 to 9.
12. A computer-readable storage medium, wherein instructions in the computer-readable storage medium, when executed by a processor, are capable of performing the stereo output control method of any one of claims 6 to 9.
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| CN112714384B (en) | 2022-05-20 |
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