CN112713906B - Noise filtering circuit and noise filtering method - Google Patents
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Abstract
The invention provides a noise filtering circuit and a noise filtering method. The noise filtering circuit processes the received clock output signal and the data output signal through the error code checker to obtain error rate information, sends a first control signal to adjust the cut-off frequency of the noise filter according to the error rate information, and sends a second control signal to adjust the bandwidth of the analog front end, so that the useful data signal can be safely transmitted to the analog front end through the noise filter while the noise of the mobile phone is filtered.
Description
Technical Field
The present invention relates to the field of receiver devices, and in particular, to a noise filtering circuit and a noise filtering method.
Background
With the development of society, mobile phones are more and more popular in people's lives, and bring convenience to the lives and also bring problems, for example, noise of the mobile phones can interfere with other electronic devices. Sometimes, it is found that when the mobile phone is close to the screen of the notebook computer, the image of some notebook computer may flicker, mainly because the electromagnetic energy emitted by the mobile phone interferes with the normal signal transmitted by the lcd display driver. Taking a GSM mobile phone as an example, electromagnetic energy near 900MHz frequency emitted from the GSM mobile phone will act on the display driving chip to generate a periodic interference signal.
In the prior art, fig. 1 is a conventional physical layer circuit of a receiver. When there is no mobile phone noise, an Analog Front-End (AFE) of a Source Driver IC (Source Driver IC) receives and amplifies a signal of a Timing Controller (TCON), and then transfers the signal to a Clock & Data Recovery (CDR) circuit, and the CDR enters a locked state and then recovers a Clock and Data. When there is mobile noise, the mobile noise will be superimposed on the useful data signal, and then the CDR will lose lock. Therefore, a noise filter should be added in front of the AFE to reduce the noise amplitude. Fig. 2 is a conventional receiver circuit with a noise filter. The bandwidth of the noise filter is set by the CTRL _ LPF signal, controlled through a PIN (PIN) or command packet. However, as the noise frequency approaches the useful signal frequency, the noise filter also affects the amplitude of the useful signal. In addition, the data rate may vary with the display resolution, and the frequency of the moving noise may also vary with the user environment. When the frequency of the useful data signal is close to the frequency of the mobile phone noise, the problem of failure in noise filtering is caused.
Disclosure of Invention
The invention provides a noise filtering circuit and a noise filtering method, which are used for solving the problem that the noise filtering fails when the frequency of a useful data signal is close to that of mobile phone noise.
According to a first aspect of the present invention, there is provided a noise filtering circuit comprising: a noise filter for receiving an input signal and outputting a filtered signal according to a cut-off frequency of the noise filter; the analog front end is connected with the noise filter and used for amplifying the filtering signal to obtain an amplified signal; the clock data recovery circuit is connected with the analog front end and used for locking the amplified signal and outputting a clock output signal and a data output signal; the error code checker is respectively connected with the noise filter, the analog front end and the clock data recovery circuit, and is used for processing the received clock output signal and the data output signal to obtain error code rate information, sending a first control signal to finely adjust the cut-off frequency of the noise filter according to the error code rate information, and sending a second control signal to finely adjust the bandwidth of the analog front end.
In some embodiments, the noise filter is further configured to receive an adjustment control signal to coarsely adjust a cutoff frequency of the noise filter.
In some embodiments, the noise filter is a passive filter.
In some embodiments, the passive filter comprises: a first resistor, one end of which is connected to a first input signal of the input signals, and the other end of which is connected to a first node; a second resistor, one end of which is connected to a second input signal of the input signals, and the other end of which is connected to a second node; one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to a third node; one end of the second capacitor is connected to the second node, and the other end of the second capacitor is connected to a third node; wherein the first node is connected to a first filtered signal of the filtered signals and the second node is connected to a second filtered signal of the filtered signals.
In some embodiments, the analog front end comprises: a plurality of cascaded amplifiers; and the amplitude calibrator is connected with the plurality of cascaded amplifiers respectively and is used for adjusting the amplitude of the output signal of the analog front end.
In some embodiments, the amplifier comprises: one end of the third resistor is connected to a power supply signal, and the other end of the third resistor is connected to a fourth node; one end of the fourth resistor is connected to a power supply signal, and the other end of the fourth resistor is connected to a fifth node; one end of the third capacitor is connected to a power supply signal, and the other end of the third capacitor is connected to a fourth node; one end of the third capacitor is connected to a power supply signal, and the other end of the fourth capacitor is connected to a fifth node; a first transistor, a drain of which is connected to a fourth node, a gate of which is connected to a first filtered signal of the filtered signals, and a source of which is connected to a sixth node; a drain of the second transistor is connected to a fifth node, a gate of the second transistor is connected to a second filtered signal of the filtered signals, and a source of the second transistor is connected to a sixth node; and one end of the current source is connected to the sixth node, and the other end of the current source is grounded.
In some embodiments, the amplitude calibrator comprises: the first comparator is used for receiving a positive reference signal, a negative reference signal, a positive first amplified signal and a negative second amplified signal in the amplified signals to obtain a first comparison signal; the second comparator is used for receiving the positive reference signal, the negative first amplified signal and the positive second amplified signal in the amplified signals to obtain a second comparison signal; the OR gate is used for carrying out OR operation on the first comparison signal and the second comparison signal to obtain a target signal; the deburring device is used for removing burrs of the target signal; and the logic output is connected with the deburring device and is used for adjusting the amplitude calibration signal.
According to a second aspect of the present invention, there is provided a noise filtering method, which is applied to the noise filtering circuit described above, the method including: after power-on reset, the noise filtering circuit enters a training mode; coarse tuning the cut-off frequency of the noise filter; finely adjusting the cut-off frequency of the noise filter and the bandwidth of the analog front end; adjusting the amplitude of an amplified signal output by the analog front end; locking the amplified signal and outputting a clock output signal and a data output signal; processing the clock output signal and the data output signal to obtain error rate information; and when the error rate information meets the requirement of a preset parameter, transmitting the clock output signal and the data output signal to display equipment connected with the noise filtering circuit.
In some embodiments, the method further comprises: and when the error rate information does not meet the requirement of preset parameters, re-fine-adjusting the cut-off frequency of the noise filter and the bandwidth of the analog front end according to the error rate information.
In some embodiments, the method further comprises: and when the amplified signal is unlocked, the noise filtering circuit reenters the training mode.
Compared with the prior art, the invention has the beneficial effects that: the received clock output signal and the data output signal are processed through the error code checker, error code rate information is obtained, a first control signal is sent according to the error code rate information to adjust the cut-off frequency of the noise filter, and a second control signal is sent to adjust the bandwidth of the analog front end, so that the useful data signal can be safely transmitted to the analog front end through the noise filter while the noise of the mobile phone is filtered.
Drawings
Fig. 1 is a schematic diagram of a receiver circuit provided in the prior art.
Fig. 2 is a schematic diagram of another receiver circuit provided in the prior art.
Fig. 3 is a schematic diagram of a noise filtering circuit according to an embodiment of the invention.
Fig. 4 is a circuit diagram of an analog front end according to an embodiment of the present invention.
Fig. 5 is a schematic circuit diagram of a passive filter according to an embodiment of the present invention.
Fig. 6 is a circuit schematic diagram of an amplifier according to an embodiment of the present invention.
Fig. 7 is a circuit schematic diagram of an amplitude calibrator according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of a frequency response of a noise filtering circuit according to an embodiment of the present invention.
Fig. 9 is a schematic flowchart illustrating steps of a noise filtering method according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 3, the present invention provides a noise filtering circuit, which includes a noise filter 31, an analog front end 32, a clock data recovery circuit 33, and an error checker 34.
The noise filter 31 is arranged to receive input signals (VIP, VIN) and to output a filtered signal in dependence of a cut-off frequency of said noise filter 31.
In the embodiment of the present invention, the noise filter 31 is a passive filter, and the noise filter 31 is further configured to receive an adjustment control signal (CTRL _ LPF Coarse) to adjust a cut-off frequency of the noise filter, where the adjustment control signal (CTRL _ LPF Coarse) may be transmitted by the timing controller TCON.
Referring to fig. 5, an embodiment of the invention provides a passive filter, which includes a resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first node M1, a second node M2, and a third node M3.
One end of the first resistor R1 is connected to a first input signal (VIP) of the input signals, and the other end of the first resistor R1 is connected to the first node M1.
One end of the second resistor R2 is connected to a second input signal (VIN) of the input signals, and the other end of the second resistor R2 is connected to the second node M2.
One end of the first capacitor C1 is connected to the first node M1, and the other end of the first capacitor C1 is connected to the third node M3.
One end of the second capacitor C2 is connected to the second node M2, and the other end of the second capacitor C2 is connected to the third node M3.
Wherein the first node M1 is connected to a first one of the filtered signals (VP0) and the second node M2 is connected to a second one of the filtered signals (VN 0). The resistance values of the first resistor and the second resistor can be adjusted by a resistor control signal (CTRL _ RES), and the capacitance values of the first capacitor and the second capacitor can be adjusted by a capacitor control signal (CTRL _ CAP).
The analog front end 32 is connected to the noise filter 31, and the analog front end 32 is configured to amplify the filtered signal to obtain an amplified signal.
Referring to fig. 4, an embodiment of the invention provides an analog front end, including: an amplifier 41 and an amplitude calibrator 42.
A plurality of cascaded amplifiers 41.
Referring to fig. 6, the amplifier 41 includes: the circuit comprises a third resistor R3, a fourth resistor R4, a third capacitor C3, a fourth capacitor C4, a first transistor T1, a second transistor T2, a fourth node M4, a fifth node M5, a sixth node M6 and a current source A.
One end of the third resistor R3 is connected to the power signal, and the other end of the third resistor R3 is connected to the fourth node M4. The amplifier receives a resistor control signal (CTRL _ RES) to adjust the resistance of the third resistor R3.
One end of the fourth resistor R4 is connected to the power signal, and the other end of the fourth resistor R4 is connected to the fifth node M5. The amplifier receives a resistor control signal (CTRL _ RES) to adjust the resistance of the fourth resistor R4.
One end of the third capacitor C3 is connected to the power signal, and the other end of the third capacitor C3 is connected to the fourth node M4. The amplifier receives a capacitance control signal (CTRL _ CAP) to adjust the capacitance of the third capacitor C3.
One end of the fourth capacitor C4 is connected to the power signal, and the other end of the fourth capacitor C4 is connected to the fifth node M5. The amplifier receives a capacitance control signal (CTRL _ CAP) to adjust the capacitance of the fourth capacitor C4.
A drain of the first transistor T1 is connected to the fourth node M4, a gate of the first transistor T1 is connected to a first filtered signal VP0 of the filtered signals, and a source of the first transistor T1 is connected to a sixth node M6.
A drain of the second transistor T2 is connected to the fifth node M5, a gate of the second transistor T2 is connected to a second filtering signal VN0 of the filtering signal, and a source of the second transistor T2 is connected to the sixth node M6.
One end of the current source a is connected to the sixth node M6, and the other end of the current source a is grounded. The current source receives a BIAS control signal (CTRL _ BIAS) to adjust the BIAS current of the amplifier. A high dc gain means that the gain of the low frequency useful data signal can be increased.
The sizes of the resistor and the capacitor are changed through a resistor control signal (CTRL _ RES) and a capacitor control signal (CTRL _ CAP), so that the bandwidth of the passive filter is changed, and the faster cut-off frequency performance is obtained. The useful data signals can be safely transmitted to a post-stage amplifier circuit through a passive filter while the noise of the mobile phone is filtered, and the data signals are amplified through a multi-stage amplifier circuit and output by the VOP and the VON. The BIAS control signal (CTRL _ BIAS) is used to vary the current of the amplifier to adjust the output amplitude of the analog front end.
An amplitude calibrator 42 connected to a respective plurality of said cascaded amplifiers 42, said amplitude calibrator 42 being adapted to adjust the amplitude of the output signals (VOP, VON) of said analog front-end.
Referring to fig. 7, the amplitude calibrator includes a first comparator 71, a second comparator 72, an OR gate OR, a deburrer 73, and a logic outputter 74.
The first comparator 71 is configured to receive a positive reference signal (VREF _ P) and a negative reference signal (VREF _ N) and a positive first amplified signal (VOP) and a negative second amplified signal (VON) in the amplified signals, and obtain a first comparison signal.
The first comparator 72 is configured to receive a positive reference signal (VREF _ P) and a negative reference signal (VREF _ N) and a negative first amplified signal (VOP) and a positive second amplified signal (VON) of the amplified signals, and obtain a second comparison signal.
The OR gate OR is used for performing OR operation on the first comparison signal and the second comparison signal to obtain a target signal.
The deburring device 73 is used to remove burrs of the target signal.
A logic output 74 is connected to the de-burring unit 73, wherein the logic output 74 is used for adjusting the amplitude calibration signal.
Where | VREF _ P-VREF _ N | is the target amplitude, this value can be generated by a bandgap reference. VOP/VON and VREF _ P/VREF _ N are connected to the first comparator and the second comparator input, and the logic output is used to change the setting of the amplitude calibration signal, which can adaptively adjust the amplitude of VOP/VON to a target value.
A clock data recovery circuit 33 is connected to the analog front end 32, the clock data recovery circuit 33 being configured to lock the amplified signal and output a clock output signal (CKOUT) and a data output signal (DOUT).
The error checker 34 is connected to the noise filter 31, the analog front end 32 and the clock data recovery circuit 33, respectively, and the error checker 34 is configured to process the received clock output signal (CKOUT) and the data output signal (DOUT) to obtain error rate information, send a first control signal (CTRL _ LPF Fine) to adjust a cutoff frequency of the noise filter 31 according to the error rate information, and send a second control signal (CTRL _ AFE Fine) to adjust a bandwidth of the analog front end 32.
The noise filtering circuit can obtain a faster cut-off frequency performance by using a method of cascading a passive filter and a self-adaptive analog front end, and the filtering effect of the noise edge of the mobile phone is improved. The structure can effectively amplify useful data signals and attenuate useless mobile phone noise signals.
As shown in fig. 8, the frequency response of the noise filtering circuit provided in the embodiment of the present invention has a dc gain of not 0dB, and also plays a role of amplifying a useful data signal. When the frequency of the useful data signal is close to that of the mobile phone interference noise, the mobile phone interference noise can be filtered under the condition of ensuring the integrity of the useful data signal.
As shown in fig. 9, an embodiment of the present invention provides a noise filtering method, which is suitable for the noise filtering circuit described above, and the method includes steps S91 to S97.
In step S91, after the power-on reset, the noise filtering circuit enters a training mode.
In step S92, the cutoff frequency of the noise filter is coarsely adjusted.
In step S93, the cutoff frequency of the noise filter and the bandwidth of the analog front end are fine-tuned.
In step S94, the amplitude of the amplified signal output by the analog front end is adjusted.
In step S95, the amplified signal is locked, and a clock output signal and a data output signal are output.
And step S96, processing the clock output signal and the data output signal to obtain error rate information.
And step S97, when the error rate information meets the requirement of a preset parameter, transmitting the clock output signal and the data output signal to a display device connected with the noise filtering circuit.
In some embodiments, the noise filtering method further comprises: and when the error rate information does not meet the requirement of preset parameters, re-fine-adjusting the cut-off frequency of the noise filter and the bandwidth of the analog front end according to the error rate information.
In some embodiments, the noise filtering method further comprises: and when the amplified signal is unlocked, the noise filtering circuit reenters the training mode.
The timing controller TCON sends a command packet to coarsely adjust the cutoff frequency of the noise filter during the training mode. And then, finely adjusting coefficients of the noise filter and the analog front end by using the error rate information, and after finishing the adjustment of the cut-off frequency of the passive filter and the analog front end, performing self-adaptive adjustment on the output amplitude of the analog front end. If the error rate information does not meet the preset parameter requirement, fine tuning and output amplitude control are executed again. If the amplified signal is unlocked, namely the clock data recovery circuit CDR is unlocked, the training mode is re-entered, and the clock data recovery circuit CDR is started again after the CDR is re-locked. In this case, the loss of CDR lock due to the sensitivity drop of AFE due to the variation of supply voltage and temperature can be solved by recalibration.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
The noise filtering circuit and the noise filtering method provided by the embodiment of the present invention are described in detail above, and a specific example is applied in the present disclosure to explain the principle and the embodiment of the present invention, and the description of the above embodiment is only used to help understanding the technical solution and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A noise filtering circuit, comprising:
the noise filter is used for receiving an input signal and outputting a filtering signal according to the cut-off frequency of the noise filter;
the analog front end is connected with the noise filter and used for amplifying the filtering signal to obtain an amplified signal;
the clock data recovery circuit is connected with the analog front end and used for locking the amplified signal and outputting a clock output signal and a data output signal;
the error code checker is connected with the noise filter, the analog front end and the clock data recovery circuit respectively, and is used for processing the received clock output signal and the data output signal to obtain error code rate information, sending a first control signal according to the error code rate information to fine-tune a cut-off frequency of the noise filter, and sending a second control signal according to the error code rate information to fine-tune a bandwidth of the analog front end.
2. The noise filtering circuit of claim 1, wherein the noise filter is further configured to receive an adjustment control signal to coarsely adjust a cutoff frequency of the noise filter.
3. The noise filtering circuit of claim 1, wherein the noise filter is a passive filter.
4. The noise filtering circuit of claim 3, wherein the passive filter comprises:
a first resistor having one end connected to a first input signal of the input signals and the other end connected to a first node;
a second resistor, one end of which is connected to a second input signal of the input signals, and the other end of which is connected to a second node;
one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to a third node;
one end of the second capacitor is connected to the second node, and the other end of the second capacitor is connected to a third node;
wherein the first node is connected to a first filtered signal of the filtered signals and the second node is connected to a second filtered signal of the filtered signals.
5. The noise filtering circuit of claim 1, wherein the analog front end comprises:
a plurality of cascaded amplifiers;
and the amplitude calibrator is connected with the plurality of cascaded amplifiers respectively and is used for adjusting the amplitude of the amplified signal output by the analog front end.
6. The noise filtering circuit of claim 5, wherein the amplifier comprises:
one end of the third resistor is connected to a power supply signal, and the other end of the third resistor is connected to a fourth node;
one end of the fourth resistor is connected to a power supply signal, and the other end of the fourth resistor is connected to a fifth node;
one end of the third capacitor is connected to a power supply signal, and the other end of the third capacitor is connected to a fourth node;
one end of the third capacitor is connected to a power supply signal, and the other end of the fourth capacitor is connected to a fifth node;
a first transistor, a drain of which is connected to a fourth node, a gate of which is connected to a first filtered signal of the filtered signals, and a source of which is connected to a sixth node;
a second transistor, a drain of which is connected to a fifth node, a gate of which is connected to a second filtered signal of the filtered signals, and a source of which is connected to a sixth node;
and one end of the current source is connected to the sixth node, and the other end of the current source is grounded.
7. The noise filtering circuit of claim 5, wherein the amplitude calibrator comprises:
a first comparator, configured to receive a positive reference signal and a negative reference signal, and a positive first amplified signal and a negative second amplified signal in the amplified signals, to obtain a first comparison signal;
the second comparator is used for receiving the positive reference signal, the negative first amplified signal and the positive second amplified signal in the amplified signals to obtain a second comparison signal;
the OR gate is used for carrying out OR operation on the first comparison signal and the second comparison signal to obtain a target signal;
the deburring device is used for removing burrs of the target signal;
and the logic output device is connected with the deburring device and is used for adjusting the amplitude calibration signal.
8. A noise filtering method applied to the noise filtering circuit according to any one of claims 1 to 7, the method comprising:
after power-on reset, the noise filtering circuit enters a training mode;
coarse tuning the cut-off frequency of the noise filter;
adjusting the amplitude of an amplified signal output by the analog front end;
locking the amplified signal and outputting a clock output signal and a data output signal;
processing the clock output signal and the data output signal to obtain error rate information;
according to the error rate information, finely adjusting the cut-off frequency of a noise filter and the bandwidth of an analog front end;
and when the error rate information meets the requirement of a preset parameter, transmitting the clock output signal and the data output signal to display equipment connected with the noise filtering circuit.
9. The noise filtering method according to claim 8, further comprising:
and when the error rate information does not meet the requirement of preset parameters, re-fine-adjusting the cut-off frequency of the noise filter and the bandwidth of the analog front end according to the error rate information.
10. The noise filtering method according to claim 8, further comprising:
and when the amplified signal is unlocked, the noise filtering circuit reenters the training mode.
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| CN202011530970.4A CN112713906B (en) | 2020-12-22 | 2020-12-22 | Noise filtering circuit and noise filtering method |
| PCT/CN2021/137443 WO2022135208A1 (en) | 2020-12-22 | 2021-12-13 | Noise filtering circuit and noise filtering method |
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| CN117975844A (en) * | 2022-10-25 | 2024-05-03 | 摩星半导体(广东)有限公司 | Driving circuit and display device |
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| FR2770351A1 (en) * | 1997-10-28 | 1999-04-30 | Philips Electronics Nv | HIGH GAIN AMPLIFIER HAVING LIMITED OUTPUT DYNAMIC |
| US20040218919A1 (en) * | 2003-04-30 | 2004-11-04 | Lucent Technologies Inc. | Method and apparatus for Q-factor monitoring using forward error correction coding |
| CN101355388B (en) * | 2007-07-25 | 2012-07-04 | 华为技术有限公司 | Receiving apparatus and method |
| KR100889733B1 (en) * | 2007-08-20 | 2009-03-24 | 한국전자통신연구원 | Receiver and receiving method for human body communication using multiple receivers |
| CN102480446B (en) * | 2010-11-29 | 2014-08-20 | 瑞昱半导体股份有限公司 | Receiver equalizer correcting device and method |
| US9184957B2 (en) * | 2012-12-27 | 2015-11-10 | Intel Corporation | High speed receivers circuits and methods |
| US9001943B2 (en) * | 2013-03-14 | 2015-04-07 | Altera Corporation | Digital equalizer adaptation using on-die instrument |
| US9881579B2 (en) * | 2013-03-26 | 2018-01-30 | Silicon Works Co., Ltd. | Low noise sensitivity source driver for display apparatus |
| CN103973235B (en) * | 2014-04-10 | 2016-08-17 | 嘉兴禾润电子科技有限公司 | Limiting amplifier |
| CN207399155U (en) * | 2017-11-03 | 2018-05-22 | 国网江苏省电力公司电力科学研究院 | Signal filtering process Compare System based on analog-digital converter |
| KR102482009B1 (en) * | 2018-04-24 | 2022-12-28 | 삼성디스플레이 주식회사 | Source drivier having receving circuit and display device having them |
| CN112713906B (en) * | 2020-12-22 | 2022-07-22 | 北京奕斯伟计算技术有限公司 | Noise filtering circuit and noise filtering method |
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