CN112713089A

CN112713089A - Method for manufacturing semiconductor device

Info

Publication number: CN112713089A
Application number: CN202011157360.4A
Authority: CN
Inventors: M·阿加姆; T·C·H·姚
Original assignee: Semiconductor Components Industries LLC
Current assignee: Semiconductor Components Industries LLC
Priority date: 2019-10-24
Filing date: 2020-10-26
Publication date: 2021-04-27

Abstract

The present invention relates to a method of manufacturing a semiconductor device. The fabrication process utilizes process steps used during CMOS formation to form one or more additional types of devices on the same substrate used for the CMOS formation, and at least partially in parallel with the CMOS formation process. A first layer of implant wells may be formed at a first depth in the substrate using a first mask and then a second layer of implant wells may be formed at a second, shallower depth using a second mask. CMOS devices that are part of the CMOS platform may be formed using some of the wells, while peripheral devices may be formed using the remaining wells.

Description

Method for manufacturing semiconductor device

Technical Field

This specification relates to semiconductor manufacturing technology, and more particularly to methods of fabricating semiconductor devices.

Background

Complementary Metal Oxide Semiconductor (CMOS) devices are widely used in the construction of Integrated Circuit (IC) microchips. In many cases, it is desirable to include other types of transistor-based devices on a CMO-based microchip. For example, such an approach may enable mixed voltage performance, device miniaturization, and other advantages, as well as optimization of the overall microchip for a particular application (e.g., low noise application). However, the associated manufacturing processes are typically inefficient and expensive.

Disclosure of Invention

According to one general aspect, a method of fabricating a semiconductor device includes: performing a first implant into the substrate at a first depth using a first mask having at least a first opening defining a first well and a second opening defining a second well; performing a second implant into the substrate at a second depth using a second mask, the second mask having at least a third opening defining a third well and a fourth opening defining a fourth well, and the second depth being closer to the implanted surface of the substrate than the first depth; the CMOS device is formed using at least the first and third wells, and the peripheral device is formed using at least the second and fourth wells.

According to another general aspect, a method of fabricating a semiconductor device includes: forming a CMOS device of a CMOS platform on a substrate, the CMOS device being formed using at least a first deep well and at least a first shallow well, the first deep well being implanted using a first mask and the first shallow well being implanted using a second mask; and forming at least one peripheral device on the substrate using at least a second deep well and at least a second shallow well, the second deep well being implanted using the first mask and the second shallow well being implanted using the second mask.

According to another general aspect, a method of fabricating a semiconductor device includes: forming a CMOS device of a CMOS platform on a substrate, the CMOS device being formed using at least a first deep well and at least a first shallow well, the first deep well being implanted using a first mask and the first shallow well being implanted using a second mask; and forming at least one double-diffused metal oxide transistor (DMOS) in the substrate, the DMOS transistor being formed using at least a second deep well and at least a second shallow well, the second deep well being implanted using the first mask and the second shallow well being implanted using the second mask.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

Drawings

Fig. 1 is a schematic diagram illustrating a split well implant process for CMOS and peripheral devices.

Fig. 2 is a flow diagram illustrating exemplary operations of the example of fig. 1.

Figure 3 shows an example of a cross-section of a CMOS device that may be formed using the techniques of figures 1 and 2.

Fig. 4 shows a cross-section of an exemplary isolation scheme for a CMOS device that can be implemented using the techniques of fig. 1 and 2.

Fig. 5 shows a first example of a peripheral device (vertical DMOS) formed using the techniques of fig. 1 and 2.

Fig. 6 shows an exemplary top view of the vertical DMOS of fig. 5.

Fig. 7 is a cross-sectional view showing a first operation for forming the vertical DMOS of fig. 5 and 6.

Fig. 8 is a cross-sectional view showing a second operation for forming the vertical DMOS of fig. 5 and 6.

Fig. 9 is a cross-sectional view showing a third operation for forming the vertical DMOS of fig. 5 and 6.

Fig. 10 is a cross-sectional view showing a fourth operation for forming the vertical DMOS of fig. 5 and 6.

Fig. 11 is a cross-sectional view showing a fifth operation for forming the vertical DMOS of fig. 5 and 6.

Fig. 12 is a cross-sectional view showing a sixth operation for forming the vertical DMOS of fig. 5 and 6.

Fig. 13 is a cross-sectional view showing a seventh operation for forming the vertical DMOS of fig. 5 and 6.

Fig. 14 is a flowchart illustrating exemplary operations of fig. 7 to 13 in constructing the vertical DMOS of fig. 5 and 6.

Fig. 15 is an exemplary simulated cross-section of the vertical DMOS of fig. 5 and 6.

Fig. 16 is an exemplary circuit using the vertical DMOS of fig. 5 and 6 with CMOS transistors.

Fig. 17 is a cross-sectional view showing a first operation for forming a lateral DMOS.

Fig. 18 is a cross-sectional view showing a second operation for forming a lateral DMOS.

Fig. 19 is a cross-sectional view showing a third operation for forming the lateral DMOS.

Fig. 20 is a cross-sectional view showing a fourth operation for forming a lateral DMOS.

Fig. 21 is a cross-sectional view showing a fifth operation for forming a lateral DMOS.

Fig. 22 is a flowchart illustrating the exemplary operations of fig. 17-21 for forming a lateral DMOS.

Fig. 23 shows a simulated cross-sectional view of the lateral DMOS of fig. 17-22.

FIG. 24 shows a cross-sectional view of a first operation for forming a Low Voltage (LV) floating body NMOS.

FIG. 25 illustrates a cross-sectional view of a second operation for forming the LV floating body NMOS.

FIG. 26 illustrates a cross-sectional view of a third operation for forming the LV floating body NMOS.

FIG. 27 shows a cross-sectional view of a fourth operation for forming the LV floating body NMOS.

FIG. 28 shows a cross-sectional view of a fifth operation for forming the LV floating body NMOS.

FIG. 29 is a flowchart illustrating exemplary operations for forming the LV floating body NMOS of FIGS. 24-28.

Fig. 30 is a first exemplary circuit constructed using the LV floating body NMOS of fig. 24-29.

Fig. 31 is a second exemplary circuit constructed using the LV floating body NMOS of fig. 24-29.

Fig. 32 is a simulated cross-section of the LV floating body NMOS of fig. 24-29, and associated current-voltage plots.

Fig. 33 is a cross section of a first operation for forming a Junction Field Effect Transistor (JFET).

Figure 34 is a cross section of a second operation for forming a JFET.

Figure 35 is a cross section of a third operation for forming a JFET.

Figure 36 is a cross section of a fourth operation for forming a JFET.

Fig. 37 is a flowchart illustrating exemplary operations for forming the JFET of fig. 33-36.

Fig. 38 is a simulated first cross section of the JFET of fig. 33-37.

Fig. 39 is a simulated second cross section of the JFET of fig. 33-37.

Fig. 40 is a simulated third cross section of the JFET of fig. 33-37.

Fig. 41 is a simulated fourth cross section of the JFET of fig. 33-37.

Figure 42 shows a cross section of a second exemplary embodiment of a JFET.

Figure 43 shows a cross section of a third exemplary embodiment of a JFET.

Fig. 44 shows a cross section of a first exemplary operation for forming a (bipolar junction transistor) BJT.

Fig. 45 shows a cross-section of a second exemplary operation for forming a BJT.

Fig. 46 shows a cross-section of a third exemplary operation for forming a BJT.

Fig. 47 illustrates a cross-section of a fourth exemplary operation for forming a BJT.

Fig. 48 is a flowchart illustrating exemplary operations for forming the BJT of fig. 44-47.

Fig. 49 is a simulated first cross-section of the BJT of fig. 44-48.

Fig. 50 is a simulated second cross-section of the BJT of fig. 44-48.

Fig. 51 is a simulated third cross-section of the BJT of fig. 44-48.

Fig. 52 is a first exemplary current-voltage graph for the BJT of fig. 44-48.

Fig. 53 is a second exemplary current-voltage graph for the BJT of fig. 44-48.

Fig. 54 shows a cross-section of a second exemplary embodiment of a BJT.

Fig. 55 shows a cross-section of a third exemplary embodiment of a BJT.

Detailed Description

As described in detail below, a fabrication process may be implemented that utilizes process steps used during CMOS formation to form one or more additional types of devices on the same substrate used for CMOS formation, and at least partially in parallel with the CMOS formation process. For example, a first layer of an implant well (e.g., a first Nwell) may be formed at a first depth in the substrate using a first mask, and then a second layer of the implant well may be formed at a second, shallower depth using a second mask.

In this way, a desired combination of implant wells at different depths may be formed. For example, the shallow implant well may be stacked adjacent to the deep implant well, or the shallow implant well and the deep implant well may be partially or completely offset from each other within the substrate.

CMOS devices that are part of the CMOS platform may be formed using some of the wells, while peripheral devices may be formed using the remaining wells. Thus, the use of separate or additional process modules to form all or part of the peripheral devices may be minimized or avoided.

In some embodiments, the first and second masks may have different levels of implantation accuracy, such that, for example, relatively smaller or narrower shallow wells may be formed as needed for the formation of peripheral devices, and/or CMOS and peripheral devices may be formed closer to each other, while still maintaining a desired level of device isolation. Thus, improvements in device performance and device density may be obtained and process efficiency may be increased.

In various embodiments, more than two (i.e., three or more) different implant well masks may be used to form an implant well shared by CMOS and peripheral device processing. Furthermore, the CMOS process steps used to form the main CMOS devices of the CMOS platform may be utilized (e.g., shared with peripheral devices) before, during, or after the use of any such number of implant well masks.

Fig. 1 is a schematic diagram illustrating a split well implant process for CMOS and peripheral devices. In the example of fig. 1, the substrate 102 is subjected to multiple rounds of dopant implantation (represented by implant 104). A first mask 106 is used at a first time to form an implant well at a first depth and a second mask 108 is used at a second time to form an implant well at a second depth closer to the surface of the substrate 102. In an exemplary embodiment, the first mask 106 may be used to form relatively deep wells and may be referred to as a deep mask, while the second mask 108 may be used to form relatively shallow wells and may be referred to as a shallow mask.

In more detail, the first mask 106 includes an opening 110 for defining a deep well 112, an opening 114 for defining a deep well 116, an opening 118 for defining a deep well 120, and an opening 122 for defining a deep well 124. Similarly, the second mask 108 includes an opening 126 for defining a shallow well 128, an opening 130 for defining a shallow well 132, an opening 134 for defining a shallow well 136, an opening 138 for defining a shallow well 140, an opening 142 for defining a shallow well 144, and an opening 146 for defining a shallow well 148. In some implementations, such as in the examples of fig. 5-16 below, the

shallow wells

128, 136 may show a cross-section of a diffusion ring.

In an exemplary embodiment, the substrate 102 may be used primarily to construct a CMOS platform that includes a number of NPN/PNP transistors and related devices and structures, including, for example, isolation structures and metal contacts. In a conventional process, the construction of such a CMOS platform may be done in two or more separate process modules, and the remaining areas of the substrate 102 are then used to construct additional peripheral devices. For example, a CMOs platform may be constructed in a first process module using a first mask to implant all CMO related wells, while peripheral devices may be subsequently constructed in a second process module using at least a second mask.

However, in the example of fig. 1, using the

masks

106, 108 to divide the well formation process into separate masking steps, all desired wells for both CMOS and peripheral devices may be formed within a single process block. As shown and described with respect to fig. 1, the desired wells may be formed with a high degree of flexibility and efficiency such that many different types of peripheral devices may be formed, examples of which are described and illustrated herein.

Furthermore, it is possible to form such circuits in an efficient, cost-effective manner. For example, the process flow of an existing CMOS platform may be enhanced by simply changing the characteristics (e.g., opening, thickness) of the

masks

106, 108 to form any of the peripheral devices described herein, as well as many other devices.

Other advantages are also obtained. For example, the energy of the implants in the implants 104 used to form the various

deep wells

112, 116, 120, 124 may be higher than the energy of the implants used to form the various

shallow wells

128, 132, 136, 140, 144, 148. Thus, the second shallow mask 108 may be thinner and therefore more precise than the first deep mask 106 due to being used for a relatively lower energy implant, such that shallow wells (e.g., shallow well 132) may be formed with greater precision.

In other examples, it may be possible that portions of the substrate 102 may be used to provide isolation between two or more of the various wells. For example, a region 156 of the substrate 102 may provide isolation between the

shallow wells

140, 144, while a region 158 may provide isolation between the

deep wells

116, 120. As shown, region 156 is smaller than region 158, allowing

shallow wells

140, 144 to be formed closer to each other than

deep wells

116, 120.

This may be advantageous, for example, when less isolation is required at different depths of the substrate 102 (e.g., due to the depth-related magnitude of the electric field). In such cases, the multi-mask approach of fig. 1 enables optimization and miniaturization of isolation widths, and thus smaller device sizes and greater device densities on the substrate 102.

In addition to using the

masks

106, 108 to form the desired combination of deep and shallow wells, in-module, shared, and separate processes 160 may also be performed to define separate CMOS and peripheral devices and combinations thereof. For example, in the simplified example of fig. 1, the region 150 including the

shallow wells

140, 144 and the

deep wells

116, 120 may be used to form a CMOS device, such as a PNP or NPN transistor of a CMOS platform (as shown in more detailed examples with respect to fig. 3 and 4).

Meanwhile, the region 152 including the deep well 112 and the

shallow wells

128, 132, 136 may be used to form peripheral devices, such as vertical DMOS (double diffused MOS) transistors, which may be used, for example, for non-volatile memory circuits (as shown in more detailed examples with respect to fig. 5-16). The deep well 124 and the shallow well 148 in the region 154 may also be used for one or more additional peripheral devices. In addition, many other variations and combinations of shallow and deep wells may be used, examples of which are shown and described below with respect to fig. 17-55.

As mentioned above and described in detail below, in-module processing 160 refers to and includes any potential processing steps that may be performed within a process module in which the deep mask 106 and the shallow mask 108 are used. Such in-module processing may be referred to as shared when referring to process steps implemented together for both CMOS devices and peripheral devices formed in the substrate 102.

For example, both CMOS devices in region 150 and one or more peripheral devices in region 152 may require the implantation of an additional well having a doping type (e.g., p-type) opposite to that of the various

shallow wells

128, 132, 136, 140, 144 (e.g., n-type). In such cases, the in-module processing 160 may represent an additional mask (not separately shown in fig. 1) for implanting p-type dopants in desired ones of the two

regions

150, 152.

Such shared processing may include any processing steps that may be required by a group of CMOS and peripheral devices, including different types of peripheral devices. Such processing steps may include, for example, silicide or other deposition, etching or other removal processes, annealing processes, or contact formation. Shared processing may also refer to processing steps that facilitate the formation of CMOS and peripheral devices, such as steps for forming isolation regions or structures.

Various types of peripheral devices that may be included may require many different processing steps, some of which may not directly overlap with the formation of corresponding CMOS devices or other peripheral devices. In such cases, for example, the CMOS devices may be masked and separate processing may be performed for the peripheral devices. However, because of the use of the techniques described herein, such separate processing may be performed without the need to move the substrate 102 to a separate processing module.

In this specification, the time of use of the deep mask 106 may be referred to by symbol and terminology as T_DAnd the time of using the shallow mask 108 may be referred to as T_S. The processing step within the module 160 may be referred to as T_IIs performed for one or more time periods. At time T_IThe processing step may be performed at time T_DAnd T_SBefore, interspersed between, or after. For example, the isolation structure may be at an initial T_IIs formed in the substrate 102, followed by time T_DThe deep mask 106 is used, followed by at time T_SThe shallow mask 108 is used, followed by a subsequent T during which a shared process is performed for the CMOS/peripheral devices_IAnd then a final T_IAt the final T_IAny remaining separate processing is performed for the CMOS devices and the peripheral devices.

In this specification, the substrate 102 is commonly referred to as p-type, so that the various wells are referred to as Nwell. However, it should be understood that the reverse dopant type may also be used. Additionally, as used herein, the term peripheral device refers to a device that is peripheral in number and/or function to the main circuit of the CMOS platform and not necessarily to the physical periphery of the substrate 102.

Fig. 2 is a flow diagram illustrating exemplary operations of the example of fig. 1. In the example of fig. 2, a first implant into the substrate may be performed at a first depth using a first mask having at least a first opening defining a first well and a second opening defining a second well (202). For example, referring to fig. 1, a first mask 106 may be used to implant at least two of the example

deep wells

112, 116, 120, 124. In various embodiments, the implantation may be performed in any desired manner. For example, multiple diffusions may be performed to establish a desired doping gradient within the

deep wells

112, 116, 120, 124.

A second implant into the substrate may be performed at a second depth using a second mask having at least a third opening defining a third well and a fourth opening defining a fourth well, wherein the second depth is closer to an implant surface (204) of the substrate than the first depth. For example, referring to fig. 1, the second mask 108 may be used to implant at least two of the example

shallow wells

128, 132, 136, 140, 144, 148, which may be formed closer to the surface of the substrate 102 where the implantation is performed, as shown and described.

CMOS devices (206) may be formed using at least the first well and the third well. For example, a CMOS device may be formed using deep well 116 and shallow well 140 or using deep well 120 and shallow well 144.

Peripheral devices (208) may be formed using at least the second well and the fourth well. For example, the peripheral devices may be formed using deep well 112 and one or more of

shallow wells

128, 132, 136.

In fig. 2, shared and separate processes (210) are shown to include both CMOS processing 206 and peripheral device processing 208. As described above with respect to fig. 1, the shared processing may include in-module processing steps, where one or more steps of CMOS processing 206 and peripheral device processing 208 are performed in parallel. The separate processing may include, for example, in-module processing steps in which the steps of CMOS processing 206 (including the sharing step) are completed, followed by the remaining steps of peripheral device processing 208 completed in series therewith. In some embodiments, such additional separate steps for finalizing the peripheral device may not be necessary. As described, the ability to perform such shared and individual processing within the process modules enables higher process efficiency and reduced processing costs.

Fig. 3 and 4, hereinafter, illustrate exemplary embodiments and aspects of a CMOS device formed using the techniques of fig. 1 and 2. Fig. 5-16 illustrate exemplary embodiments and aspects of a first exemplary peripheral device (vertical DMOS) using the techniques of fig. 1 and 2. Fig. 17-23 illustrate exemplary embodiments and aspects of a second exemplary peripheral device (lateral DMOS) using the techniques of fig. 1 and 2. Fig. 24-32 illustrate exemplary embodiments and aspects of a third exemplary peripheral device (floating body Low Voltage (LV) NMOS) using the techniques of fig. 1-2. Fig. 33-43 illustrate exemplary embodiments and aspects of a fourth exemplary peripheral device (isolated Junction Field Effect Transistor (JFET)) using the techniques of fig. 1 and 2. Fig. 44-55 illustrate exemplary embodiments and aspects of a fifth exemplary peripheral device (bipolar junction transistor (BJT)) using the techniques of fig. 1 and 2.

In the following, it is assumed that the functions, operating characteristics of the CMOS device and various peripheral devices themselves are known. Furthermore, the device is provided as an example and other CMOS and peripheral devices may also be used. Accordingly, the functional and operational characteristics of the various CMOS and peripheral devices are not described in detail herein, except as may be necessary or helpful in understanding the exemplary benefits of using the techniques of fig. 1 and 2 to form each peripheral device or similar peripheral device.

As just mentioned, fig. 3 shows an example of a cross-section of a CMOS device that can be formed using the techniques of fig. 1 and 2. In the example of fig. 3, the PMOS device is shown as being formed using a p-doped substrate 302 (e.g., a p-type epitaxial layer), which may correspond to the substrate 102 of fig. 1. A. the

An n-type deep well NWdeep 304 is shown formed within the substrate 302, and an n-type shallow well NWshallow 306 is formed between the well NWdeep 304 and the surface of the PMOS device shown.

As can be appreciated from the description of fig. 1 and 2, the deep well NWdeep 304 may represent a first well formed using a first mask, such as mask 106 of fig. 1. For example, deep well NWDeep 304 may be formed similarly to deep well 116 or deep well 120 of fig. 1.

Additionally, a second mask (such as mask 108 of fig. 1) may be used to form the shallow well nwshow 306. For example, the shallow well nwshow 306 may be formed similarly to the shallow well 140 or the shallow well 144 of fig. 1.

Although not shown in the example of fig. 3, it can be appreciated from the above description of fig. 1 and 2 that at least one peripheral device can also be formed in the substrate 302. For example, another deep well formed using a first mask and another shallow well formed using a second mask may be used to form one or more of the peripheral devices mentioned above and described and illustrated below with respect to fig. 5-55, or other peripheral devices.

The PMOS device of fig. 3 may be isolated from such peripheral devices and other CMOS devices using Shallow Trench Isolation (STI)

structures

308, 310. The remainder of fig. 3 shows an exemplary PMOS structure, whose function is not described herein, including a source contact 312, an n-type source/drain (SD) region 314, a pSD region 316, and a p-type lightly doped drain (pLDD) region 318. A drain contact 320 is shown connected to the pSD region 322 and the pLDD region 324. The p-type polysilicon gate layer 324 is shown connected to a gate contact 326.

In addition, as can be appreciated from the above description of fig. 1 and 2, many of the processing steps used to construct the PMOS device of fig. 3 may be utilized or shared in the construction of the peripheral devices. For example, the

STI structures

308, 310 may isolate the PMOS device of fig. 3 from peripheral devices. In addition, layers of the PMOS device of fig. 3, such as polysilicon gate layer 324, may be formed simultaneously with polysilicon gates of one or more peripheral devices. Implantation of various doped regions, such as nSD region 314 or pSD region 316, may be performed in tandem with corresponding n-type or p-type implantation in the peripheral devices. Similar comments apply to the formation of the various contacts (source contact 312, drain contact 320, and gate contact 326).

Fig. 4 shows a cross-section of an exemplary isolation scheme for a CMOS device that can be implemented using the techniques of fig. 1 and 2. In particular, an isolation scheme is shown instead of the

STI structures

308, 310 of fig. 3, wherein the substrate 402 has deep wells NWdeep 404 and NWdeep 406 and shallow wells nwshow 408 and nwshow 410 formed therein, and wherein isolation is provided by a p-well 412 formed in the substrate 402. That is, fig. 4 provides a more detailed example of the isolation scheme mentioned above with respect to fig. 1 with respect to the isolation region 156 formed between the shallow well 140 and the shallow well 144.

As mentioned above, the techniques of fig. 1 and 2 enable a reduction in the size of the p-well 412 while still maintaining a desired and necessary level of isolation between the shallow wells 408 and 410 (where, for example, CMOS devices, such as the PMOS device of fig. 3, may be formed). In particular, the use of

multiple masks

106, 108 of fig. 1 enables the split well configuration described herein, wherein the width of the deep well may be different from the width of the narrow aperture. Furthermore, the finer degree of control provided by the second shallow mask 108 of fig. 1 (as compared to the first deep mask 106) enables the

shallow wells

408, 410 to be placed close to each other.

Thus, for example, for CMOS devices for which the operating electric field has a depth dependence, different levels of isolation may be achieved at different depths to avoid undesirable effects of such electric fields. In conventional approaches, it may be necessary to maintain a minimum separation distance determined by the maximum value of the electric field, even when the electric field is weak at a given depth. However, in fig. 4, the isolation distances may be customized at different depths for the corresponding values of the electric field at those depths.

Fig. 5 shows a first example of a peripheral device (vertical DMOS) formed using the techniques of fig. 1 and 2. Fig. 6 shows an exemplary top view of the vertical DMOS of fig. 5.

In the example of fig. 5, a p-type substrate 502 (e.g., an epitaxial layer) has a deep N-well (NWdeep)504 formed therein, similar to deep well 112 of fig. 1.

Cross-sectional areas

506, 510 of the diffusion ring are shown formed using a shallow N-well, along with a central shallow Nwell 508, such that the

areas

506, 508, 510 are formed between the deep N-well 504 and the surface of the substrate 502, and correspond to the exemplary embodiment of the

shallow wells

128, 132, 136 of fig. 1. Thus, NWdeep 504 may provide a drive region or nDrive 504 for the drain of the vertical CMOS and may be referred to as this, while the central shallow Nwell 508 provides a drift region and may be referred to as nddrift. Meanwhile, the outer shallow N-

wells

506, 510 provide a plug or sinker connection between the drain contact 528 and the nDrive region 504, as described in more detail below, and may be referred to as npugs or

nSinker wells

506, 510.

The remainder of fig. 5 shows additional elements and aspects of the vertical DMOS. For example, a p-well 512 is shown, wherein a p-type region 514 is formed adjacent (surrounding) the shallow N-well 508. STI 516 provides isolation between p-well 512 and

shallow Nwell

506, 510.

The source contact 520 is connected to a p-source/drain (pSD) region 522 adjacent nSD region 524 through silicide 525. nLDD region 526 is formed adjacent to nSD region 524. nSD regions 530 are formed in the nwshow/nplus well 506 and provide nplus tap connections to the drain contacts 528 via silicide 531.

The gate contact 532 is connected to the polysilicon gate 534 by a silicide 540, with a gate oxide 536 formed between the polysilicon gate 534 and the surface of the substrate 502. Sidewall spacers 538 surround the polysilicon gate 534 and are formed over the nLDD region 526.

Each of source contact 520, gate contact 532, and drain contact 528 are further shown in the top view of fig. 6. Fig. 6 illustrates the ring nature of diffusion ring 506/510, as well as the active region of source contact 520 encapsulated by diffusion ring 506/510.

As can be observed, the vertical DMOS of fig. 5 and 6 may be implemented with all

terminals

520, 528, 532 on the topside surface of the silicon substrate 502. The device is a DMOS device due to the nature of the high voltage double diffused drain 504/506/508/510/530 and is referred to as vertical due to the vertical drift that exists in the double diffused drain. In various embodiments, the devices of fig. 5 and 6 may have three or four terminals, e.g., drain, gate, source, and body, where the source and body may be electrically tied to make a single terminal, which may be referred to individually as the source. The body terminal is not shown in the examples of fig. 5, 6, but is shown in the example of fig. 15. The device may be n-type (nVDMOS) or p-type (pVDMOS).

In an exemplary embodiment, the devices of fig. 5 and 6 can be implemented to provide medium or high voltage vertical DMOS integrated into a CMOS platform without the need for any additional process modules other than those required by the CMOS platform. For example, the described vertical DMOS may be used to provide embedded non-volatile memory devices using 15V-20V operating voltages. Using the techniques described herein, such memory modules may be included without increasing the manufacturing complexity and cost of the associated products. The vertical DMOS of fig. 5 and 6 may also be used for various other applications requiring medium or high voltage operating ranges.

Fig. 7-13 show an exemplary process flow for forming the vertical DMOS of fig. 5 and 6, corresponding to the flow chart of fig. 14. In particular, fig. 7-13 show half-pitch cross-sections corresponding to the cross-section of fig. 6. The description of fig. 7-13 is provided below with reference to corresponding steps of the flowchart of fig. 14.

In fig. 7, two

active regions

706, 708 are formed in a substrate 502 and using a sacrificial oxide growth 704, separated by a field oxide isolation 516, as described in more detail below (1402). As also described, active region 706 may be used to form the drain of the vertical DMOS and active region 708 may be used to form the source of the vertical DMOS.

In fig. 8, an n-type doped buried diffusion layer 504 (referred to herein as NWdeep) may be formed under the two

active regions

706, 708 in order to separate 1404 the substrate surface, including the

active regions

706, 708 and the isolation structure 516, from the bottom of the substrate 502. For example, the NWdeep mask 106 of fig. 1 may be used to form the NWdeep layer 504. As can also be appreciated from fig. 1-4, NWdeep well 504 may be formed (e.g., using the deepest implant of a CMOS nWell implant chain) during the same dedicated masking step as one or more deep n-wells of a CMOS structure formed in substrate 502, such as well NWdeep 304 of fig. 3. As described above, NWdeep well 504 may function as and be referred to as the nDrive well of the formed vertical DMOS.

In fig. 9, shallow diffusion rings (nwshort) 506, 510 may be formed in the drain active region 708, which bond NWdeep 504 to the surface 1406 of the substrate 502. As mentioned, the nwshow ring 508 may be referred to as nPlug or nSinker. Also in fig. 9, nwshow well 508 is formed in source active region 706 and it bonds NWdeep, nDrive 504 to the surface of substrate 502 (1408), where nwshow well 508 may be referred to as ndriveft, as mentioned above.

The

wells

506, 508 may be formed by the shallowest implant of the CMOS nWell implant chain by one special masking step (e.g., using the shallow mask 108 of fig. 1). As described, the use of the shallow mask 108 of fig. 1 enables the shallow implant to be separated from the standard CMOS flow and enables the use of thinner photoresist masks and associated smaller critical dimensions. Thus, while shown as separate steps in fig. 14, it should be understood that

steps

1408, 1410 may be performed in parallel as part of the same dedicated masking step.

In fig. 10, Pwell 512 is formed, leaving a p-region 514(1410) surrounding nwshow (ndrift) well 508. More specifically, Pwell (also known as pBody) can be formed as an annular p-type diffusion inside the nplus ring 506 and around the nDrift well 508. Pwell 512(pBody) may be formed by the full or shallowest implant of the cmos Pwell injection chain. For example, if formed by part of a pWell implant chain, pWell 512 may be implanted from a dedicated mask (similar to

dedicated masks

106, 108 of fig. 1) and thus provide an example of the in-module processing 160 of fig. 1. In an exemplary embodiment, the pBody diffusion 512 reaches the substrate 502 surface and incompletely counter-dopes the buried nDrive 504.

A gate oxide layer 1002(1412) may be formed at the surface of the source active region 708. For example, the oxide layer 1002 may be formed separately after the oxide 704 is removed.

In fig. 11, a polysilicon layer 534 is formed to overlap a portion of nwshow/nDrift 508 and pWell 512, and a layer 1102(1414) is formed. As shown in fig. 12, layer 1102 may be a lightly doped n-type layer, a portion of which is used to form the nLDD 526.

Specifically, in fig. 12, dielectric spacer structures 538(1416) are formed on the sides of polysilicon layer 534. Body taps psds 522 and nSD 524 are then formed to also define nLDD 526, as mentioned above, along with drain regions nSD 530(1418) that define the nPlug taps. As shown in fig. 13, silicide layers 525, 531 may be formed on the surfaces of the drain/source regions not covered by the polysilicon layer 534, and

contacts

520, 528, 532 may be formed to make terminals of the device (1420).

In an exemplary embodiment, all of the processing steps of fig. 10-13, such as step 1410-1420, may be formed using shared processing steps utilized in standard CMOS flow. Specifically, the vertical DMOS of fig. 5-14 may be formed with HV drains using CMOS drain contacts 528, CMOS silicide 531, and CMOS nSD diffusion 530. Meanwhile,

nwshow wells

506, 510 provide nplus regions separately from NWdeep well 504 for providing nDrive regions, and nwshow well 508 provides ndriveft depleted by n-type polysilicon layer 534 and pWell 512.

In fig. 15, a cross-sectional simulation 1500 provides an example of the vertical DMOS of fig. 5 and 6 with corresponding reference numerals. The simulated view 1501 shows the corresponding electric field distribution, including the region 1502 that shows the complete depletion of the drift region 508.

Thus, CMOS Pwell 512 is shown vertically encapsulated by nDrive/NWdeep 504 and laterally encapsulated by nddrift/nwshow 508, the former of which isolates the source/body from the bulk of the substrate 502, and the latter of which provides the depletion drift region 1502 for the HV device, as just mentioned. In other words, the HV drain is obtained by the complete depletion of the vertical drift 1502.

In fig. 16, the vertical DMOS of fig. 5-15 is used to provide an exemplary circuit application, a HV driver 1602 for a non-volatile memory. In fig. 16, transistor 1604 may be implemented using the techniques described above to provide a high-side bootstrapped HV switch. Transistor 1604 may be implemented with a drain at Vpp (thereby providing a shared drain with a shared drain diffusion), and with a HV source with respect to the substrate.

Fig. 17-23 illustrate exemplary embodiments and aspects of a second exemplary peripheral device (lateral DMOS) using the techniques of fig. 1 and 2. Specifically, fig. 17-23 illustrate and describe the formation of a half-pitch cross-section of a lateral DMOS. The description of fig. 17-21 is provided below with reference to corresponding steps of the flowchart of fig. 22.

In fig. 17, two

active regions

1700, 1701 are formed in a substrate 1702 and using sacrificial oxide growth 1708, separated by field oxide isolation regions 1704, 1706 (2202). As described below, active region 1700 may be used to form the body and source of the lateral DMOS and active region 1701 may be used to form the drain of the lateral DMOS.

Also in fig. 17, an n-type doped buried diffusion layer 1710 (referred to herein as NWdeep) may be formed under both

active regions

1700, 1701 in order to separate the substrate surface (including the

active regions

1700, 1701 and the isolation structures 1704, 1706) from the bottom of the substrate 1702 (2204). For example, the NWdeep mask 106 of fig. 1 may be used to form the NWdeep layer 1710. As can also be appreciated from fig. 1-4, NWdeep well 1710 may be formed (e.g., using the deepest implant of a CMOS nWell implant chain) during the same dedicated masking step as one or more deep n-wells of a CMOS structure formed in substrate 1702, such as well NWdeep 304 of fig. 3. NWdeep well 1710 may be used as and referred to as a reduced surface field (RESURF) diffusion well for the lateral DMOS being formed.

In fig. 18, a shallow diffusion well (nwshort) 1802 may be formed in the source active area 1700, which bonds NWdeep 1710 to the surface 2206 of the substrate 1702. In fig. 19, a pDrift diffusion 1902 may be formed by a pWell diffusion process using a CMOS platform so as to overlap the drain active region 1701 and intersect the source active region 1700 (2208). For example, pDrift diffusion 1902 may be implanted from a dedicated mask (similar to

dedicated masks

106, 108 of fig. 1) if formed by a portion of the pWell implant chain of a CMOS platform. The nBody diffusion (nwsallow) 1802 may be formed as a donut shaped n-type diffusion around pDrift diffusion 1902.

Well 1802 can be formed by the shallowest implant of the CMOS nWell implant chain by one special masking step (e.g., using shallow mask 108 of fig. 1). As described, the use of the shallow mask 108 of fig. 1 enables the shallow implant to be separated from the standard CMOS flow and enables the use of thinner photoresist masks and associated smaller critical dimensions.

A gate oxide layer 1901(2210) may be formed. For example, the oxide layer 1901 may be formed separately after the oxide 1708 is removed. In fig. 20, a polysilicon layer 2002 (e.g., p-doped) may be formed to overlap portions of nBody1802, pDrift 1902, and field oxide isolation 1706, and a pLDD layer 2004(2212) may be formed.

In fig. 21, dielectric spacer structures 2114(2214) made of a suitable oxide or nitride are formed on the sides of the polysilicon layer 2002. Then, a pLDD diffusion 2101 may be defined under the spacer 2114, with a pSD source diffusion 2108 formed on the side of the pLDD 2101, nSD a body tap 2102 formed on the side of the pSD 2108, and another pSD diffusion 2124 formed in the pDrift diffusion 1902 for ptap contact.

Also as shown in fig. 21,

suicides

2106, 2112, and 2124 may be formed on the surface of the drain/source regions not covered by polysilicon layer 534, and

contacts

2104, 2110, 2118, and 2122 may be formed to make the terminals of the device (2218).

In an exemplary embodiment, all of the processing steps of fig. 19-21, such as steps 2208-2218, may be formed using the shared in-module processing step (e.g., mask) 160 utilized for standard CMOS flow. Specifically, the lateral DMOS of fig. 21 may be formed through the HV drains using CMOS drain contacts 2122, CMOS silicide 2124, and CMOS pSD diffusions 2120. Also, nwshow wells 1802 provide bulk diffusion, while NWdeep wells 1710 provide reduced surface field diffusion.

The lateral DMOS of fig. 17-23 may be used to provide medium or high voltage lateral DMOS integrated into a CMOS platform without adding process modules beyond conventional CMOS processing. The lateral DMOS of fig. 17-23 may be used for embedded non-volatile memories IP requiring, for example, 15v-20v operating voltage. Using the techniques described herein, such memory IP does not increase the manufacturing complexity or cost of the resulting product. The lateral DMOS may also be used for applications other than non-volatile memory applications.

In fig. 23, a cross-sectional simulation 2300 provides an example of the lateral DMOS of fig. 21 with corresponding labels. Simulated view 2301 shows a corresponding electric field profile, including region 2302 showing full depletion of drift region 1902.

Fig. 24-32 illustrate exemplary embodiments and aspects of a third exemplary peripheral device (floating body Low Voltage (LV) NMOS) formed using the techniques of fig. 1-2. The description of fig. 24-28 is provided below with reference to corresponding steps of the flowchart of fig. 29.

Hereinafter, the floating body LV NMOS, shown in cross-section, provides a low voltage n-type mosfet formed in pWell isolated from pEpi/pSubstrate, with five terminals: drain, gate, source, bulk and Isolation (ISO). The body terminal may be independent of pSubstrate/ground bias, the iso terminal may be biased at a higher voltage than both pSubstrate and the body, and the body terminal and the iso terminal may be tied together.

In fig. 24, a circular ring shaped active region 2406 may be formed to accommodate the above mentioned iso terminal (2902) of the floating body LV NMOS defined by field oxide isolation 2408 at the surface of the p-doped layer of the silicon substrate 2402. Transistor active regions 2404 may be formed within the holes of the circular ring-shaped Iso active region 2406 to accommodate the main transistor, and which are defined by field oxide isolation 2410 (2904).

An n-type doped buried diffusion (NWdeep)2412 may then be formed under the

active regions

2404, 2406 to separate the substrate surface and the active region/field isolation structures from the bottom of the substrate 2402 (2906). For example, the NWdeep mask 106 of fig. 1 may be used to form the NWdeep layer 2412. As can also be appreciated from fig. 1-4, NWdeep well 2412 may be formed during the same dedicated masking step (e.g., the deepest implant using a CMOS nWell implant chain) as one or more deep n-wells of a CMOS structure formed in substrate 2402, such as well NWdeep 304 of fig. 3.

In fig. 25, the shallowest implant of the CMOS nWell implant chain may be used to form a circular n-type lateral isolation diffusion 2502(2908) below the Iso active region 2406. Well 2502 may be formed by the shallowest implant of the CMOS nWell implant chain by one special masking step (e.g., using shallow mask 108 of fig. 1). As described, the use of the shallow mask 108 of fig. 1 enables the shallow implant to be separated from the standard CMOS flow and enables the use of thinner photoresist masks and associated smaller critical dimensions.

In fig. 26, CMOS pWell implantation can be used to form a p-type body diffusion 2602(2910) within the hole of a circular lateral diffusion (nwwindow) 2502. Then, as shown in fig. 27 and 28, an NMOS transistor may be formed within the p-type body 2602 using CMOS processing (2912).

Specifically, in fig. 27, and similar to the description of transistor formation provided above with respect to fig. 3, 10-13, and 19-21, a gate polysilicon layer 2702 can be formed, along with a source nLDD layer 2704 and a drain nLDD layer 2706.

In fig. 28, the gate structure 2802 is completed using a gate polysilicon layer 2702 and a silicide layer 2804 is disposed at the surface of the substrate 2402 not covered by or including the gate structure 2802 or

oxide isolation

2408, 2410. Source terminal 2806 is thus connected to nSD region 2708, while body terminal 2810 is similarly connected to pSD region 2812. The drain terminal 2814 is connected to nSD region 2816. Finally, Iso terminal 2818 connects to Iso nDS region 2820.

In an exemplary embodiment, all of the processing steps of fig. 24-28, such as steps 2908-2912, may be formed using the shared in-module processing steps (e.g., mask) 160 utilized for standard CMOS flow.

Fig. 30 is a first exemplary circuit constructed using the LV floating body NMOS of fig. 24-29. Fig. 30 shows a HV driver 3002 for a non-volatile memory, including an exemplary implementation 3004 of the LV floating body NMOS.

Fig. 31 is a second exemplary circuit constructed using the LV floating body NMOS of fig. 24-29. FIG. 31 shows a charge pump 3102, including an exemplary implementation 3104 of the LV floating body NMOS.

Fig. 32 is a cross section of a simulation 3202 of the LV floating body NMOS of fig. 24-29, and an associated current-voltage plot 3204. Simulated view 3202 shows the corresponding electric field distribution. As shown in fig. 32, the floating body NMOS device provides vertical isolation that allows high voltage p-body bias (shown by curve 3206) with respect to p-epi/p-substrate (shown by curve 3208). Low voltage operation is guaranteed when NWdeep 2412 does not interfere with the highest device voltage configuration (e.g., BVdss).

Fig. 33-43 illustrate exemplary embodiments and aspects of a fourth exemplary peripheral device (isolated Junction Field Effect Transistor (JFET)) using the techniques of fig. 1 and 2. The description of fig. 33-36 is provided below with reference to corresponding steps of the flowchart of fig. 37.

In fig. 33, active regions 3304(3702) defined by field oxide isolation 3306 are formed in a p-type substrate 3302. An n-type doped buried diffusion (NWdeep)3308 is then formed under the active region 3304 to separate the substrate surface and the active region/field isolation structure from the bottom of the substrate (3704). For example, the NWdeep mask 106 of fig. 1 may be used to form the NWdeep layer 3308. As can also be appreciated from fig. 1-4, NWdeep well 3308 may be formed during the same dedicated masking step (e.g., the deepest implant using a CMOS nWell implant chain) as one or more deep n-wells of a CMOS structure formed in substrate 3302, such as well NWdeep 304 of fig. 3.

In fig. 34, the n-type diffusion (nwsallow) 3402 may be formed using the shallowest implant of the CMOS nWell implant chain, which may be used to form the back gate terminal of the JFET, as described and illustrated below (3706). The well 3402 may be formed by the shallowest implant of the CMOS nWell implant chain by one special masking step (e.g., using the shallow mask 108 of fig. 1). As described, the use of the shallow mask 108 of fig. 1 enables the shallow implant to be separated from the standard CMOS flow and enables the use of thinner photoresist masks and associated smaller critical dimensions.

In fig. 35, p-type body diffusion 3502 can be formed in active region 3304 bounded by NWdeep 3308 and nwshow 3402 and using CMOS pwwell implants to construct a PJFET channel (3708). Then, referring to fig. 35 and 36,

pSD implants

3504, 3506 and source/

drain terminals

3604, 3606 may be formed, while nSD implants 3508 may be formed in pwwell channel 3502 to form front gate and front gate terminals 3608, and nSD implants 3510 may be formed in nwwindow 3402 to form back gate and back gate terminals 3610 (3710).

In an exemplary embodiment, some of the processing steps of fig. 33-36, such as

steps

3702, 3708, 3710, may be formed using a shared in-module processing step (e.g., mask) 160 utilized for standard CMOS flow.

Low/medium voltage laterally isolated JFET devices (which are constructed using the techniques of fig. 33-37) can be used, for example, for low frequency and/or low noise applications, while significantly reducing amplifier noise. In P-JFET channel 3502 isolated by shallow-split Nwell implants 3308 and deep-split Nwell implants 3402, the channel current can be turned off by applying a positive voltage to

front gates

3608, 3508 and back gate 3610/3510/3402. Thus, the device shown is completely isolated from the P-EPI/psubstrate 3302 by deep (vertical) N-well NWdeep 3308 and shallow (lateral) split N-well 3402. The device is normally on, operates at a negative voltage in the on mode, and is turned off using a positive voltage on the front gate 3608 and the back gate 3610. In addition, the device is suitable for use in designs without segmented Nwell features; nwell of standard CMOS devices can be constructed by NWwell and NWshallow to ensure the industry standard for pwwell isolation and latch-up immunity.

Fig. 38 is a simulated first cross section of the JFET of fig. 33-37. In fig. 38, cross-sectional simulation 3800 provides an example of the JFET of fig. 36 with corresponding labels. In fig. 39, an analog view 3900 shows the corresponding electric field distribution, including region 3902 showing the fully depleted channel of the JFET shown. Fig. 38 and 39 show that NWdeep 3308 isolates the P-JFET from the bulk substrate 3302 and may also serve as the back gate of the device (not shown in fig. 38, 39). Further, in some embodiments, NWdeep 3308 may be configured to partially counter dope pwwell 3502 and extend control of front gate 3608.

Fig. 40 is a third cross section of an electrical simulation of the JFETs of fig. 33-37, and fig. 41 is a fourth cross section of the JFETs of fig. 33-37. Fig. 40 shows a simulation 4000 of the off condition of a JFET device with a fully depleted channel. Fig. 41 shows the conduction condition and associated current density.

In the example of fig. 38-41, the corresponding JFET device can thus be implemented as an isolated normally-on JFET that is off at a specified voltage (e.g., 1.5V). More specifically, fig. 38 to 41 illustrate the manner in which the P-JFET channel can be fully depleted by applying a positive voltage on the front gate and back gate, and the manner in which the P-JFET channel can normally turn on when a negative voltage is applied on the drain and the gate voltage is below the threshold voltage (e.g., 1.5V). In some embodiments, the operating voltage may be limited to a relatively high voltage (e.g., >10V) by the CMOS well junction, and may be adjusted by appropriately using implant spacing and STI isolation.

Figure 42 shows a cross section of a second exemplary embodiment of a JFET. In fig. 42, a substrate 4202 has NWdeep wells 4203 formed therein that are connected to nwshow wells 4204. Then, pWell 4205 provides a channel for the JFET device formed with the drain 4206, source 4207, front gate 4208 and back gate 4210. The silicide layer 4212 provides a connection between the drain 4206 and the pSD region 4214, the source 4207 and the pSD region 4218, the front gate 4208 and the nSD region 4216, and the back gate 4210 and the nSD region 4220. STI 4222 and STI 4224 provide isolation. In some implementations, a split P-well option can be used to keep only a shallow portion of the P-well 4205 in the P-JFET channel.

Figure 43 shows a cross section of a third exemplary embodiment of a JFET. In FIG. 42, a substrate 4302 has an NWdeep well 4303 formed therein, which is connected to NWshallow well 4304 and encapsulates pWell 4305. Fig. 42 provides an embodiment of an N-JFET using NWdeep Nwell 4303 as the channel of a JFET device formed with drain 4306, source 4307, front gate 4308, and back gate 4310. Silicide layer 4312 provides a connection between drain 4306 and pSD region 4314, source 4307 and pSD region 4318, front gates 4308 and nSD region 4316, and back gates 4310 and nSD region 4320. A separate pWell 4322 is provided between the nwshow well 4304 and the back gate 4310, and isolation is provided by STI 4324. Thus, the p-well 4305 and the p-substrate provide the terminals of the front gate 4308 and the back gate 4310, respectively.

Fig. 44-55 illustrate exemplary embodiments and aspects of a fifth exemplary peripheral device (bipolar junction transistor (BJT)) using the techniques of fig. 1 and 2. The description of fig. 44-47 is provided below with reference to corresponding steps of the flowchart of fig. 48.

In fig. 44, active areas 4404(4802) defined by field oxide isolation 4406 are formed in a p-type substrate 4402. An n-type doped buried diffusion (NWdeep)4408 is then formed under the active area 4404 to separate the substrate surface and the active area/field isolation structures from the bottom of the substrate 4402 (4804). For example, the NWdeep mask 106 of fig. 1 may be used to form the NWdeep layer 4408. As can also be appreciated from fig. 1-4, NWdeep well 4408 may be formed during the same dedicated masking step (e.g., the deepest implant using a CMOS nWell implant chain) as one or more deep n-wells of a CMOS structure formed in substrate 4402, such as well NWdeep 304 of fig. 3.

In fig. 45, an n-type diffusion (nwsallow) 4502 can be formed using the shallowest implant of the CMOS nWell implant chain, which can be used to form the collector terminal of a BJT, as described and illustrated below (4806). The well 4502 may be formed by the shallowest implant of the CMOS nWell implant chain by one special masking step (e.g., using the shallow mask 108 of fig. 1). As described, the use of the shallow mask 108 of fig. 1 enables the shallow implant to be separated from the standard CMOS flow and enables the use of thinner photoresist masks and associated smaller critical dimensions.

In fig. 46 and 47, p-type body diffusion 4602 can be formed to provide the BJT base defined by NWdeep 4408 and nwsallow 4502 as the collector region, and CMOS pWell implantation (4808) is used. Then, referring to fig. 46 and 47,

pSD implants

4604, 4606 can be formed to use silicide layer 4702 to make connections to

base terminals

4704, 4706, respectively, and nSD implant 4608 can be formed in Pwell 4602, which provides the base of the BJT, and can be connected to emitter terminal 4708. Also, an nSD implant 4610 may be formed in nwshow 4502 and connected to collector terminal 4710 (4810).

Thus, fig. 44-48 illustrate the formation of a vertical BJT with emitter 4708/4608, bases 4602/4606, 4706, and collector 4408/4502/4610/4710. Using the techniques described herein, the BJTs of fig. 44-48 can be constructed having and providing higher gain than similar BJTs formed by conventional methods due to the lower energy of the split deep Nwell implant. Other embodiments are possible, for example, an nLDD implant may be added to nS region 4608 to improve the implant characteristics of the BJT.

In an exemplary embodiment, some of the processing steps of fig. 44-46, such as steps 4802, 4808, 4810, may be formed using a shared in-module processing step (e.g., mask) 160 utilized for standard CMOS flow.

Fig. 49 is a simulated first cross-section of the BJT of fig. 44-48. Fig. 49 shows pwwell 4602 is vertically encapsulated by NWdeep wells 4408 and laterally encapsulated by nwshow wells 4502. Furthermore, NWdeep well 4408 partially counter-dopes pwwell 4602 and helps increase the gain of the BJT device.

Fig. 50 is a simulated second cross-section of the BJT of fig. 44-48. Fig. 50 shows an exemplary electrostatic potential of a BJT device in reverse bias.

Fig. 51 is a simulated third cross-section of the BJT of fig. 44-48. Fig. 51 shows exemplary currents during forward operation of a BJT device.

Fig. 52 is a first exemplary current-voltage graph for the BJT of fig. 44-48. Fig. 53 is a second exemplary current-voltage graph for the BJT of fig. 44-48.

Fig. 54 shows a cross-section of a second exemplary embodiment of a BJT. In fig. 54, a substrate 5402 has NWdeep wells 5403 formed therein that are connected to nwshow wells 5404. Then, pWell 5405 provides a base for the BJT device formed with

base terminals

5406, 5407, emitter terminal 5408 and collector terminal 5410. Silicide layer 5412 provides connections between

base terminals

5406, 5407 and

pSD regions

5414, 5418, between emitter terminal 5408 and pSD region 5416, and between collector terminal 5410 and nSD region 5420. STI 5422 and STI 5424 provide isolation. In some embodiments, a split P-well option may be used to improve control over the base of the BJT.

Fig. 55 shows a cross-section of a third exemplary embodiment of a BJT using a PNP embodiment. In fig. 55, a substrate 5502 has nwshow wells 5404 formed therein as a base. Then, pWell 5505 and substrate 5502 provide a collector for a BJT device formed with base terminals 5506, 5507, an emitter 5508 terminal and a collector terminal 5510. Silicide layer 5512 provides a connection between base terminals 5506, 5507 and

pSD regions

5514, 5518, between emitter terminal 5508 and pSD region 5516, and between collector terminal 5510 and nSD region 5520. STI 5522 provides isolation.

In some implementations, a first implant into the substrate may be performed at a first depth and first and second wells laterally spaced apart from each other are defined within the substrate. A second implant into the substrate may be performed at a second depth, thereby defining third and fourth wells laterally spaced apart from each other within the substrate, wherein the second depth is closer to an implant surface of the substrate than the first depth. The CMOS device may be formed using at least the first well and the third well, and the peripheral device may be formed using at least the second well and the fourth well. For example, the first well and the third well may be used to reconstruct a CMOS well. The various wells may be doped n-type, p-type, or a combination thereof.

The peripheral device may comprise a single transistor or field effect device that is not electrically connected to another transistor or field effect device in a complementary configuration. The peripheral devices may be electrically connected to one or more CMOS transistors.

In some embodiments, a method of fabricating a semiconductor device includes: performing a first implant into the substrate at a first depth using a first mask having at least a first opening defining a first well and a second opening defining a second well; and performing a second implant into the substrate at a second depth using a second mask, the second mask having at least a third opening defining a third well and a fourth opening defining a fourth well, and the second depth being closer to the implanted surface of the substrate than the first depth. The method further includes forming a CMOS device using at least the first well and the third well, and forming a peripheral device using at least the second well and the fourth well.

The method may include forming device elements of the CMOS device and device elements of the peripheral device during a single sharing process. The first and second implants may be performed within a single process module. The method may include performing a fifth implant into the substrate using the first mask and at the first depth to form a fifth well; performing a sixth implant into the substrate using the second mask and at a second depth to form a sixth well; and forming a second CMOS device using at least the fifth well and the sixth well, wherein isolation is provided between the CMOS device and the second CMOS device by a portion of the substrate between the third well and the sixth well. The distance between the third well and the sixth well may be smaller than the distance between the first well and the fifth well. The active region of the peripheral device may be enclosed by the second well and the fourth well. The second well and the fourth well may be at least partially adjacent to each other in a direction perpendicular to the implantation surface, and may have different lengths in a direction parallel to the implantation surface.

The peripheral devices may include vertical double Diffused Metal Oxide Semiconductor (DMOS) transistors. The peripheral devices may include lateral double Diffused Metal Oxide Semiconductor (DMOS) transistors. The peripheral devices may include floating body MOS transistors. The peripheral device may include a Junction Field Effect Transistor (JFET). The peripheral device may include a Bipolar Junction Transistor (BJT).

When the peripheral device includes a floating body MOS transistor, an exemplary method may include defining a circular ring-shaped active region to accommodate an isolation terminal of the floating body MOS, using an isolation structure at a surface of the substrate, and forming a transistor active region within a hole of the circular ring-shaped active region to accommodate the floating body MOS transistor, the transistor active region defined by a second isolation structure at the surface of the substrate. The method may further include forming a diffusion region of the floating body MOS using a second well and forming a circular ring-shaped lateral isolation diffusion below the circular ring-shaped active region using a fourth well. The method may further include forming a body diffusion within the hole of the annular lateral isolation diffusion, forming a floating body MOS transistor within the body diffusion, and forming the body diffusion along with a well implant process for forming a CMOS device.

In some embodiments, a method of fabricating a semiconductor device may include forming a CMOS device of a CMOS platform on a substrate, the CMOS device being formed using at least a first deep well and at least a first shallow well, the first deep well being implanted using a first mask and the first shallow well being implanted using a second mask. The method may include forming at least one peripheral device on the substrate using at least a second deep well and at least a second shallow well, the second deep well being implanted using a first mask and the second shallow well being implanted using a second mask.

The method may include forming a first device element of a CMOS device and a second device element of at least one peripheral device during a single sharing process. The substrate may be doped to a first conductivity type, and the first and second device elements may include first and second wells of opposite conductivity types, respectively. The at least one peripheral device may include a vertical double Diffused Metal Oxide Semiconductor (DMOS) transistor. The at least one peripheral device may include a lateral double Diffused Metal Oxide Semiconductor (DMOS) transistor. The DMOS transistor may be a vertical DMOS or a lateral DMOS.

In some embodiments, a method of fabricating a semiconductor device may include: forming a CMOS device of a CMOS platform on a substrate, the CMOS device being formed using at least a first deep well and at least a first shallow well, the first deep well being implanted using a first mask and the first shallow well being implanted using a second mask; and forming at least one floating body MOS device on the substrate using at least a second deep well and at least a second shallow well, the second deep well being implanted using the first mask and the second shallow well being implanted using the second mask. The method may further include defining a circular ring shaped active region to accommodate an isolation terminal of the floating body MOS, using an isolation structure at a surface of the substrate, and forming a transistor active region within a hole of the circular ring shaped active region to accommodate a floating body MOS transistor, the transistor active region defined by a second isolation structure at the surface of the substrate. The method may further include forming a buried diffusion region of the floating body MOS using a second well and forming a circular ring-shaped lateral isolation diffusion below the circular ring-shaped active region using a fourth well. The method may further include forming a bulk diffusion within the hole of the annular lateral isolation diffusion. The method may further include forming a floating body MOS transistor within the body diffusion and/or forming the body diffusion along with a well implant process for forming a CMOS device.

It will be understood that in the foregoing description, when an element such as a layer, region, substrate, or component is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it can be directly on, connected to, or coupled to the other element or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intervening elements or layers present. Elements shown as directly on, directly connected to, or directly coupled to the element may be referred to in this manner, although the terms directly on …, directly connected to …, or directly coupled to … may not be used throughout the detailed description. The claims of this application, if any, may be amended to recite exemplary relationships that are described in the specification or illustrated in the drawings.

As used in this specification and the claims, the singular form can include the plural form unless the context clearly dictates otherwise. In addition to the orientations shown in the figures, spatially relative terms (e.g., above …, above …, above …, below …, below …, below …, below …, etc.) are intended to encompass different orientations of the device in use or operation. In some embodiments, relative terms above … and below … may include vertically above … and vertically below …, respectively. In some embodiments, the term adjacent can include laterally adjacent or horizontally adjacent.

Some embodiments may be implemented using various semiconductor processing and/or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like.

While certain features of the described embodiments have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments. It is to be understood that such modifications and variations are presented by way of example only, and not limitation, and that various changes in form and details may be made. Any portion of the devices and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The embodiments described herein can include various combinations and/or subcombinations of the functions, components and/or features of the different embodiments described.

Claims

1. A method of fabricating a semiconductor device, comprising:

performing a first implant into the substrate at a first depth using a first mask having at least a first opening defining a first well and a second opening defining a second well;

performing a second implant into the substrate at a second depth using a second mask, the second mask having at least a third opening defining a third well and a fourth opening defining a fourth well, and the second depth being closer to an implant surface of the substrate than the first depth;

forming a CMOS device using at least the first well and the third well; and

forming a peripheral device using at least the second well and the fourth well.

2. The method of claim 1, further comprising:

forming device elements of the CMOS device and device elements of the peripheral device during a single sharing process.

3. The method of claim 1, wherein the first and second injections are performed within a single process module.

4. The method of claim 1, further comprising:

performing a fifth implant into the substrate using the first mask and at the first depth to form a fifth well;

performing a sixth implant into the substrate using the second mask and at the second depth to form a sixth well; and

forming a second CMOS device using at least the fifth well and the sixth well, wherein isolation is provided between the CMOS device and the second CMOS device by a portion of the substrate between the third well and the sixth well,

wherein a distance between the third well and the sixth well is smaller than a distance between the first well and the fifth well, and

further wherein the active region of the peripheral device is enclosed by the second well and the fourth well.

5. The method of claim 1, wherein the peripheral device comprises a vertical double-diffused metal-oxide-semiconductor (DMOS) transistor.

6. The method of claim 1, wherein the peripheral device comprises a lateral double-diffused metal-oxide-semiconductor (DMOS) transistor.

7. The method of claim 1, wherein the peripheral device comprises a floating body MOS transistor.

8. The method of claim 1, wherein the peripheral device comprises a Junction Field Effect Transistor (JFET).

9. The method of claim 1, wherein the peripheral device comprises a Bipolar Junction Transistor (BJT).

10. A method of fabricating a semiconductor device, comprising:

forming a CMOS device of a CMOS platform on a substrate, the CMOS device formed using at least a first deep well and at least a first shallow well, the first deep well implanted using a first mask and the first shallow well implanted using a second mask; and

forming at least one peripheral device on the substrate using at least a second deep well and at least a second shallow well, the second deep well being implanted using the first mask and the second shallow well being implanted using the second mask.

11. The method of claim 10, further comprising:

forming a first device element of the CMOS device and a second device element of the at least one peripheral device during a single sharing process.

12. A method of fabricating a semiconductor device, comprising:

forming at least one double-diffused metal-oxide transistor DMOS in the substrate, the DMOS transistor being formed using at least a second deep well and at least a second shallow well, the second deep well being implanted using the first mask and the second shallow well being implanted using the second mask.

13. A method of fabricating a semiconductor device, comprising:

forming a Complementary Metal Oxide Semiconductor (CMOS) device using at least the first well and the third well; and

forming a floating body MOS transistor using at least the second well and the fourth well.

14. A method of fabricating a semiconductor device, comprising:

forming at least one floating body MOS device on the substrate using at least a second deep well and at least a second shallow well, the second deep well being implanted using the first mask and the second shallow well being implanted using the second mask.