CN112711039B - Time synchronization attack detection and correction method and device based on optimal estimation - Google Patents

Time synchronization attack detection and correction method and device based on optimal estimation Download PDF

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CN112711039B
CN112711039B CN202110323384.0A CN202110323384A CN112711039B CN 112711039 B CN112711039 B CN 112711039B CN 202110323384 A CN202110323384 A CN 202110323384A CN 112711039 B CN112711039 B CN 112711039B
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clock
clock error
sequence
model
receiver
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CN112711039A (en
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冯旭哲
陆青
周超
胡梅
马超
刘宗敏
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National University of Defense Technology
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
    • G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
    • G01S19/13—Receivers
    • G01S19/21—Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
    • G—PHYSICS
    • G04—HOROLOGY
    • G04R—RADIO-CONTROLLED TIME-PIECES
    • G04R20/00—Setting the time according to the time information carried or implied by the radio signal
    • G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/14—Network architectures or network communication protocols for network security for detecting or protecting against malicious traffic
    • H04L63/1408—Network architectures or network communication protocols for network security for detecting or protecting against malicious traffic by monitoring network traffic
    • H04L63/1416—Event detection, e.g. attack signature detection

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Abstract

The application relates to a time synchronization attack detection and correction method and device based on optimal estimation, computer equipment and a storage medium. The method comprises the following steps: acquiring an observation clock error sequence, constructing an optimization model by taking a clock error binomial model parameter and a clock error attack amount as optimization variables and taking the minimum difference value between the observation clock error sequence and a real clock error sequence when being attacked by time as an optimization target, and solving the optimization model under a constraint condition to obtain an estimation value of the clock error binomial model parameter and an estimation value of the clock error attack amount; fitting a clock error model in an observation window according to the estimated value of the clock error binomial model parameter, and determining a predicted clock error sequence in the observation window; and obtaining a receiver clock error model fitting residual error according to the observed clock error sequence and the predicted clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and if so, correcting a current clock error calculation value of the receiver according to an estimated value of a clock error attack amount.

Description

Time synchronization attack detection and correction method and device based on optimal estimation
Technical Field
The application relates to the field of satellite time service anti-spoofing, in particular to a time synchronization attack detection and correction method and device based on optimal estimation, computer equipment and a storage medium.
Background
With the continuous improvement of the technology level, the precision requirement of each industry on time synchronization becomes higher and higher. For example, power systems utilize phase measurement units to estimate the state of the grid in real time and perform system control and power scheduling accordingly, while phase measurement units rely heavily on precise time synchronization, which can be achieved by satellite navigation solutions or network time synchronization protocols. Besides, time synchronization is widely used in the fields of mobile communication, aviation control, robot cooperative control, and sensor-based passive positioning.
Positioning, navigation and time service are three basic services of a global satellite navigation system. The satellite time service is the most important time service method at present because of the characteristics of wide audience, good accuracy, long-term stability and the like. The time service type receiver is used as a main device for realizing time synchronization, and high-precision time is obtained by resolving the received satellite navigation signal, so that a standard time signal is provided for each system. At present, the time synchronization system based on the GPS/BDS uses civil GPS/BDS signals, and the signal structure of the civil satellite navigation signals is disclosed, which makes the time synchronization system vulnerable to time synchronization attack. The attack aiming at the time synchronization system is to inject false satellite navigation signals into the receiver, so that the target receiver solves and obtains wrong time information, and further, the time of an important infrastructure department of the opposite party cannot be synchronized. Time synchronization attacks, which typically do not see the effect immediately, cause losses and hazards that are covert and persistent, so efficient time synchronization attack resistant algorithms are necessary.
The prior art has the problem of poor real-time performance.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a time synchronization attack detection and correction method, apparatus, computer device and storage medium based on optimal estimation, which can improve the real-time performance of the algorithm.
A time synchronization attack detection and correction method based on optimal estimation comprises the following steps:
acquiring an observation clock error sequence of the satellite time service receiver in an observation window;
according to a coefficient matrix of an observation clock error sequence and a binomial model for describing clock errors, taking parameters of the clock error binomial model and a clock error attack amount as optimization variables, and taking the minimum difference value between the observation clock error sequence and a real clock error sequence when being attacked by time as an optimization target, constructing an optimization model, and solving the optimization model under a constraint condition to obtain an estimation value of the parameters of the clock error binomial model and an estimation value of the clock error attack amount; the clock error binomial model parameters comprise clock drift, frequency drift and clock error;
fitting a clock error model in the observation window according to the estimated value of the clock error binomial model parameter, and determining a predicted clock error sequence in the observation window according to the clock error model;
and obtaining a receiver clock error model fitting residual error according to the observed clock error sequence and the predicted clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and if so, correcting a current clock error calculation value of the receiver according to an estimated value of a clock error attack amount.
In one embodiment, the method further comprises the following steps: according to the coefficient matrix of the observation clock error sequence and the binomial model used for describing the clock error, the parameters of the clock error binomial model and the clock error attack amount are taken as optimization variables, the minimum difference value between the observation clock error sequence and the real clock error sequence when the clock error is attacked is taken as an optimization target, and the construction of the optimization model is as follows:
Figure 486327DEST_PATH_IMAGE001
wherein the content of the first and second substances,
Figure 983168DEST_PATH_IMAGE002
；
Figure 633592DEST_PATH_IMAGE003
a sequence of observed clock differences is represented,
Figure 557686DEST_PATH_IMAGE004
which is indicative of the current observation time instant,
Figure 926350DEST_PATH_IMAGE005
which represents the length of the observation window,
Figure 210570DEST_PATH_IMAGE006
represents the observed clock error;
Figure 246659DEST_PATH_IMAGE007
an estimated value representing the clock error attack amount;
Figure 76075DEST_PATH_IMAGE008
a true value representing the amount of clock error attack;
Figure 932035DEST_PATH_IMAGE009
representing estimated values of clock-error binomial model parameters, wherein
Figure 36258DEST_PATH_IMAGE010
Respectively representing estimated values of clock drift, frequency drift and clock offset of the receiver;
Figure 146427DEST_PATH_IMAGE011
representing the true values of the parameters of the clock-difference binomial model;
Figure 677903DEST_PATH_IMAGE012
representing a coefficient matrix;
Figure 755580DEST_PATH_IMAGE013
a true value representing the receiver clock drift;
solving the optimized model under the constraint condition to obtain an estimated value of clock error binomial model parameters and an estimated value of clock error attack quantity; the constraint condition is
Figure 397914DEST_PATH_IMAGE014
。
In one embodiment, the method further comprises the following steps: fitting a clock error model in the observation window according to the estimated value of the clock error binomial model parameter, and determining a predicted clock error sequence in the observation window according to the clock error model as follows:
Figure 143016DEST_PATH_IMAGE015
wherein the content of the first and second substances,
Figure 829081DEST_PATH_IMAGE016
，nindicating a time sequence number within the observation window;
Figure 394055DEST_PATH_IMAGE017
representing the predicted clock error obtained from the clock error model.
In one embodiment, the method further comprises the following steps: obtaining the fitting error sequence of each time in the observation window according to the difference value of the observation clock difference sequence and the predicted clock difference sequence
Figure 574500DEST_PATH_IMAGE018
，
Figure 174109DEST_PATH_IMAGE019
；
From the fitting error sequence
Figure 529611DEST_PATH_IMAGE021
，
Figure 581880DEST_PATH_IMAGE022
，
Figure 566017DEST_PATH_IMAGE023
Representing the step length of the sliding window to obtain the mean value of the fitting error
Figure 20132DEST_PATH_IMAGE024
And standard deviation of
Figure 64311DEST_PATH_IMAGE025
；
Judgment of
Figure 853144DEST_PATH_IMAGE026
Fitting error of time of day
Figure 640972DEST_PATH_IMAGE027
Whether or not to fall on
Figure 949593DEST_PATH_IMAGE028
Within the interval, if
Figure 899095DEST_PATH_IMAGE029
Then the receiver is considered to be in
Figure 925957DEST_PATH_IMAGE030
The time is not attacked by time synchronization if
Figure 2628DEST_PATH_IMAGE031
Then the receiver is considered to be in
Figure 431336DEST_PATH_IMAGE030
The time of day is subject to a time synchronization attack.
In one embodiment, the method further comprises the following steps: if the receiver is attacked, correcting the current clock error calculation value of the receiver according to the estimated value of the clock error attack quantity, and obtaining the corrected clock error calculation value as follows:
Figure 551738DEST_PATH_IMAGE032
wherein the content of the first and second substances,
Figure 331476DEST_PATH_IMAGE033
is shown inmAn estimate of the amount of clock-error attack at a time.
In one embodiment, the method further comprises the following steps: obtaining a receiver clock error model fitting residual error according to the observation clock error sequence and the prediction clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, if so, correcting the current clock error calculation value of the receiver according to the estimated value of the clock error attack amount, and moving the observation window backwards
Figure 195526DEST_PATH_IMAGE034
And (5) continuously carrying out time synchronization attack detection and correction on each observation epoch.
In one embodiment, the method further comprises the following steps: and resolving to obtain an observation clock error sequence in an observation window according to the satellite navigation signal received by a receiving antenna of the satellite time service receiver.
An optimal estimation based time synchronization attack detection and correction device, comprising:
the observation clock error sequence acquisition module is used for acquiring an observation clock error sequence of the satellite time service receiver in an observation window;
the optimization model solving module is used for establishing an optimization model by taking parameters of a clock error binomial model and a clock error attack amount as optimization variables and taking the minimum difference value between the observed clock error sequence and a real clock error sequence when the clock error binomial model is attacked by time as an optimization target according to a coefficient matrix of the observed clock error binomial model and the binomial model used for describing the clock error, and solving the optimization model under the constraint condition to obtain an estimation value of the parameters of the clock error binomial model and an estimation value of the clock error attack amount; the clock error binomial model parameters comprise clock drift, frequency drift and clock error;
the system comprises a prediction clock error sequence acquisition module, a clock error model generation module and a clock error correction module, wherein the prediction clock error sequence acquisition module is used for fitting a clock error model in an observation window according to an estimated value of a clock error binomial model parameter and determining a prediction clock error sequence in the observation window according to the clock error model;
and the clock error correction module is used for obtaining a receiver clock error model fitting residual error according to the observed clock error sequence and the predicted clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and correcting the current clock error calculation value of the receiver according to the estimated value of the clock error attack amount if the receiver is attacked.
A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
acquiring an observation clock error sequence of the satellite time service receiver in an observation window;
according to a coefficient matrix of an observation clock error sequence and a binomial model for describing clock errors, taking parameters of the clock error binomial model and a clock error attack amount as optimization variables, and taking the minimum difference value between the observation clock error sequence and a real clock error sequence when being attacked by time as an optimization target, constructing an optimization model, and solving the optimization model under a constraint condition to obtain an estimation value of the parameters of the clock error binomial model and an estimation value of the clock error attack amount; the clock error binomial model parameters comprise clock drift, frequency drift and clock error;
fitting a clock error model in the observation window according to the estimated value of the clock error binomial model parameter, and determining a predicted clock error sequence in the observation window according to the clock error model;
and obtaining a receiver clock error model fitting residual error according to the observed clock error sequence and the predicted clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and if so, correcting a current clock error calculation value of the receiver according to an estimated value of a clock error attack amount.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
acquiring an observation clock error sequence of the satellite time service receiver in an observation window;
according to a coefficient matrix of an observation clock error sequence and a binomial model for describing clock errors, taking parameters of the clock error binomial model and a clock error attack amount as optimization variables, and taking the minimum difference value between the observation clock error sequence and a real clock error sequence when being attacked by time as an optimization target, constructing an optimization model, and solving the optimization model under a constraint condition to obtain an estimation value of the parameters of the clock error binomial model and an estimation value of the clock error attack amount; the clock error binomial model parameters comprise clock drift, frequency drift and clock error;
fitting a clock error model in the observation window according to the estimated value of the clock error binomial model parameter, and determining a predicted clock error sequence in the observation window according to the clock error model;
and obtaining a receiver clock error model fitting residual error according to the observed clock error sequence and the predicted clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and if so, correcting a current clock error calculation value of the receiver according to an estimated value of a clock error attack amount.
According to the time synchronization attack detection and correction method and device based on optimal estimation, the computer equipment and the storage medium, an observation clock difference sequence of the satellite time service receiver in an observation window is obtained, the clock difference binomial model parameters and the clock difference attack amount are used as optimization variables, the minimum difference value between the observation clock difference sequence and the real clock difference sequence when the satellite time service receiver is attacked is used as an optimization target, an optimization model is constructed, the optimization model is solved under the constraint condition, and the estimation value of the clock difference binomial model parameters and the estimation value of the clock difference attack amount are obtained; then, fitting a clock error model in an observation window according to the estimated value of the clock error binomial model parameter, and further determining a predicted clock error sequence in the observation window; and obtaining a receiver clock error model fitting residual error according to the observed clock error sequence and the predicted clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and if so, correcting a current clock error calculation value of the receiver according to an estimated value of a clock error attack amount. Compared with other time synchronization attack resisting algorithms, the algorithm provided by the invention can be detected and corrected in real time, is good in real time and has a good effect on resisting time synchronization attack.
Drawings
FIG. 1 is a schematic flow chart of a method for time-synchronized attack detection and correction based on optimal estimation according to an embodiment;
FIG. 2 is a schematic flow chart of a method for time-synchronized attack detection and correction based on optimal estimation in another embodiment;
FIG. 3 is a schematic diagram of detecting and correcting a mutant time synchronization attack as contemplated in one embodiment;
FIG. 4 is a diagram of detecting and correcting a persistent time synchronization attack as is involved in one embodiment;
FIG. 5 is a block diagram of an embodiment of an apparatus for time-synchronized attack detection and modification based on optimal estimation;
FIG. 6 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The time synchronization attack detection and correction method based on the optimal estimation can be applied to the following application environments. Executing a time synchronization attack detection and correction method based on optimal estimation through a satellite time attack detection terminal, acquiring an observation clock error sequence of a satellite time service receiver in an observation window, constructing an optimal model by taking clock error binomial model parameters and a clock error attack amount as optimization variables and taking the minimum difference value between the observation clock error sequence and a real clock error sequence when the satellite time service receiver is subjected to time attack as an optimization target, and solving the optimal model under a constraint condition to obtain an estimated value of the clock error binomial model parameters and an estimated value of the clock error attack amount; then, fitting a clock error model in an observation window according to the estimated value of the clock error binomial model parameter, and further determining a predicted clock error sequence in the observation window; and obtaining a receiver clock error model fitting residual error according to the observed clock error sequence and the predicted clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and if so, correcting a current clock error calculation value of the receiver according to an estimated value of a clock error attack amount.
In one embodiment, as shown in fig. 1, there is provided a time synchronization attack detection and correction method based on optimal estimation, comprising the following steps:
and 102, acquiring an observation clock error sequence of the satellite time service receiver in an observation window.
The deviation between the time obtained by the satellite time service receiver and the standard system time is called receiver clock error, and the clock error of the receiver can be expressed by a binomial model within a period of time as follows:
Figure 478740DEST_PATH_IMAGE035
in the formula (I), the compound is shown in the specification,
Figure 550470DEST_PATH_IMAGE036
for receiver at reference time
Figure 286345DEST_PATH_IMAGE037
Deviation from system time, also known as receiver clock error;
Figure 219666DEST_PATH_IMAGE038
for receiver internal clock at reference time
Figure 91807DEST_PATH_IMAGE039
Frequency drift relative to actual frequency;
Figure 85171DEST_PATH_IMAGE040
is the drift factor of the receiver clock frequency, i.e. the clock drift.
In the prior art, a binomial coefficient is determined by performing polynomial fitting on observation data, and a sliding window mode is adopted to recur backwards so as to ensure that the obtained coefficient has good continuity.
104, according to the observation clock error sequence and the coefficient matrix of the binomial model for describing the clock error, taking the parameters of the clock error binomial model and the clock error attack amount as optimization variables, and taking the minimum difference value between the observation clock error sequence and the real clock error sequence when being attacked by time as an optimization target, constructing an optimization model, and solving the optimization model under the constraint condition to obtain the estimation value of the parameters of the clock error binomial model and the estimation value of the clock error attack amount;
the coefficient matrix is predefined according to a clock-difference binomial model structure. In the embodiment, the optimal estimation mode is adopted, the solution of the clock error binomial model parameters and the clock error attack amount is converted into the solution optimization model, and the algorithm provided by the invention can be detected and corrected in real time, so that the time synchronization attack resisting method has a good effect.
And step 106, fitting a clock error model in the observation window according to the estimated value of the clock error binomial model parameter, and determining a predicted clock error sequence in the observation window according to the clock error model.
The predicted clock difference sequence is obtained according to a clock difference binomial model constructed by the estimated binomial model parameters, and has certain continuity and predictability.
And 108, obtaining a receiver clock difference model fitting residual according to the observation clock difference sequence and the prediction clock difference sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock difference model fitting residual, and if so, correcting the current clock difference calculation value of the receiver according to the estimated value of the clock difference attack quantity.
If the difference between the observed clock difference value obtained by the receiver at the observation time and the clock difference value predicted by the binomial is too large, the receiver is considered to be attacked by time synchronization, and the current clock difference calculation value of the receiver needs to be corrected according to the estimated value of the clock difference attack amount.
In the time synchronization attack detection and correction method based on optimal estimation, an observation clock error sequence of a satellite time service receiver in an observation window is obtained, a clock error binomial model parameter and a clock error attack amount are used as optimization variables, the minimum difference value between the observation clock error sequence and a real clock error sequence when the satellite time service receiver is attacked is used as an optimization target, an optimization model is constructed, the optimization model is solved under a constraint condition, and an estimation value of the clock error binomial model parameter and an estimation value of the clock error attack amount are obtained; then, fitting a clock error model in an observation window according to the estimated value of the clock error binomial model parameter, and further determining a predicted clock error sequence in the observation window; and obtaining a receiver clock error model fitting residual error according to the observed clock error sequence and the predicted clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and if so, correcting a current clock error calculation value of the receiver according to an estimated value of a clock error attack amount. Compared with other time synchronization attack resisting algorithms, the algorithm provided by the invention can be detected and corrected in real time, is good in real time and has a good effect on resisting time synchronization attack.
In one embodiment, the method further comprises the following steps: according to the coefficient matrix of the observation clock error sequence and the binomial model used for describing the clock error, the parameters of the clock error binomial model and the clock error attack amount are taken as optimization variables, the minimum difference value between the observation clock error sequence and the real clock error sequence when the clock error is attacked is taken as an optimization target, and the construction of the optimization model is as follows:
Figure 56145DEST_PATH_IMAGE041
wherein the content of the first and second substances,
Figure 527577DEST_PATH_IMAGE042
；
Figure 519804DEST_PATH_IMAGE043
a sequence of observed clock differences is represented,
Figure 684069DEST_PATH_IMAGE044
which is indicative of the current observation time instant,
Figure 128957DEST_PATH_IMAGE045
which represents the length of the observation window,
Figure 404080DEST_PATH_IMAGE047
represents the observed clock error;
Figure 765660DEST_PATH_IMAGE048
an estimated value representing the clock error attack amount;
Figure 835248DEST_PATH_IMAGE049
a true value representing the amount of clock error attack;
Figure 33011DEST_PATH_IMAGE050
representing estimated values of clock-error binomial model parameters, wherein
Figure 846246DEST_PATH_IMAGE051
Respectively representing estimated values of clock drift, frequency drift and clock offset of the receiver;
Figure 813065DEST_PATH_IMAGE052
representing the true values of the parameters of the clock-difference binomial model;
Figure 538707DEST_PATH_IMAGE053
representing a coefficient matrix;
Figure 489345DEST_PATH_IMAGE054
a true value representing the receiver clock drift;
solving the optimized model under the constraint condition to obtain an estimated value of clock error binomial model parameters and an estimated value of clock error attack quantity; the constraint condition is
Figure 840692DEST_PATH_IMAGE055
。
In one embodiment, the method further comprises the following steps: fitting a clock error model in the observation window according to the estimated value of the clock error binomial model parameter, and determining a predicted clock error sequence in the observation window according to the clock error model as follows:
Figure 662018DEST_PATH_IMAGE056
wherein the content of the first and second substances,
Figure 338987DEST_PATH_IMAGE057
，nindicating a time sequence number within the observation window;
Figure 760609DEST_PATH_IMAGE058
representing the predicted clock error obtained from the clock error model.
In one embodiment, the method further comprises the following steps: obtaining the fitting error sequence of each time in the observation window according to the difference value of the observation clock difference sequence and the predicted clock difference sequence
Figure 650068DEST_PATH_IMAGE059
，
Figure 857058DEST_PATH_IMAGE060
(ii) a From the fitting error sequence
Figure 173770DEST_PATH_IMAGE061
，
Figure 833422DEST_PATH_IMAGE062
，
Figure 274374DEST_PATH_IMAGE063
Representing the step length of the sliding window to obtain the mean value of the fitting error
Figure 70292DEST_PATH_IMAGE064
And standard deviation of
Figure 89063DEST_PATH_IMAGE065
(ii) a Judgment of
Figure 970432DEST_PATH_IMAGE066
Fitting error of time of day
Figure 201693DEST_PATH_IMAGE067
Whether or not to fall on
Figure 366964DEST_PATH_IMAGE068
Within the interval, if
Figure 556637DEST_PATH_IMAGE069
Then the receiver is considered to be in
Figure 925301DEST_PATH_IMAGE070
The time is not attacked by time synchronization if
Figure 960253DEST_PATH_IMAGE071
Then the receiver is considered to be in
Figure 730763DEST_PATH_IMAGE070
The time of day is subject to a time synchronization attack. If the receiver is attacked, correcting the current clock error calculation value of the receiver according to the estimated value of the clock error attack quantity, and obtaining the corrected clock error calculation value as follows:
Figure 576491DEST_PATH_IMAGE072
wherein the content of the first and second substances,
Figure 698030DEST_PATH_IMAGE073
is shown inmTime of dayAn estimate of the amount of clock error attack.
In one embodiment, the method further comprises the following steps: obtaining a receiver clock error model fitting residual error according to the observation clock error sequence and the prediction clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, if so, correcting the current clock error calculation value of the receiver according to the estimated value of the clock error attack amount, and moving the observation window backwards
Figure 271094DEST_PATH_IMAGE074
And (5) continuously carrying out time synchronization attack detection and correction on each observation epoch.
In one embodiment, the method further comprises the following steps: and resolving to obtain an observation clock error sequence in an observation window according to the satellite navigation signal received by a receiving antenna of the satellite time service receiver.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 2, a time synchronization attack detection and correction method based on optimal estimation is provided, which includes the following steps:
step (1): the receiver is obtained by resolving according to the satellite navigation signal received by the receiving antennakClock difference value of receiver of time of day
Figure 161690DEST_PATH_IMAGE075
；
Step (2): will be provided withkMarking the actual clock error attack amount of the time
Figure 427586DEST_PATH_IMAGE076
Length of sliding observation window
Figure 770843DEST_PATH_IMAGE077
The step size of the sliding is marked
Figure 662444DEST_PATH_IMAGE078
. When the receiver is in normal operation, the signal is calculated and obtained
Figure 407546DEST_PATH_IMAGE079
After a true receiver clock difference value
Figure 844344DEST_PATH_IMAGE080
Within the observation window of (a) solving the following optimization model:
Figure 674897DEST_PATH_IMAGE081
wherein
Figure 589763DEST_PATH_IMAGE082
，
Figure 937174DEST_PATH_IMAGE083
Is a receiver clock difference sequence, and each item of the sequence is a clock difference value obtained by the receiver after normal resolving in the step (1) or correction in the step (6).
Figure 810452DEST_PATH_IMAGE084
The sequence is the estimated clock error attack quantity of each time, and the estimation result is 0 to indicate that the receiver is not attacked by time synchronization at the time.
Figure 128301DEST_PATH_IMAGE085
Is estimated to bekA fitting coefficient of a receiver clock error binomial model of a time, wherein
Figure 846859DEST_PATH_IMAGE086
Respectively representing the clock drift, frequency drift and clock offset of the receiver, because the clock drift of the high-precision crystal oscillator used by the general receiver is less than that of the common receiver in a short time
Figure 566553DEST_PATH_IMAGE087
In magnitude, therefore there are
Figure 594421DEST_PATH_IMAGE088
Satisfy the requirement of
Figure 399566DEST_PATH_IMAGE089
。
Figure 187393DEST_PATH_IMAGE090
The coefficient matrix is obtained by using a clock error binomial model of the receiver in an observation window
Figure 496015DEST_PATH_IMAGE091
The discretization of each observation epoch in the interior is obtained by:
Figure 711095DEST_PATH_IMAGE092
and (3): utilizing the receiver clock error binomial model parameters obtained in the step (2)
Figure 472378DEST_PATH_IMAGE093
To fit the observation window
Figure 814629DEST_PATH_IMAGE094
Inner receiver clock error model:
Figure 977757DEST_PATH_IMAGE095
wherein
Figure 363739DEST_PATH_IMAGE096
。
And (4): using the product obtained in step (1)
Figure 877897DEST_PATH_IMAGE097
Receiver clock error solution value of each time in time period
Figure 741947DEST_PATH_IMAGE098
Subtracting the model fitting value obtained in the step (3)
Figure 274429DEST_PATH_IMAGE099
So as to obtain the receiver clock error fitting error of each time in the current observation window
Figure 96891DEST_PATH_IMAGE100
Then calculating the fitting error sequence of the receiver clock error model
Figure 832766DEST_PATH_IMAGE102
Mean value of
Figure 500508DEST_PATH_IMAGE103
And standard deviation of
Figure 638228DEST_PATH_IMAGE104
；
And (5): judging fitting error
Figure 631592DEST_PATH_IMAGE105
Whether or not to fall on
Figure 336986DEST_PATH_IMAGE107
Within the interval, if
Figure 73998DEST_PATH_IMAGE108
Then the receiver is considered to be in
Figure 66225DEST_PATH_IMAGE109
Time of day not receiving timeSynchronous attack, in which the clock error is resolved
Figure 964911DEST_PATH_IMAGE110
Is a normal value if
Figure 940957DEST_PATH_IMAGE111
If yes, executing step (6);
and (6): utilizing the clock error attack amount estimated in the step (2)
Figure 199769DEST_PATH_IMAGE112
To the clock difference solution
Figure 312082DEST_PATH_IMAGE113
And (5) correcting:
Figure 381669DEST_PATH_IMAGE114
the corrected clock error
Figure 313853DEST_PATH_IMAGE115
In place of the receivermClock error calculation value of time
Figure 392667DEST_PATH_IMAGE116
. Moving the observation window backward
Figure 110218DEST_PATH_IMAGE117
And (4) observing the epoch and returning to the step (2).
In another specific example, MATLAB simulation software of MathWorks company and a high-precision positioning type receiver board UB4B0 of Unicorecomm company are used for verifying the time synchronization attack detection and correction method. The time synchronization attack signal is obtained through simulation on the basis of the received real satellite signal, the attack signal cannot influence the position calculation result of the receiver, and only influences relevant parameters of a receiver clock. The receiver receives clock error obtained by resolving real satellite signals and resolves the clock error when suffering from mutant time synchronization attackThe relationship between the obtained clock offset and the clock offset corrected by the method is shown in FIG. 3 (a), the mutant time synchronization attack starts at the 60 th time, and the time attack amount is
Figure 85128DEST_PATH_IMAGE118
The error between the receiver clock difference corrected by the method and the clock difference obtained by resolving the received real satellite signal is shown in fig. 3 (b), and the maximum error between the receiver clock difference and the clock difference is about
Figure 770187DEST_PATH_IMAGE119
. The relationship between the clock offset obtained by the receiver receiving the real satellite signal and the clock offset obtained by the receiver when suffering the continuous time synchronization attack and the clock offset obtained by the receiver after being corrected by the method is shown in fig. 4 (a), the continuous time attack starts from the 60 th s, and the time attack amount is about
Figure 121534DEST_PATH_IMAGE120
The error between the receiver clock difference corrected by the method and the clock difference obtained by resolving the received real satellite signal is shown in fig. 4 (b), and the maximum error between the receiver clock difference and the clock difference is
Figure 208439DEST_PATH_IMAGE121
. According to the embodiment, the algorithm provided by the invention has better time synchronization attack detection and correction effects.
In one embodiment, as shown in fig. 5, there is provided an optimal estimation-based time synchronization attack detection and modification apparatus, including: an observation clock difference sequence obtaining module 502, an optimization model solving module 504, a prediction clock difference sequence obtaining module 506 and a clock difference correction module 508, wherein:
an observation clock difference sequence obtaining module 502, configured to obtain an observation clock difference sequence of the satellite time service receiver in an observation window;
an optimization model solving module 504, configured to construct an optimization model according to a coefficient matrix of an observation clock difference sequence and a binomial model used for describing clock differences, with parameters of the clock difference binomial model and a clock difference attack amount as optimization variables, and with a minimum difference between the observation clock difference sequence and a real clock difference sequence when subjected to time attack as an optimization target, and solve the optimization model under a constraint condition to obtain an estimated value of the parameters of the clock difference binomial model and an estimated value of the clock difference attack amount; the clock error binomial model parameters comprise clock drift, frequency drift and clock error;
a predicted clock difference sequence obtaining module 506, configured to fit a clock difference model in the observation window according to the estimated value of the clock difference binomial model parameter, and determine a predicted clock difference sequence in the observation window according to the clock difference model;
and the clock offset correction module 508 is configured to obtain a receiver clock offset model fitting residual according to the observed clock offset sequence and the predicted clock offset sequence, judge whether the receiver is attacked by time synchronization according to the receiver clock offset model fitting residual, and correct a current clock offset calculation value of the receiver according to an estimated value of a clock offset attack amount if the receiver is attacked.
The optimization model solving module 504 is further configured to construct an optimization model, according to the observed clock difference sequence and the coefficient matrix of the binomial model used for describing the clock difference, with the clock difference binomial model parameters and the clock difference attack amount as optimization variables, and with the minimum difference between the observed clock difference sequence and the real clock difference sequence when subjected to time attack as an optimization objective:
Figure 869096DEST_PATH_IMAGE122
wherein the content of the first and second substances,
Figure 775872DEST_PATH_IMAGE123
；
Figure 196489DEST_PATH_IMAGE124
a sequence of observed clock differences is represented,
Figure 872321DEST_PATH_IMAGE125
which is indicative of the current observation time instant,
Figure 720191DEST_PATH_IMAGE126
which represents the length of the observation window,
Figure 885504DEST_PATH_IMAGE127
represents the observed clock error;
Figure 844233DEST_PATH_IMAGE128
an estimated value representing the clock error attack amount;
Figure 640150DEST_PATH_IMAGE129
a true value representing the amount of clock error attack;
Figure 658922DEST_PATH_IMAGE130
representing estimated values of clock-error binomial model parameters, wherein
Figure 274711DEST_PATH_IMAGE131
Respectively representing estimated values of clock drift, frequency drift and clock offset of the receiver;
Figure 37131DEST_PATH_IMAGE132
representing the true values of the parameters of the clock-difference binomial model;
Figure 202402DEST_PATH_IMAGE133
representing a coefficient matrix;
Figure 126495DEST_PATH_IMAGE134
a true value representing the receiver clock drift;
solving the optimized model under the constraint condition to obtain an estimated value of clock error binomial model parameters and an estimated value of clock error attack quantity; the constraint condition is
Figure 495160DEST_PATH_IMAGE135
。
The predicted clock difference sequence obtaining module 506 is further configured to fit a clock difference model in the observation window according to the estimated values of the clock difference binomial model parameters, and determine that the predicted clock difference sequence in the observation window is:
Figure 795691DEST_PATH_IMAGE136
wherein the content of the first and second substances,
Figure 300622DEST_PATH_IMAGE137
，nindicating a time sequence number within the observation window;
Figure 411928DEST_PATH_IMAGE138
representing the predicted clock error obtained from the clock error model.
The clock error correction module 508 is further configured to obtain a fitting error sequence at each time in the observation window according to a difference between the observed clock error sequence and the predicted clock error sequence
Figure 267889DEST_PATH_IMAGE139
，
Figure 106532DEST_PATH_IMAGE140
；
From the fitting error sequence
Figure 997127DEST_PATH_IMAGE141
，
Figure 263024DEST_PATH_IMAGE142
，
Figure 606280DEST_PATH_IMAGE143
Representing the step length of the sliding window to obtain the mean value of the fitting error
Figure 232303DEST_PATH_IMAGE144
And standard deviation of
Figure 977405DEST_PATH_IMAGE145
；
Judgment of
Figure 414202DEST_PATH_IMAGE146
Fitting error of time of day
Figure 244755DEST_PATH_IMAGE147
Whether or not to fall on
Figure 425201DEST_PATH_IMAGE148
Within the interval, if
Figure 38191DEST_PATH_IMAGE149
Then the receiver is considered to be in
Figure 911469DEST_PATH_IMAGE150
The time is not attacked by time synchronization if
Figure 698160DEST_PATH_IMAGE152
Then the receiver is considered to be in
Figure 947875DEST_PATH_IMAGE150
The time of day is subject to a time synchronization attack. If the receiver is attacked, correcting the current clock error calculation value of the receiver according to the estimated value of the clock error attack quantity, and obtaining the corrected clock error calculation value as follows:
Figure 401991DEST_PATH_IMAGE153
wherein the content of the first and second substances,
Figure 429858DEST_PATH_IMAGE154
is shown inmAn estimate of the amount of clock-error attack at a time.
The clock error correction module 508 is also used for moving the observation window backward
Figure DEST_PATH_IMAGE155
And (5) continuously carrying out time synchronization attack detection and correction on each observation epoch.
The observation clock difference sequence obtaining module 502 is further configured to obtain an observation clock difference sequence in the observation window by resolving according to a satellite navigation signal received by a receiving antenna of the satellite time service receiver.
For specific limitations of the time synchronization attack detection and correction device based on the optimal estimation, see the above limitations on the time synchronization attack detection and correction method based on the optimal estimation, which are not described herein again. The modules in the above-mentioned time synchronization attack detection and correction device based on optimal estimation can be wholly or partially realized by software, hardware and their combination. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 6. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a time synchronization attack detection and modification method based on an optimal estimate. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 6 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In an embodiment, a computer device is provided, comprising a memory storing a computer program and a processor implementing the steps of the above method embodiments when executing the computer program.
In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A time synchronization attack detection and correction method based on optimal estimation is characterized by comprising the following steps:
acquiring an observation clock error sequence of the satellite time service receiver in an observation window;
according to the coefficient matrix of the observation clock error sequence and the binomial model for describing the clock error, taking the parameters of the clock error binomial model and the clock error attack amount as optimization variables, and taking the minimum difference value between the observation clock error sequence and the real clock error sequence when being attacked by time as an optimization target, constructing an optimization model, and solving the optimization model under the constraint condition to obtain the estimation value of the parameters of the clock error binomial model and the estimation value of the clock error attack amount; the clock error binomial model parameters comprise clock drift, frequency drift and clock error;
fitting a clock error model in the observation window according to the estimated value of the clock error binomial model parameter, and determining a predicted clock error sequence in the observation window according to the clock error model;
and obtaining a receiver clock error model fitting residual error according to the observation clock error sequence and the prediction clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and if so, correcting the current clock error calculation value of the receiver according to the estimated value of the clock error attack amount.
2. The method according to claim 1, wherein, based on the observed clock difference sequence and the coefficient matrix of the binomial model for describing the clock difference, the optimization model is constructed by using the parameters of the binomial model for clock difference and the attack amount for clock difference as optimization variables and using the minimum difference between the observed clock difference sequence and the real clock difference sequence when being attacked by time as an optimization target, and the optimization model is solved under the constraint condition to obtain the estimated values of the parameters of the binomial model for clock difference and the estimated values of the attack amount for clock difference, comprising:
according to the coefficient matrix of the observation clock error sequence and the binomial model used for describing the clock error, the parameters of the clock error binomial model and the clock error attack amount are taken as optimization variables, the minimum difference value between the observation clock error sequence and the real clock error sequence when the clock error is attacked is taken as an optimization target, and the construction of the optimization model is as follows:
Figure 885914DEST_PATH_IMAGE001
wherein the content of the first and second substances,
Figure 49042DEST_PATH_IMAGE002
，
Figure 966182DEST_PATH_IMAGE003
representing any one column vector;
Figure 214761DEST_PATH_IMAGE004
representing the sequence of observed clock differences,
Figure 78812DEST_PATH_IMAGE005
which is indicative of the current observation time instant,
Figure 893184DEST_PATH_IMAGE006
which represents the length of the observation window,
Figure 184488DEST_PATH_IMAGE007
represents the observed clock error;
Figure 920363DEST_PATH_IMAGE008
a sequence representing an estimate of the amount of said clock error attack;
Figure 384842DEST_PATH_IMAGE009
a sequence of true values representing the amount of clock error attack;
Figure 991404DEST_PATH_IMAGE010
representing estimated values of said clock-difference binomial model parameters, wherein
Figure 719189DEST_PATH_IMAGE011
Respectively representing estimated values of clock drift, frequency drift and clock offset of the receiver;
Figure 739097DEST_PATH_IMAGE012
representing the true values of the parameters of the clock-difference binomial model;
Figure 679372DEST_PATH_IMAGE013
representing the coefficient matrix;
Figure 468336DEST_PATH_IMAGE014
a true value representing the receiver clock drift;
solving the optimization model under the constraint condition to obtain an estimation value of the clock error binomial model parameter and a sequence of the estimation value of the clock error attack quantity, and obtaining the estimation value of the clock error attack quantity according to the sequence of the estimation value of the clock error attack quantity; the constraint condition is
Figure 367022DEST_PATH_IMAGE015
。
3. The method of claim 2, wherein fitting a clock model within the observation window based on the estimated values of the clock binomial model parameters, determining a sequence of predicted clock differences within the observation window based on the clock model, comprises:
fitting a clock error model in the observation window according to the estimated value of the clock error binomial model parameter, and determining a predicted clock error sequence in the observation window according to the clock error model as follows:
Figure 560979DEST_PATH_IMAGE016
wherein the content of the first and second substances,
Figure 570523DEST_PATH_IMAGE017
，nindicating a time sequence number within the observation window;
Figure 479573DEST_PATH_IMAGE018
representing the predicted clock error obtained from the clock error model.
4. The method of claim 3, wherein determining whether the receiver is under a time synchronization attack based on a current clock offset in the observed clock offset sequence and the predicted clock offset sequence comprises:
obtaining a fitting residual sequence of each moment in the observation window according to the difference value of the observation clock difference sequence and the prediction clock difference sequence
Figure 18002DEST_PATH_IMAGE019
，
Figure 12503DEST_PATH_IMAGE020
；
From the fitted residual sequence
Figure 560159DEST_PATH_IMAGE021
，
Figure 261399DEST_PATH_IMAGE022
，
Figure 33046DEST_PATH_IMAGE023
Representing the step length of the sliding window to obtain the mean value of the fitting residual errors
Figure 718105DEST_PATH_IMAGE024
And standard deviation of
Figure 803873DEST_PATH_IMAGE025
；
Judgment of
Figure 421936DEST_PATH_IMAGE026
Fitting residual of time of day
Figure 833326DEST_PATH_IMAGE027
Whether or not to fall on
Figure 474522DEST_PATH_IMAGE028
Within the interval, if
Figure 160719DEST_PATH_IMAGE029
Then the receiver is considered to be in
Figure 836551DEST_PATH_IMAGE030
The time is not attacked by time synchronization if
Figure 153262DEST_PATH_IMAGE031
Then the receiver is considered to be in
Figure 344072DEST_PATH_IMAGE030
The time of day is subject to a time synchronization attack.
5. The method of claim 4, wherein the modifying the current clock offset solution of the receiver according to the estimated value of the clock offset attack amount if the receiver is attacked comprises:
if the receiver is attacked, correcting the current clock error calculation value of the receiver according to the estimated value of the clock error attack quantity, and obtaining the corrected clock error calculation value as follows:
Figure 37222DEST_PATH_IMAGE032
wherein the content of the first and second substances,
Figure 567560DEST_PATH_IMAGE033
is shown inmAn estimate of the amount of said clock error attack at a time.
6. The method of claim 5, wherein determining whether the receiver is under time synchronization attack according to the current clock offset in the observed clock offset sequence and the predicted clock offset sequence, and if the receiver is under attack, after correcting the current clock offset calculation value of the receiver according to the estimated value of the clock offset attack amount, the method comprises:
moving the observation window backward
Figure 117490DEST_PATH_IMAGE034
And (5) continuously carrying out time synchronization attack detection and correction on each observation epoch.
7. The method according to any one of claims 1 to 6, wherein acquiring the sequence of observation clock differences of the satellite timing receiver in the observation window comprises:
and resolving to obtain an observation clock error sequence in an observation window according to the satellite navigation signal received by a receiving antenna of the satellite time service receiver.
8. An optimal estimation based time synchronization attack detection and modification apparatus, the apparatus comprising:
the observation clock error sequence acquisition module is used for acquiring an observation clock error sequence of the satellite time service receiver in an observation window;
the optimization model solving module is used for constructing an optimization model by taking clock error binomial model parameters and clock error attack quantity as optimization variables and taking the minimum difference value between an observation clock error sequence and a real clock error sequence when the clock error binomial model is attacked by time as an optimization target according to the observation clock error sequence and a coefficient matrix of a binomial model for describing clock error, and solving the optimization model under the constraint condition to obtain an estimation value of the clock error binomial model parameters and an estimation value of the clock error attack quantity; the clock error binomial model parameters comprise clock drift, frequency drift and clock error;
the predicted clock difference sequence acquisition module is used for fitting a clock difference model in the observation window according to the estimated value of the clock difference binomial model parameter and determining a predicted clock difference sequence in the observation window according to the clock difference model;
and the clock error correction module is used for obtaining a receiver clock error model fitting residual error according to the observation clock error sequence and the prediction clock error sequence, judging whether the receiver is attacked by time synchronization according to the receiver clock error model fitting residual error, and correcting the current clock error calculation value of the receiver according to the estimated value of the clock error attack amount if the receiver is attacked.
9. A computer device comprising a memory and a processor, the memory storing a computer program, wherein the processor implements the steps of the method of any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.
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