CN112702377A - Data stream conversion system - Google Patents
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Abstract
The invention discloses a data stream conversion system, comprising: the system comprises a first control module, a second control module and a data stream conversion module, wherein the second control module is respectively connected with the first control module and the data stream conversion module; the first control module is used for initiating a data stream conversion request; the second control module is used for generating a data stream conversion signaling according to the data stream conversion request and sending the data stream conversion signaling to the data stream conversion module according to a preset message structure, wherein the preset message structure comprises a data stream packet indication field and a channel number indication field for defining the maximum channel number; the data stream conversion module is used for grouping the cached data stream according to the data stream conversion signaling, converting the data stream into a preset format and generating feedback information aiming at the data stream conversion signaling. According to the technical scheme, the data stream is grouped and converted into the preset format, so that the transmission efficiency of the data stream is improved, and the stability of data stream transmission is ensured.
Description
Technical Field
The embodiment of the invention relates to the technical field of data communication, in particular to a data stream conversion system.
Background
Video or image processing systems are increasingly used in a wide variety of fields, such as device inspection/detection, security monitoring, industrial vision, and artificial intelligence. With the increasing of the resolution of the video or image processing system, the number of channels (Lane) used in the terminal device for video display increases, and the Link Rate (LR) on each Lane also increases, which makes higher and higher requirements on the real-time performance, coordination, and the like of the hardware platform of the video or image processing system.
Under the scene that the data processing capacity is greatly increased, the data streams among different lanes are unbalanced in distribution and non-uniform in format, so that the transmission efficiency of the data streams is low, and the system stability is poor.
Disclosure of Invention
The invention provides a data stream conversion system, which improves the transmission efficiency of data streams and ensures the stability of data stream transmission by grouping and converting the data streams into a preset format.
An embodiment of the present invention provides a data stream conversion system, including: the device comprises a first control module, a second control module and a data stream conversion module, wherein the second control module is respectively connected with the first control module and the data stream conversion module; the first control module is used for initiating a data stream conversion request; the second control module is configured to generate a data stream conversion signaling according to the data stream conversion request, and send the data stream conversion signaling to the data stream conversion module according to a preset message structure, where the preset message structure includes a data stream packet indication field and a channel number indication field for defining a maximum channel number; and the data stream conversion module is used for grouping the cached data stream according to the data stream conversion signaling, converting the data stream into a preset format and generating feedback information aiming at the data stream conversion signaling.
Further, the second control module includes:
the data stream conversion module comprises:
the grouping submodule is used for determining the caching quantity of the data stream and grouping the cached data stream according to the data stream grouping indication field and the maximum channel number;
and the conversion submodule is used for converting the cached data stream into a preset bit width, changing the position of the data effective bit and extracting the data effective bit to obtain the data stream in a preset format.
Further, the data stream conversion module further includes:
and the output submodule is used for synchronously outputting the data stream with the preset format or asynchronously outputting the data stream according to the channel serial number.
Further, the output sub-module is specifically configured to:
if the number of the cached data streams is greater than or equal to the number of the channels, asynchronously outputting the data streams according to the channel serial numbers; otherwise, synchronously outputting the data stream with the preset format.
Further, the output sub-module is specifically configured to:
if the pixel data width of the cached data stream is smaller than the pixel data width of the data stream on the channel, asynchronously outputting the data stream according to the channel serial number; otherwise, synchronously outputting the data stream with the preset format.
Further, the preset message structure further includes: a master-slave module definition field and a feedback field;
the master-slave module definition field is used for defining a master module and a slave module in the data stream conversion module;
the feedback field is used for defining the module state after the data stream conversion signaling interaction is completed, and the module state comprises an affirmation state and a non-affirmation state.
Further, the preset message structure further includes: a data stream buffer number indication field;
the data stream cache quantity indication field is used for indicating the quantity, the cache mode and the data stream operation mode of cached data streams, wherein the cache mode comprises line cache, field cache and clock cache, and the data stream operation mode comprises ping-pong operation, serial-parallel conversion operation, pipeline operation and data interface synchronization operation.
Further, the preset message structure further includes: a format conversion indication field;
the format conversion indication field is used for defining bit width of the cached data stream, preset bit width, and address of a start bit and address of an end bit for extracting a valid bit of data.
Further, the preset message structure further includes:
and the data stream output mode selection field is used for defining an output mode, and the output mode comprises synchronous output and asynchronous output according to the channel sequence number.
Further, the preset message structure further includes: checking the field;
and the check field is used for checking the data stream conversion signaling according to a preset specification and indicating the interaction failure of the data stream conversion signaling when the check fails.
An embodiment of the present invention provides a data stream conversion system, including: the device comprises a first control module, a second control module and a data stream conversion module, wherein the second control module is respectively connected with the first control module and the data stream conversion module; the first control module is used for initiating a data stream conversion request; the second control module is configured to generate a data stream conversion signaling according to the data stream conversion request, and send the data stream conversion signaling to the data stream conversion module according to a preset message structure, where the preset message structure includes a data stream packet indication field and a channel number indication field for defining a maximum channel number; and the data stream conversion module is used for grouping the cached data stream according to the data stream conversion signaling, converting the data stream into a preset format and generating feedback information aiming at the data stream conversion signaling. According to the technical scheme, the data stream is grouped and converted into the preset format, so that the transmission efficiency of the data stream is improved, and the stability of data stream transmission is ensured.
Drawings
Fig. 1 is a schematic structural diagram of a data stream conversion system according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a data stream conversion system according to a second embodiment of the present invention;
fig. 3 is a schematic diagram of signaling interaction of a data stream conversion system according to a second embodiment of the present invention;
fig. 4 is a schematic structural diagram of a video processing system for implementing data stream conversion according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic structural diagram of a data stream conversion system according to an embodiment of the present invention. The present embodiment is applicable to a case where a change in Intellectual Property (IP) kernel parameters, a change in bit width of a video stream, a change in display mode, a change in control register flag, and the like occur in a video or image processing system, and a change occurs to a different data stream.
Specifically, as shown in fig. 1, the system includes: the system comprises a first control module 10, a second control module 20 and a data stream conversion module 30, wherein the second control module 20 is respectively connected with the first control module 10 and the data stream conversion module 30; the first control module 10 is configured to initiate a data stream conversion request; the second control module 20 is configured to generate a data stream conversion signaling according to the data stream conversion request and send the data stream conversion signaling to the data stream conversion module 30 according to a preset message structure; the data stream conversion module 30 is configured to packetize the cached data stream and convert the buffered data stream into a preset format according to the data stream conversion signaling, and generate first feedback information for the data stream conversion signaling, where the preset message structure includes a channel number indication field and a data stream packet indication field.
The Lane number indication field is used to indicate the Lane number that needs to be supported after the data stream conversion, for example, N Lanes, where N is a positive integer and represents that the Lane number that can be supported by the physical layer is N. Grouping is performed according to the supported maximum Lane number in the data processing process, and under the condition, all Lanes smaller than the supported maximum Lane number can be compatible, so that the hardware platform can adapt to the Lane number. The data stream packet indication field is used to indicate the packet status of the data stream on each Lane. The data stream conversion module 30 may complete the data stream reassembly and distribution on all lanes in the video image processing system in output manners such as buffering, grouping, output format conversion, time-sharing asynchronization/buffer synchronization, etc. for the data stream according to the indication of the data stream conversion signaling of the preset message structure of the second control module 20, thereby automatically and effectively completing the distribution of the data stream on each Lane according to different system requirements.
Further, the data stream conversion module 30 includes at least one of the following: the device comprises an external storage module, a quick storage module, a peripheral module and a video interface physical layer implementation module. The external storage module is used for storing original data streams of videos or images needing to be displayed in the system. For example, the external storage module may employ a Flash memory (e.g., Nand Flash), a Solid State Drive (SSD), and other storage media. The fast storage module is a module for temporarily storing Data in order to further reduce the latency in the case of signaling execution with large Data processing and low round trip delay (latency) inside the second control module 20, and may use a fast and low latency Physical device, such as a Double Data Rate SDRAM (DDR), etc., the peripheral module may be a General-purpose input/output (GPIO), a Universal Asynchronous Receiver/Transmitter (UART), a Universal Serial Bus (USB), a network Port, etc., the video interface Physical Layer implementation module is used to drive a Physical Layer implementation of a Display module, such as a Physical Layer (PHY) of a transceiver TX/Receiver (TX/RX) of a Display interface (Display Port, DP), a port Physical Layer (D-PHY) of a Serial Display Interface (MIPI) of a Mobile Industry Processor Interface (Mobile Industry Processor Interface).
Further, the first control module 10 is an embedded control module or an FPGA module; correspondingly, the second control module 20 is an FPGA module or an embedded control module.
Specifically, the embedded control module may adopt any embedded chip and system, and is used for a data stream conversion request, and may also be used for requesting to read/write register data, requesting to enable/close a video display unit or module, requesting to control an external device or requesting to modify parameter settings of the video display module, and the like. The FPGA module is used for implementing or executing operations which need a large amount of data processing and low round-trip delay (latency) such as storage control, peripheral control, video interface IP core implementation and the like.
The data stream conversion system of this embodiment initiates a data stream conversion request through the first control module, generates a data stream conversion signaling through the second control module, and indicates the data stream conversion signaling to the data stream conversion module according to the preset message structure, and the data stream conversion module can perform operations such as caching, grouping, format conversion and the like according to the data stream conversion signaling of the preset message structure of the second control module, and avoid data stream distribution imbalance among different lanes by grouping and converting the data stream into the preset format, thereby enhancing stability and robustness of transmission of different data streams, and improving transmission efficiency of the data streams.
Example two
The present embodiment is optimized based on the above embodiments, and the interaction process between the second control module 20 and the data stream conversion module 30 is specifically described. The embodiment is applicable to a Video image processing system based on a Field Programmable Gate Array (FPGA) and an embedded system, and particularly relates to a Video image processing system with a digital Video Interface standard (DP) of a Video Electronics Standards Association (VESA), a Mobile Industry Processor Interface standard (MIPI), and a High Definition Multimedia Interface standard (HDMI). Technical details that are not elaborated in this embodiment may be referred to any of the embodiments described above.
Fig. 2 is a schematic structural diagram of a data stream conversion system according to a second embodiment of the present invention. As shown in fig. 2, the data stream conversion module 30 includes: the grouping submodule 31 is configured to determine the buffering amount of the data stream, and group the buffered data stream according to the data stream grouping indication field and the maximum channel number; the converting submodule 32 is configured to convert the cached data stream into a preset bit width, change the position of the data valid bit, and extract the data valid bit to obtain a data stream in a preset format.
Optionally, the data stream may be buffered according to a clock and a fixed data packet and output in a multi-stage pipeline manner, or may be buffered according to a row or a field (column) and output in a ping-pong operation manner. The grouping submodule 31 sorts the cached data streams according to Lane number and grouping indication field in the system to match data on each Lane, and the converting submodule 32 performs output format conversion on the data streams according to the requirement of the video image processing system, specifically may change the number of effective input data streams according to the output requirement, for example, 2 effective input data streams are converted into 4 effective output data streams, that is, the Dual mode is converted into the Quad mode, etc.; conversion of data bit width, such as 48bit to 24 bit; changes in data Significant bits, for example, changes in the positions of the Most Significant Bits (MSB), the Least Significant Bits (LSB), and the like; for example, when the input data bit width corresponding to each color in the input RGB data is 16 bits, in order to correspond to different output data bit widths, for example, 8 bits/10 bits/12 bits/16 bits, etc., in the process of extracting effective data bits, it is necessary to indicate the start/end data bit address of the actually selected effective data bit, for example, when the input data bit width is 16 bits, for the 8-bit output data bit width, the start/end data bit addresses are [0:7], [6:13], etc.
Further, the data stream conversion module 30 further includes: and the output submodule 33 is configured to output the data stream in the preset format synchronously or asynchronously according to the channel sequence number.
Specifically, the asynchronous output may be time-sharing asynchronous, that is, the input data streams are output in turn in time-sharing mode according to the serial number of Lane, and for a Lane without data stream output at a certain time, an output-temporarily-prohibited mode is adopted, which is asynchronous with the Lane with the output data stream, so that the input data stream does not need to be cached again, and the internal storage resources of the video image processing system, especially the control board, are effectively saved. Synchronous output means that the input data stream is firstly buffered, and when the number of buffered data streams is greater than or equal to the number of lanes used, the data stream will be output simultaneously on all lanes used, so that all lanes will simultaneously output completely synchronous output data.
Further, the output sub-module 33 is specifically configured to: if the number of the cached data streams is greater than or equal to the number of the channels, asynchronously outputting the data streams according to the channel serial numbers; otherwise, synchronously outputting the data stream with the preset format.
Further, the output sub-module 33 is specifically configured to: if the pixel data width of the cached data stream is smaller than the pixel data width of the data stream on the channel, asynchronously outputting the data stream according to the channel serial number; otherwise, synchronously outputting the data stream with the preset format.
Specifically, under the condition that the number of input data streams is greater than or equal to the available Lane number, or under the condition that the width of pixel data of the input data streams is smaller than the width of pixel data of data streams on the Lane to be output, asynchronous output is adopted in the process of converting the bit width of the data; and under the condition that the number of input data streams is less than or equal to the number of available Lanes, or the pixel data width of the input data streams is greater than the pixel data width of the data streams on the output Lanes, synchronous output is adopted in the process of converting the data bit width.
Further, the presetting of the message structure further includes: a master-slave module definition field and a feedback field; the master-slave module definition field is used for defining a master module and a slave module in the data stream conversion module; the feedback field is used for defining the module state after the data stream conversion signaling interaction is completed, and the module state comprises an affirmation state and a non-affirmation state.
Specifically, the master-slave module definition field is used to define the master module and the slave module in the data stream conversion module 30. The master module and the slave module are defined according to the initiator and the receiver of the command, and the master-slave relationship between the modules corresponding to different signaling interaction processes may be different. For example, the embedded module may serve as a master module to initiate data stream conversion signaling, and the FPGA module serves as a slave module to receive and execute the signaling; the FPGA module may also serve as a master module to initiate a data stream conversion signaling to the embedded module, which is a slave module at this time. For another example, the data stream conversion signaling of the second control module 20 is forwarded by the master module in the data stream conversion module 30 to the slave module, and the slave module completes the data stream conversion and feeds back to the master module, and the master module feeds back to the second control module 20. In the above example, the data stream conversion signaling and the first feedback information are transmitted according to a master-slave structure, rather than a step-by-step transmission, and each group of modules having a master-slave relationship performs layered forwarding and interaction of signaling in respective links, so that the organization structure of the system is standardized, and the reliability and efficiency of interaction are improved. The feedback field is used for defining the module state after the data stream conversion signaling interaction is completed, and the module state comprises an ACK state and a NACK state, so that the confirmation operation of the signaling interaction is completed.
Further, the presetting of the message structure further includes: a data stream buffer number indication field; the data stream cache quantity indication field is used for indicating the quantity, the cache mode and the data stream operation mode of cached data streams, wherein the cache mode comprises line cache, field cache and clock cache, and the data stream operation mode comprises ping-pong operation, serial-parallel conversion operation, pipeline operation and data interface synchronization operation.
Specifically, ping-pong operation means that an input data stream is distributed to two data buffer areas, the two data buffer areas are mutually matched and switched according to beats in each buffer period, and the buffered data stream is operated and processed without pause, so that the ping-pong operation can be applied to a pipeline algorithm, seamless buffering and efficient processing of the data stream are realized, and the space of the buffer areas is saved; the serial-parallel conversion operation is to convert a serial input data stream into a parallel data stream for output, and is simple to implement; the pipeline operation refers to that all steps of conversion processing of data streams are connected in series in a unidirectional mode to improve the working frequency; the data interface synchronization operation can realize the synchronization of data streams through a synchronization enabling or synchronization indicating signal, and the efficiency is improved.
Further, the presetting of the message structure further includes: a format conversion indication field; the format conversion indication field is used for defining bit width of the cached data stream, preset bit width, and address of a start bit and address of an end bit for extracting valid bits of data.
Further, the presetting of the message structure further includes: and the data stream output mode selection field is used for defining an output mode, and the output mode comprises synchronous output and asynchronous output according to the channel sequence number.
Further, the preset message structure further comprises a check field; the check field is used for checking the data stream conversion signaling according to a preset specification and indicating the interaction failure of the data stream conversion signaling when the check fails, so that the interactive signaling and the message structure are checked under the condition that the quality of a signaling transmission channel cannot be ensured, and the quality of the transmitted signaling and the transmitted message structure is ensured. Communication specifications are established through interaction between the modules through the preset message structure, and data stream conversion can be realized only under the condition that interactive signaling conforms to the preset specifications.
Further, the master module is configured to receive a data stream conversion signaling sent by the second control module according to a preset message structure, where the data stream conversion signaling is forwarded to the slave module through the master module; the slave module is used for grouping the cached data stream according to the data stream conversion signaling, converting the buffered data stream into a preset format, generating first feedback information aiming at the data stream conversion signaling and sending the first feedback information to the master module.
On the basis of the above embodiment, the second control module 20 is further configured to send the initialization signaling to the master modules in the first control module 10 and the data stream conversion module 30 before receiving the data stream conversion request, so that the master module forwards the initialization signaling to the slave modules to initialize the modules; the second control module 20 is further configured to receive second feedback information of the master module of the data stream conversion module 30, where the second feedback information is obtained by the master module through the slave module, and the second feedback information is used to indicate that the slave module is initialized. The master module and the slave module are determined according to the master-slave module definition field in the initialization signaling. The initialization signaling is transmitted layer by layer according to a master-slave relationship. After all the slave modules are initialized, the first feedback information is fed back to the master module until the second control module 20 receives the second feedback information.
Fig. 3 is a schematic diagram of signaling interaction of a data stream conversion system according to a second embodiment of the present invention. As shown in fig. 3, the signaling interaction process specifically includes:
and S1, the FPGA module sends the initialization signaling to the embedded control module.
Specifically, the FPGA module determines a master-slave module definition field according to a hardware condition of video or image processing, where the field is compatible with all modules and can uniquely identify each module; determining a channel number indicating field, a data stream packet indicating field, a data stream cache quantity indicating field, a format conversion indicating field, a data stream output mode selecting field and a master-slave module defining field according to a physical process of data stream conversion. Optionally, the method further includes determining a signaling checking mechanism and determining a checking field, when the master/slave module sends/receives the signaling, first determining whether the signaling to be interacted meets the requirement according to the signaling checking mechanism, and if so, indicating that the signaling transmission is correct; otherwise, signaling transmission failure is indicated, and a predefined retransmission or signaling feedback mechanism is started.
S2, the FPGA module sends the initialization signaling to the main module in the data stream conversion module 30.
It should be noted that the FPGA module is the second control module 20, the embedded control module is the first control module 10, and S1 and S2 are preferably performed synchronously.
S3, the master module forwards the initialization signaling to the slave module.
S4, the slave module is ready and feeds back the second feedback information to the master module.
And S5, the main module feeds back second feedback information to the FPGA module.
Specifically, the second feedback information is used to indicate that the slave module has already been prepared according to the initialization signaling, and can identify the signaling of the preset message structure sent by the corresponding master module in the subsequent communication process.
And S6, the embedded control module initiates a data stream conversion request to the FPGA module.
S7, the FPGA module sends the data flow conversion signaling generated based on the data flow conversion request to the main module,
and S8, the master module forwards the data stream conversion signaling to the slave module.
And S9, the slave module groups the buffered data stream, converts the buffered data stream into a preset format and feeds back first feedback information to the master module.
S10, the master module feeds back the first feedback information to the second control module 20.
Specifically, the master module receives and confirms the signaling feedback field, and performs, for example, retransmission, reset or other operations preset by the system according to the information in the signaling feedback field, and feeds back the first feedback information to the second control module 20, which is used to indicate the implementation of data stream conversion.
Further, the main module feeds back the implementation situation of the data stream conversion to the FPGA module through the first feedback information, and after receiving the first feedback information, the FPGA module may implement a process preset by the system, such as retransmission, retry, waiting, and the like, so as to complete the request initiated by the embedded control module in the current interaction process as much as possible, so as to improve the implementation efficiency of the signaling interaction process each time.
And S11, feeding back the data stream conversion result to the embedded control module by the FPGA module.
Specifically, each time the first control module 10 initiates a request, the second control module 20 will respond, and try to complete signaling interaction several times until it is successful. And adopting preset strategies including retransmission, retry, waiting and the like in the process of the attempt. If all the preset strategies fail, the information of interaction failure is fed back to the first control module 10.
In the signaling interaction process, the first control module 10 is an embedded control module, the second control module 20 is an FPGA module, the data stream conversion module 30 includes an external storage module, a fast storage module, a peripheral module and a video interface physical layer implementation module, the FPGA further includes a plurality of modules, and the modules and the external related modules may have a master-slave relationship.
Illustratively, the process of grouping and converting the buffered data stream into the preset format is as follows:
a. the second control module determines a master/slave module definition field according to the physical platform module condition of the system, and the field can be compatible with all modules and can uniquely identify each module;
b. the second control module determines and initializes Lane number indicating fields;
c. the second control module determines and initializes a data stream cache quantity indication field;
d. the second control module determines a grouping indication field and initializes the grouping indication field;
e. the second control module determines and initializes the format conversion indication field;
f. the second control module determines and initializes a data stream output mode selection field;
g. the second control module sends a data stream conversion signaling to a slave module of the data stream conversion module according to a preset message structure;
h. reading Lane number indication fields from the modules and determining the maximum Lane number supported by the system;
i. reading the data stream buffer quantity indication field from the module, and distributing the resources and space needed by the buffer for the data stream;
j. reading a grouping indication field from the module, and determining the Lane number and grouping actually used by the system;
k. reading the format conversion indication field from the module, and determining the actual data stream output bit width and the effective bit address index;
reading a data stream output mode selection field from the slave module, and determining a data stream output mode and a strategy according to the actually used Lane number and grouping;
m, the slave module completes grouping and conversion of the data stream according to the data stream conversion signaling and the information read from each indication field;
n, the slave module feeds back a signaling feedback field to the second control module;
and o, the second control module receives and confirms the signaling feedback field to confirm the completion of the data stream conversion process.
In the process, the signaling interaction between the second air control module and the data stream conversion module is carried out according to the structure of the master module and the slave module in a grading manner.
Fig. 4 is a schematic structural diagram of a video processing system for data stream conversion according to a second embodiment of the present invention. As shown in fig. 4, the first control module 10 may be an embedded control module, the second control module 20 may be an FPGA module, and the physical layer data stream conversion module 30 may include an external storage module, a fast storage module, a peripheral module, a video interface physical layer implementation module, and the like. Wherein, the FPGA module comprises at least one of the following components: the device comprises a bus interaction module, a Micro Control Unit (MCU) video stream preprocessing Unit, a video data stream transmission control module, a clock control module, an embedded soft core control module, a bus controller module, a video pattern processing module, an internal storage controller module, an external control module, a display clock generator module, a video time schedule controller module and a video interface IP core module.
Illustratively, the bus interaction module is used for selecting or deciding all modules connected with the bus interaction module; the MCU video stream preprocessing unit is used for preprocessing and converting the video data stream input from the external storage module according to the format and the parameter type set by the system so as to facilitate subsequent processing; the video data stream transmission control module is used for controlling the time sequence and parameters of the data stream after the data stream is preprocessed and converted; the clock control module is responsible for generating and controlling a global clock in the process of processing the video or the image; the embedded soft core control module is a control core of the FPGA module, is used for realizing core functions of time sequence control, parameter configuration, physical process realization and the like of all modules in the FPGA module, and can adopt Xilinx soft sum processors (MicroBlaze) and the like; the bus controller module is used for controlling all modules connected with the bus interaction module; the video pattern processing module is responsible for adapting to mode conversion and time sequence control of a video image data stream corresponding to the video interface IP core module; the internal storage controller module is used for realizing the control of the fast storage module, including the writing/reading of data stream, frame control and the like; the peripheral control module is used for controlling all peripheral modules, including starting/closing of the peripheral, working mode control and the like; the display clock generator module is used for realizing the time sequence control of all modules, namely the video interface IP core module and the video interface physical layer; the video time sequence controller module is responsible for data conversion, time sequence control and the like in the process of transmitting data input from the video pattern processing module to the video interface IP core module.
It should be noted that, when the second control module 20 is an FPGA module, it may further include a plurality of modules having a master-slave relationship therein, at this time, the embedded soft core control module is a control center, and other modules are controlled by the embedded soft core control module and are all slave modules of the embedded soft core control module, and further master-slave relationships exist among other modules.
The data stream conversion system of the second embodiment of the invention is optimized on the basis of the above embodiments, a perfect signaling interaction mechanism is established by defining preset message nodes, each group of modules with master-slave relation performs signaling forwarding and interaction in respective links, the interaction structure and specification of each module are defined, organized and precise signaling interaction between master and slave modules is realized, data stream conversion is completed under the condition that seamless, smooth and non-crash situations of a hardware system and a platform are ensured, meanwhile, the system has minimum effective system time delay on the premise of event driving, and the interaction reliability and efficiency are improved. The data stream conversion module completes data stream recombination and distribution on all lanes in the video image processing system in output modes of caching, grouping, output format conversion, time-sharing asynchronization/caching synchronization and the like for different data streams under the Lane number self-adaption and extensible application scene according to the indication of the data stream conversion signaling, thereby automatically and effectively completing the distribution of the data streams on all lanes according to different system requirements.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A data stream conversion system, comprising: the device comprises a first control module, a second control module and a data stream conversion module, wherein the second control module is respectively connected with the first control module and the data stream conversion module;
the first control module is used for initiating a data stream conversion request;
the second control module is configured to generate a data stream conversion signaling according to the data stream conversion request, and send the data stream conversion signaling to the data stream conversion module according to a preset message structure, where the preset message structure includes a data stream packet indication field and a channel number indication field for defining a maximum channel number;
and the data stream conversion module is used for grouping the cached data stream according to the data stream conversion signaling, converting the data stream into a preset format and generating feedback information aiming at the data stream conversion signaling.
2. The system of claim 1, wherein the data stream conversion module comprises:
the grouping submodule is used for determining the caching quantity of the data stream and grouping the cached data stream according to the data stream grouping indication field and the maximum channel number;
and the conversion submodule is used for converting the cached data stream into a preset bit width, changing the position of the data effective bit and extracting the data effective bit to obtain the data stream in a preset format.
3. The system of claim 2, wherein the data stream conversion module further comprises:
and the output submodule is used for synchronously outputting the data stream with the preset format or asynchronously outputting the data stream according to the channel serial number.
4. The system of claim 3, wherein the output submodule is specifically configured to:
if the number of the cached data streams is greater than or equal to the number of the channels, asynchronously outputting the data streams according to the channel serial numbers; otherwise, synchronously outputting the data stream with the preset format.
5. The system of claim 3, wherein the output submodule is specifically configured to:
if the pixel data width of the cached data stream is smaller than the pixel data width of the data stream on the channel, asynchronously outputting the data stream according to the channel serial number; otherwise, synchronously outputting the data stream with the preset format.
6. The system according to any one of claims 1-5, wherein the predetermined message structure further comprises: a master-slave module definition field and a feedback field;
the master-slave module definition field is used for defining a master module and a slave module in the data stream conversion module;
the feedback field is used for defining the module state after the data stream conversion signaling interaction is completed, and the module state comprises an affirmation state and a non-affirmation state.
7. The system of claim 6, wherein the predetermined message structure further comprises: a data stream buffer number indication field;
the data stream cache quantity indication field is used for indicating the quantity, the cache mode and the data stream operation mode of cached data streams, wherein the cache mode comprises line cache, field cache and clock cache, and the data stream operation mode comprises ping-pong operation, serial-parallel conversion operation, pipeline operation and data interface synchronization operation.
8. The system of claim 6, wherein the predetermined message structure further comprises: a format conversion indication field;
the format conversion indication field is used for defining bit width of the cached data stream, preset bit width, and address of a start bit and address of an end bit for extracting a valid bit of data.
9. The system of claim 6, wherein the predetermined message structure further comprises:
and the data stream output mode selection field is used for defining an output mode, and the output mode comprises synchronous output and asynchronous output according to the channel sequence number.
10. The system of claim 8, wherein the predetermined message structure further comprises: checking the field;
and the check field is used for checking the data stream conversion signaling according to a preset specification and indicating the interaction failure of the data stream conversion signaling when the check fails.
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