CN112701900A - Switch control circuit, system and switch control mechanical equipment - Google Patents
Switch control circuit, system and switch control mechanical equipment Download PDFInfo
- Publication number
- CN112701900A CN112701900A CN202011462880.6A CN202011462880A CN112701900A CN 112701900 A CN112701900 A CN 112701900A CN 202011462880 A CN202011462880 A CN 202011462880A CN 112701900 A CN112701900 A CN 112701900A
- Authority
- CN
- China
- Prior art keywords
- signal
- power
- control signal
- chip unit
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Electronic Switches (AREA)
Abstract
The invention discloses a switch control circuit, a switch control system and a switch control machine. The switch control circuit includes: the output end of the power switch module is used for outputting a first power control signal; the signal input end of the lower computer signal processing module is used for accessing a lower computer control signal, and the signal output end of the lower computer signal processing module is used for outputting a rising edge detection signal, wherein the rising edge detection signal is used for detecting whether the lower computer control signal jumps from a falling edge to a rising edge; the logic gate signal processing module outputs a second power supply control signal based on a first control signal of the upper computer, a second control signal of the upper computer, a rising edge detection signal and the first power supply control signal, wherein the second power supply control signal is used for controlling the power supply control system to be in a power-on state or a power-off state. The technical scheme provided by the embodiment of the invention reduces the control difficulty of power-on or power-off of the power supply control system of the switch control mechanical equipment.
Description
Technical Field
The embodiment of the invention relates to the technical field of automatic control, in particular to a switch control circuit, a switch control system and switch control mechanical equipment.
Background
Most existing switch control devices implement power-on or power-off of a power control system through a simple power switch module, which may be a mechanical switch.
The technical defect in the prior art is that when a technician is far away from a power switch module or is limited by the placement position of a switch control mechanical device and the technician cannot touch the power switch module, the control difficulty of power-on or power-off of a power control system of the switch control mechanical device is increased.
Disclosure of Invention
In view of this, embodiments of the present invention provide a switch control circuit, a switch control system, and a switch control mechanical device, so as to reduce the difficulty in controlling power-on or power-off of a power control system of the switch control mechanical device.
In a first aspect, an embodiment of the present invention provides a switch control circuit, including:
the power supply control system comprises a power supply switch module, a first control module and a second control module, wherein the output end of the power supply switch module is used for outputting a first power supply control signal, and the first power supply control signal is used for controlling a power supply control system to be in a power-on state or a power-off state;
a lower computer signal processing module, a signal input end of which is used for accessing a lower computer control signal, and a signal output end of which is used for outputting a rising edge detection signal, wherein the rising edge detection signal is used for detecting whether the lower computer control signal jumps from a falling edge to a rising edge;
a first signal input end of the logic gate signal processing module is used for accessing a first control signal of an upper computer, a second signal input end of the logic gate signal processing module is used for accessing a second control signal of the upper computer, a third signal input end of the logic gate signal processing module is electrically connected with a signal output end of the lower computer signal processing module, and a fourth signal input end of the logic gate signal processing module is electrically connected with an output end of the power switch module and is used for accessing the first power control signal;
the logic gate signal processing module outputs a second power supply control signal through a signal output end of the signal logic gate signal processing module based on the first control signal of the upper computer, the second control signal of the upper computer, the rising edge detection signal and the first power supply control signal, wherein the second power supply control signal is used for controlling the power supply control system to be in a power-on state or a power-off state.
In a second aspect, an embodiment of the present invention further provides a switch control system, including:
the upper computer is used for outputting a first control signal and a second control signal of the upper computer;
the lower computer is used for outputting a lower computer control signal;
a switch control circuit as described in any of the first aspects;
and a power supply signal input end of the power supply control system is electrically connected with the switch control circuit and is used for receiving a second power supply control signal output by the switch control circuit.
In a third aspect, an embodiment of the present invention further provides a switch control mechanical device, including the switch control system according to any of the second aspects.
In the technical scheme provided by the embodiment, the switch control circuit is based on a first control signal of an upper computer, a second control signal of the upper computer, a first power supply control signal and a rising edge detection signal, the second power supply control signal is output through the signal output end of the signal logic gate signal processing module, compared with the prior art that the power control system is controlled to be in the power-on state or the power-off state only by the first power control signal output by the power switch module, the second power control signal is used for controlling the power control system to be in the power-on state or the power-off state, so that the technical staff is prevented from being far away from the power switch module, or the technical personnel can not touch the power switch module and can not control the power control system to be in a power-on state or a power-off state due to the limitation of the placing position of the switch control equipment, and the control difficulty of the power-on or power-off of the power supply control system of the switch control mechanical equipment is further reduced.
Drawings
Fig. 1 is a schematic structural diagram of a switch control circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a switch control system according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another switch control circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another switch control system according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another switch control circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another switch control system according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a lower computer signal processing module according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, when a technician is far from the power switch module or is limited by the placement position of the switch control mechanical device, and the technician cannot touch the power switch module, the difficulty in controlling the power-on or power-off of the power control system of the switch control mechanical device is increased.
In view of the above technical problems, an embodiment of the present invention provides the following technical solutions:
fig. 1 is a schematic structural diagram of a switch control circuit according to an embodiment of the present invention. Fig. 2 is a schematic structural diagram of a switch control system according to an embodiment of the present invention. Referring to fig. 1 and 2, the switch control circuit 100 includes: the power switch module 10, an output end 10A of the power switch module 10 is configured to output a first power control signal C, where the first power control signal C is used to control the power control system 400 to be in a power-on state or a power-off state; a signal input end 20A of the lower computer signal processing module 20 is used for accessing a lower computer control signal, and a signal output end 20B of the lower computer signal processing module 20 is used for outputting a rising edge detection signal D, where the rising edge detection signal D is used for detecting whether the lower computer control signal jumps from a falling edge to a rising edge; a logic gate signal processing module 30, a first signal input end 30A of the logic gate signal processing module 30 is used for accessing a first control signal a of an upper computer, a second signal input end 30B of the logic gate signal processing module 30 is used for accessing a second control signal B of the upper computer, a third signal input end 30C of the logic gate signal processing module 30 is electrically connected with a signal output end 20B of the lower computer signal processing module 20, and a fourth signal input end 30D of the logic gate signal processing module 30 is electrically connected with an output end 10A of the power switch module 10 and is used for accessing a first power control signal C; the logic gate signal processing module 30 outputs a second power control signal Y through a signal output end 30E of the signal logic gate signal processing module 30 based on a first control signal a of the upper computer, a second control signal B of the upper computer, a first power control signal C, and a rising edge detection signal D, wherein the second power control signal Y is used for controlling the power control system 400 to be in a power-on state or a power-off state.
Optionally, the power switch module 10 includes mechanical buttons including an upper electronic button and a lower electronic button. The output end of the upper electronic button is used for sending an upper control signal, the output end of the lower electronic button is used for outputting a lower control signal, the upper control signal and the lower control signal form a first power control signal C, and the first power control signal C is used for controlling the power control system 400 to be in a power-on state or a power-off state.
In the technical solution provided in this embodiment, the switch control circuit 100 outputs the second power control signal Y through the signal output end 30E of the signal logic gate signal processing module 30 based on the first control signal a of the upper computer, the second control signal B of the upper computer, the first power control signal C, and the rising edge detection signal D, where the second power control signal Y is used to control the power control system 400 to be in the power-on state or the power-off state, compared with the prior art that the power control system 400 is controlled to be in the power-on state or the power-off state only through the first power control signal C output by the power switch module 10, the problem that when a technician is far away from the power switch module 10 or is limited by the placement position of the switch control device, the technician cannot touch the power switch module 10 and cannot control the power control system 400 to be in the power-on state or the power-off state is, and further, the control difficulty of powering on or powering off the power control system 400 of the switch control mechanical device is reduced.
In the following, further detailed, the second power control signal Y has a logical relationship with the first control signal a of the upper computer, the second control signal B of the upper computer, the first power control signal C, and the rising edge detection signal D. On the basis of the above technical solution, the second power control signal Y satisfies the logical relationship shown in equation (1):
Y＝((A′C+A′B+BC)D)′ (1)
wherein, a is a first control signal of the upper computer, a ' is an inverse signal of the first control signal a of the upper computer, B is a second control signal of the upper computer, C is a first power control signal, D is a rising edge detection signal, and the second power control signal Y is an inverse signal of the control signal represented by ((a ' C + a ' B + BC) D).
Tables 1 and 2 show truth tables of the second power control signal Y, the first control signal a of the upper computer, the second control signal B of the upper computer, the first power control signal C and the rising edge detection signal D, and corresponding power-on states and power-off states of the power control system, which conform to equation (1). For example, "0" in tables 1 and 2 represents a low level signal, and "1" represents a high level signal. According to the logical relation shown in formula (1), the switch control circuit 100 can implement the following technical scheme based on the upper computer first control signal a, the upper computer second control signal B, the first power supply control signal C and the rising edge detection signal D:
it should be noted that the first control signal a of the upper computer and the second control signal B of the upper computer are both high-level signals or both low-level signals and are regarded as initial states of the first control signal a of the upper computer and the second control signal B of the upper computer; the initial state of the first power control signal C is a low level signal; the initial state of the lower computer control signal is a low level signal, and the signal output end 20B of the lower computer signal processing module 20 outputs a rising edge detection signal D, where the rising edge detection signal D is a high level signal; when the lower computer control signal jumps from the falling edge to the rising edge, the lower computer signal processing module 20 outputs a rising edge detection signal D, where the rising edge detection signal D is a low-level signal, and the above technical solution realizes a function that the lower computer signal processing module 20 is used to detect whether the lower computer control signal jumps from the falling edge to the rising edge, that is, when the lower computer control signal jumps from the falling edge to the rising edge, the lower computer signal processing module 20 locks the output rising edge detection signal D as a low-level signal.
The first scheme is as follows: when the first control signal a of the upper computer, the second control signal B of the upper computer, and the first power control signal C are all low level signals, the rising edge detection signal D is a high level signal, that is, the first control signal a of the upper computer, the second control signal B of the upper computer, the first power control signal C, and the control signal of the lower computer are all in an initial state, and at this time, the second power control signal Y is a high level signal, and the power control system 400 is in an initial state.
Scheme II: when the first control signal a of the upper computer and the second control signal B of the upper computer are both low level signals, the first power control signal C is a high level signal, and the rising edge detection signal D is a high level signal, that is, the first control signal a of the upper computer, the second control signal B of the upper computer and the control signal of the lower computer are all in an initial state, because the first power control signal C is triggered, the second power control signal Y is made to be a low level signal, the first power control signal C controls the power control system 400 to be in a power-on state, that is, the power switch module 10 controls the power control system 400 to be in a power-on state.
The third scheme is as follows: when the first control signal a of the upper computer is a low level signal, the second control signal B of the upper computer is a high level signal, the first power control signal C is a low level signal, and the rising edge detection signal D is a high level signal, that is, the first power control signal C and the lower computer control signal are both in an initial state, and the second power control signal Y is made to be a low level signal due to the state change of the first control signal a of the upper computer and the second control signal B of the upper computer, so that the first control signal a of the upper computer and the second control signal B of the upper computer control the power control system 400 to be in a power-on state, that is, the upper computer 200 controls the power control system 400 to be in the power-on state.
And the scheme is as follows: when the first control signal a of the upper computer is a low level signal, the second control signal B of the upper computer is a high level signal, the first power control signal C is a high level signal, and the rising edge detection signal D is a high level signal, that is, the control signal of the lower computer is in an initial state, because the states of the first control signal a of the upper computer, the second control signal B of the upper computer and the first power control signal C are changed, the second power control signal Y is made to be a low level signal, so that the first control signal a of the upper computer, the second control signal B of the upper computer and the first power control signal C control the power control system 400 to be in a power-on state, that is, the upper computer 200 and the power switch module 10 control the power control system 400 to be in a power-on state.
And a fifth scheme: when the first control signal a of the upper computer is a high level signal, the second control signal B of the upper computer is a high level signal, the first power control signal C is a high level signal, and the rising edge detection signal D is a high level signal, that is, the first control signal a of the upper computer, the second control signal B of the upper computer, and the control signal of the lower computer are all in an initial state, and the second power control signal Y is a low level signal due to the state change of the first power control signal C, so that the first power control signal C controls the power control system 400 to be in a power-on state, that is, the power switch module 10 controls the power control system 400 to be in the power-on state.
Scheme six: when the first control signal a of the upper computer is a high level signal, the second control signal B of the upper computer is a low level signal, the first power control signal C is a low level signal, and the rising edge detection signal D is a high level signal, that is, the control signal of the lower computer is in an initial state, because the states of the first control signal a of the upper computer, the second control signal B of the upper computer and the first power control signal C are changed, the second power control signal Y is made to be a high level signal, so that the first control signal a of the upper computer and the second control signal B of the upper computer control the power control system 400 to be in a power-off state, that is, the upper computer 200 and the power switch module 10 control the power control system 400 to be in the power-off state.
The scheme is seven: when the first control signal a of the upper computer is a high level signal, the second control signal B of the upper computer is a low level signal, the first power control signal C is a high level signal, and the rising edge detection signal D is a high level signal, that is, the first power control signal C and the lower computer control signal are in an initial state, and the second power control signal Y is caused to be a high level signal due to the state change of the first control signal a of the upper computer and the second control signal B of the upper computer, so that the first control signal a of the upper computer and the second control signal B of the upper computer control the power control system 400 to be in a power-off state, that is, the upper computer 200 controls the power control system 400 to be in the power-off state.
And the eighth scheme is as follows: when the first control signal a of the upper computer is a high level signal, the second control signal B of the upper computer is a high level signal, the first power control signal C is a low level signal, and the rising edge detection signal D is a high level signal, that is, the first control signal a of the upper computer, the second control signal B of the upper computer and the control signal of the lower computer are in an initial state, and the second power control signal Y is a high level signal due to the state change of the first power control signal C, so that the first power control signal C controls the power control system 400 to be in a power-off state, that is, the upper computer 200 controls the power control system 400 to be in a power-off state.
The scheme is nine: the lower computer control signal jumps from a falling edge to a rising edge, the rising edge detection signal D is a low level signal, and at this time, no matter whether the upper computer first control signal a, the upper computer second control signal B, and the first power control signal C are in an initial state, the second power control signal Y is a high level signal, so the lower computer control signal controls the power control system 400 to be in a power-off state, so that when the lower computer control signal jumps from the falling edge to the rising edge, the lower computer signal processing module 20 locks the output rising edge detection signal D to be the low level signal, and the lower computer 300 controls the power control system 400 to be in the power-off state. It should be noted that, at this time, the control of powering on or powering off the power control system 400 can be restarted only by powering on the lower computer 300 again.
Table 1 truth table and power control system state correspondence table 1
Table 2 truth table and power control system state correspondence table 2
Fig. 3 is a schematic structural diagram of another switch control circuit according to an embodiment of the present invention. Fig. 4 is a schematic structural diagram of another switch control system according to an embodiment of the present invention. On the basis of the above technical solution, the logic gate signal processing module 30 is further refined, and referring to fig. 3 and 4, the logic gate signal processing module 30 includes: a first not gate chip unit 31, an and gate chip unit 32, or a gate chip unit 33 and a second not gate chip unit 34. The signal input end 31A of the first not gate chip unit 31 is used for accessing a first control signal a of an upper computer, and the signal output end 31B of the first not gate chip unit 31 is used for outputting a first inverted signal a ', wherein the first inverted signal a' is an inverted signal of the first control signal a of the upper computer.
A first signal input end 32A of the and-gate chip unit 32 is electrically connected to a signal output end 31B of the first not-gate chip unit 31, a second signal input end 32B of the and-gate chip unit 32 is used for accessing a second control signal B of the upper computer, the and-gate chip unit 32 outputs a first logical and signal (a 'B) through a first signal output end 32C of the and-gate chip unit 32 based on the first inverse signal a' and the second control signal B of the upper computer, wherein the first logical and signal (a 'B) is a logical and signal of the first inverse signal a' and the second control signal B of the upper computer.
The third signal input end 32D of the and-gate chip unit 32 is electrically connected to the signal output end 31B of the first not-gate chip unit 31, the fourth signal input end 32E of the and-gate chip unit 32 is electrically connected to the output end 10A of the power switch module 10, and the and-gate chip unit 32 outputs a second logical and signal (a ' C) through the second signal output end 32F of the and-gate chip unit 32 based on the first inverted signal a ' and the first power control signal C, where the second logical and signal (a ' C) is an inverted signal of the first control signal a of the upper computer and a logical and signal of the first power control signal C.
A fifth signal input end 32G of the and gate chip unit 32 is connected to the second control signal B of the upper computer, a sixth signal input end 32H of the and gate chip unit 32 is electrically connected to an output end 10A of the power switch module 10, the and gate chip unit 32 outputs a third logic and signal (BC) through a third signal output end 32I of the and gate chip unit 32 based on the second control signal B of the upper computer and the first power control signal C, wherein the third logic and signal (BC) is a logic and signal of the second control signal B of the upper computer and the first power control signal C of the upper computer.
The first signal input end 33A of the or gate chip unit 33 is electrically connected to the first signal output end 32C of the and gate chip unit 32, the second signal input end 33B of the or gate chip unit 33 is electrically connected to the second signal output end 32F of the and gate chip unit 32, the third signal input end 33C of the or gate chip unit 33 is electrically connected to the third signal output end 32I of the and gate chip unit 32, or the or gate chip unit 33 outputs a logical or signal (a 'C + a' B + BC) through the signal output end 33D of the or gate chip unit 33 based on the first logical and signal (a 'B), the second logical and signal (a' C), and the third logical and signal (BC), wherein the logical or signal is a logical or signal of the first logical and signal (a 'B), the second logical and signal (a' C), and the third logical and signal (BC).
The seventh signal input terminal 32J of the and-gate chip unit 32 is electrically connected to the signal output terminal 33D of the or-gate chip unit 33, the eighth signal input terminal 32K of the and-gate chip unit 32 is electrically connected to the signal output terminal 20A of the lower computer signal processing module 20, and the and-gate chip unit 32 outputs a fourth logical and signal ((a 'C + a' B + BC) D) through the fourth signal output terminal 32L of the and-gate chip unit 32 based on the logical or signal (a 'C + a' B + BC) and the rising edge detection signal D, where the fourth logical and signal ((a 'C + a' B + BC) D) is a logical or signal (a 'C + a' B + BC) D)′C+A′B + BC) and the rising edge detection signal D.
The first signal input terminal 34A of the second not gate chip unit 34 is electrically connected to the fourth signal output terminal 32L of the and gate chip unit 32, and the second not gate chip unit 34 outputs a second inverted signal ((a ' C + a ' B + BC) D) ' based on the fourth logical and signal ((a ' C + a ' B + BC) D) through the signal output terminal 34B of the second not gate chip unit 34, wherein the second inverted signal ((a ' C + a ' B + BC) D) ' is an inverted signal of the fourth logical and signal ((a ' C + a ' B + BC) D), and the second inverted signal ((a ' C + a ' B + BC) D) ' is the second power control signal Y.
Specifically, a first control signal A of an upper computer, a second control signal B of the upper computer, a first power control signal C and a rising edge detection signal D are converted into a second power control signal Y through a first NOT gate chip unit 31, a second NOT gate chip unit 34, an AND gate chip unit 32 and/or a gate chip unit 33, the power switch module 10 controls the power control system 400 to be in the power-on state, the upper computer 200 and the power switch module 10 control the power control system 400 to be in the power-on state, the upper computer 200 and the power switch module 10 control the power control system 400 to be in the power-off state, the upper computer 200 controls the power control system 400 to be in the power-off state, and the lower computer 300 controls the power control system 400 to be in the power-off state. Compared with the prior art, the power control system 400 is controlled to be in the power-on state or the power-off state only through the first power control signal C output by the power switch module 10, so that the problem that the power control system 400 cannot be controlled to be in the power-on state or the power-off state because a technician cannot touch the power switch module 10 when the technician is far away from the power switch module 10 or is limited by the placement position of the switch control equipment is solved, and the control difficulty of power-on or power-off of the power control system 400 of the switch control mechanical equipment is further reduced.
Fig. 5 is a schematic structural diagram of another switch control circuit according to an embodiment of the present invention; fig. 6 is a schematic structural diagram of another switch control system according to an embodiment of the present invention. In order to facilitate the communication connection between the upper computer 200 and the switch control circuit 100, referring to fig. 5 and 6, the switch control circuit 100 further includes a communication module 40, a first signal input end 40A of the communication module 40 is used for accessing a first control signal of the upper computer, and a second signal input end 40B of the communication module 40 is used for accessing a second control signal of the upper computer; the first signal input terminal 30A of the logic gate signal processing module 30 is electrically connected to the first signal output terminal 40C of the communication module 40, and the second signal input terminal 30B of the logic gate signal processing module 30 is electrically connected to the second signal output terminal 40D of the communication module 40.
Specifically, the communication module 40 implements a communication connection between the upper computer 200 and the switch control circuit 100. Specifically describing the specific structure of the communication module 40, on the basis of the above technical solution, referring to fig. 3 to fig. 6, the communication module 40 includes a USB interface 41 and a USB-to-general I/O port 42; a first signal input end 41A of the USB interface 41 is used for accessing a first control signal of an upper computer, and a second signal input end 41B of the USB interface 41 is used for accessing a second control signal of the upper computer; a first signal input end 42A of the USB to general purpose I/O port 42 is electrically connected to a first signal output end 41C of the USB interface 41, a second signal input end 42B of the USB to general purpose I/O port 42 is electrically connected to a second signal output end 41D of the USB interface 41, a first signal input end 30A of the logic gate signal processing module 30 is electrically connected to the first signal output end 42C of the USB to general purpose I/O port 42, and a second signal input end 30B of the logic gate signal processing module 30 is electrically connected to the second signal output end 42D of the USB to general purpose I/O port 42.
Specifically, the USB interface 41 and the USB to general I/O port 42 also have the effect of reducing the circuit cost on the basis of realizing the communication connection between the upper computer 200 and the switch control circuit 100.
The specific process of the lower computer signal processing module 20 for detecting whether the lower computer control signal jumps from the falling edge to the rising edge is described in detail below. Fig. 7 is a schematic structural diagram of a lower computer signal processing module according to an embodiment of the present invention. On the basis of the above technical solution, referring to fig. 7, the lower computer signal processing module 20 includes a latch 21, a transistor Q1, and a first power supply 22; the signal input end 21A of the latch 21 is used for accessing a lower computer control signal; a control terminal of the transistor Q1 is electrically connected to the signal output terminal 21B of the latch 21, a first terminal of the transistor Q1 is electrically connected to the first power supply 22, a second terminal of the transistor Q1 is grounded, and a first terminal of the transistor Q1 is configured to output a rising edge detection signal D; the third signal input terminal 30C of the logic gate signal processing module 30 is electrically connected to the first terminal of the transistor Q1.
Specifically, the lower computer control signal is a low level signal, the transistor Q1 is in an off state, and the first end of the transistor Q1 outputs a rising edge detection signal D, where the rising edge detection signal D is a high level signal; when the lower computer control signal jumps from a falling edge to a rising edge, the transistor Q1 is in a conducting state, and the first terminal of the transistor Q1 outputs a rising edge detection signal D, wherein the rising edge detection signal D is a low level signal. Optionally, a first resistor R1 is located between the first power supply 22 and the first terminal of the transistor Q1 for limiting current. The first end of the second resistor R2 is electrically connected to the control terminal of the transistor Q1, and the second end of the second resistor R2 is grounded and used as a pull-down resistor, so as to prevent the control terminal of the transistor Q1 from having an excessive current.
On the basis of the above technical solution, the transistor Q1 includes an NMOS transistor, a gate of the NMOS transistor is electrically connected to the signal output terminal 21B of the latch 21, a drain of the NMOS transistor is electrically connected to the first power supply 22, and a source of the NMOS transistor is grounded. The specific lower computer control signal is a low level signal, the NMOS tube is in a cut-off state, and a drain electrode of the NMOS tube outputs a rising edge detection signal D, wherein the rising edge detection signal D is a high level signal; when the control signal of the lower computer jumps from a falling edge to a rising edge, the NMOS tube is in a conducting state, and the drain electrode of the NMOS tube outputs a rising edge detection signal D, wherein the rising edge detection signal D is a low level signal. Optionally, the lower computer signal processing module 20 further includes a diode 23, an anode of the diode 23 is electrically connected to the second terminal of the transistor Q1, a cathode of the diode 23 is electrically connected to the first terminal of the transistor Q1, and the diode 23 is configured to prevent the transistor Q1 from being broken down by a reverse electromotive force generated by an inductive load when the first terminal and the second terminal of the transistor Q1 are connected to the inductive load.
The embodiment of the invention also provides a switch control system. Referring to fig. 2, 4 and 6, the switch control system includes: the upper computer 200 is used for outputting an upper computer first control signal A and an upper computer second control signal B, and the upper computer 200 is used for outputting a first control signal A and a second control signal B; the lower computer 300, the lower computer 300 is used for outputting the lower computer control signal; a switch control circuit 100, the switch control circuit 100 being any of the switch control circuits described in the above-mentioned embodiments; in the power control system 400, a power signal input terminal of the power control system 400 is electrically connected to the switch control circuit 100, and is configured to receive the second power control signal Y output by the switch control circuit 100.
On the basis of the above technical solution, referring to fig. 4 and fig. 6, the switch control system may further include a power-on or power-off indicator 500, when the second power control signal Y controls the power control system 400 to be powered on, the power-on or power-off indicator 500 is in a lighting state, when the second power control signal Y controls the power control system 400 to be powered off, the power-on or power-off indicator 500 is in a dark state, and the power-on or power-off indicator 500 may clearly indicate the power-on state and the power-off state of the power control system 400.
The switch control system provided in this embodiment includes the switch control circuit in the above technical solution, so the switch control system provided in this embodiment of the present invention also has the beneficial effects described in the above embodiments, and details are not described here.
The embodiment of the invention also provides switch control mechanical equipment which comprises the switch control system in any technical scheme. The switch control mechanical device provided in this embodiment includes the switch control system in the above technical solution, so the switch control mechanical device provided in the embodiment of the present invention also has the beneficial effects described in the above embodiments, and details are not described here.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A switch control circuit, comprising:
the power supply control system comprises a power supply switch module, a first control module and a second control module, wherein the output end of the power supply switch module is used for outputting a first power supply control signal, and the first power supply control signal is used for controlling a power supply control system to be in a power-on state or a power-off state;
a lower computer signal processing module, a signal input end of which is used for accessing a lower computer control signal, and a signal output end of which is used for outputting a rising edge detection signal, wherein the rising edge detection signal is used for detecting whether the lower computer control signal jumps from a falling edge to a rising edge;
a first signal input end of the logic gate signal processing module is used for accessing a first control signal of an upper computer, a second signal input end of the logic gate signal processing module is used for accessing a second control signal of the upper computer, a third signal input end of the logic gate signal processing module is electrically connected with a signal output end of the lower computer signal processing module, and a fourth signal input end of the logic gate signal processing module is electrically connected with an output end of the power switch module and is used for accessing the first power control signal;
the logic gate signal processing module outputs a second power supply control signal through a signal output end of the signal logic gate signal processing module based on the first control signal of the upper computer, the second control signal of the upper computer, the rising edge detection signal and the first power supply control signal, wherein the second power supply control signal is used for controlling the power supply control system to be in a power-on state or a power-off state.
2. The switch control circuit of claim 1, wherein the second power control signal Y satisfies the following logical relationship:
Y=((A′C+A′B+BC)D)′
wherein, a is the first control signal of the upper computer, a ' is the inverse signal of the first control signal of the upper computer, B is the second control signal of the upper computer, C is the first power control signal, D is the rising edge detection signal, and the second power control signal Y is the inverse signal of the control signal represented by ((a ' C + a ' B + BC) D).
3. The switch control circuit according to claim 1, wherein the logic gate signal processing module comprises a first not gate chip unit, a second not gate chip unit, an and gate chip unit and an or gate chip unit;
the signal input end of the first NOT gate chip unit is used for accessing a first control signal of the upper computer, and the signal output end of the first NOT gate chip unit is used for outputting a first inverted signal, wherein the first inverted signal is the inverted signal of the first control signal of the upper computer;
a first signal input end of the AND gate chip unit is electrically connected with a signal output end of the first NOT gate chip unit, a second signal input end of the AND gate chip unit is used for accessing a second control signal of the upper computer, and the AND gate chip unit outputs a first logical AND signal through a first signal output end of the AND gate chip unit based on the first inverted signal and the second control signal of the upper computer, wherein the first logical AND signal is a logical AND signal of the first inverted signal and the second control signal of the upper computer;
a third signal input end of the and-gate chip unit is electrically connected with a signal output end of the first not-gate chip unit, a fourth signal input end of the and-gate chip unit is electrically connected with an output end of the power switch module, the and-gate chip unit outputs a second logical and signal through a second signal output end of the and-gate chip unit based on the first inverted signal and the first power control signal, wherein the second logical and signal is an inverted signal of the first control signal of the upper computer and a logical and signal of the first power control signal;
a fifth signal input end of the and-gate chip unit is connected with the second control signal of the upper computer, a sixth signal input end of the and-gate chip unit is electrically connected with an output end of the power switch module and is connected with the second control signal of the upper computer, the and-gate chip unit outputs a third logical and signal through a third signal output end of the and-gate chip unit based on the second control signal of the upper computer and the first power control signal, wherein the third logical and signal is the logical and signal of the second control signal of the upper computer and the first power control signal;
a first signal input end of the or gate chip unit is electrically connected with a first signal output end of the and gate chip unit, a second signal input end of the or gate chip unit is electrically connected with a second signal output end of the and gate chip unit, a third signal input end of the or gate chip unit is electrically connected with a third signal output end of the and gate chip unit, and the or gate chip unit outputs a logic or signal through a signal output end of the or gate chip unit based on the first logic and signal, the second logic and signal and the third logic and signal, wherein the logic or signal is a logic or signal of the first logic and signal, the second logic and signal and the third logic and signal;
a seventh signal input end of the and gate chip unit is electrically connected with a signal output end of the or gate chip unit, an eighth signal input end of the and gate chip unit is electrically connected with a signal output end of the lower computer signal processing module, the and gate chip unit outputs a fourth logical and signal through a fourth signal output end of the and gate chip unit based on the logical or signal and the rising edge detection signal, wherein the fourth logical and signal is a logical and signal of the logical or signal and the rising edge detection signal;
and a first signal input end of the second not gate chip unit is electrically connected with a fourth signal output end of the and gate chip unit, and the second not gate chip unit outputs a second inverted signal through a signal output end of the second not gate chip unit based on the fourth logic and signal, wherein the second inverted signal is an inverted signal of the fourth logic and signal, and the second inverted signal is the second power control signal.
4. The switch control circuit according to claim 1, further comprising a communication module, wherein a first signal input end of the communication module is used for accessing the first control signal of the upper computer, and a second signal input end of the communication module is used for accessing the second control signal of the upper computer;
and a first signal input end of the logic gate signal processing module is electrically connected with a first signal output end of the communication module, and a second signal input end of the logic gate signal processing module is electrically connected with a second signal output end of the communication module.
5. The switch control circuit of claim 4, wherein the communication module comprises a USB interface and a USB to universal I/O port;
the first signal input end of the USB interface is used for accessing a first control signal of the upper computer, and the second signal input end of the USB interface is used for accessing a second control signal of the upper computer;
the first signal input end of the USB-to-universal I/O port is electrically connected with the first signal output end of the USB interface, the second signal input end of the USB-to-universal I/O port is electrically connected with the second signal output end of the USB interface, the first signal input end of the logic gate signal processing module is electrically connected with the first signal output end of the USB-to-universal I/O port, and the second signal input end of the logic gate signal processing module is electrically connected with the second signal output end of the USB-to-universal I/O port.
6. The switch control circuit according to claim 1, wherein the lower computer signal processing module comprises a latch, a transistor and a first power supply;
the signal input end of the latch is used for accessing the lower computer control signal;
the control end of the transistor is electrically connected with the signal output end of the latch, the first end of the transistor is electrically connected with the first power supply, the second end of the transistor is grounded, and the first end of the transistor is used for outputting the rising edge detection signal;
and the third signal input end of the logic gate signal processing module is electrically connected with the first end of the transistor.
7. The switch control circuit of claim 6, wherein the transistor comprises an NMOS transistor, a gate of the NMOS transistor is electrically connected to the signal output terminal of the latch, a drain of the NMOS transistor is electrically connected to the first power supply, and a source of the NMOS transistor is grounded.
8. The switch control circuit of claim 1, wherein the power switch module includes mechanical buttons including an upper electronic button and a lower electronic button.
9. A switch control system, comprising:
the upper computer is used for outputting a first control signal and a second control signal of the upper computer;
the lower computer is used for outputting a lower computer control signal;
a switch control circuit as claimed in any one of claims 1 to 8;
and a power supply signal input end of the power supply control system is electrically connected with the switch control circuit and is used for receiving a second power supply control signal output by the switch control circuit.
10. A switch control mechanism comprising a switch control system according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011462880.6A CN112701900B (en) | 2020-12-11 | 2020-12-11 | Switch control circuit, system and switch control mechanical equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011462880.6A CN112701900B (en) | 2020-12-11 | 2020-12-11 | Switch control circuit, system and switch control mechanical equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112701900A true CN112701900A (en) | 2021-04-23 |
| CN112701900B CN112701900B (en) | 2022-03-11 |
Family
ID=75507316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011462880.6A Active CN112701900B (en) | 2020-12-11 | 2020-12-11 | Switch control circuit, system and switch control mechanical equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112701900B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202307738U (en) * | 2011-10-19 | 2012-07-04 | 深圳市龙电电气有限公司 | Remote controllable current breaker |
| CN206833289U (en) * | 2017-05-27 | 2018-01-02 | 上海一诺仪表有限公司 | A kind of slave computer |
| US20180356814A1 (en) * | 2016-04-25 | 2018-12-13 | General Electric Company | Remote vehicle operator assignment system |
-
2020
- 2020-12-11 CN CN202011462880.6A patent/CN112701900B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202307738U (en) * | 2011-10-19 | 2012-07-04 | 深圳市龙电电气有限公司 | Remote controllable current breaker |
| US20180356814A1 (en) * | 2016-04-25 | 2018-12-13 | General Electric Company | Remote vehicle operator assignment system |
| CN206833289U (en) * | 2017-05-27 | 2018-01-02 | 上海一诺仪表有限公司 | A kind of slave computer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112701900B (en) | 2022-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8253530B2 (en) | Keyboard for powering on or off computer | |
| CN107658916B (en) | Prompting circuit and electronic equipment | |
| US20120131243A1 (en) | Multiplexing pin control circuit for computer system | |
| CN201302715Y (en) | Device for computers | |
| US7615946B2 (en) | Fan speed control device | |
| US8200997B2 (en) | Computer wake up circuit includes a switch configured to prevent a control signals from an I/O controller being transmitted to south-bridge | |
| CN210804388U (en) | Hot plug detection circuit and electronic equipment | |
| CN112701900B (en) | Switch control circuit, system and switch control mechanical equipment | |
| CN110703892A (en) | EC reset circuit and electronic equipment based on USB C type interface | |
| TW201312342A (en) | Computer, motherboard and test card | |
| CN110275852B (en) | Electronic device and hot plug protection circuit | |
| US8319438B2 (en) | Circuit for detecting computer states | |
| US20150054669A1 (en) | Encoder input device | |
| TW201305811A (en) | Indication circuit for electronic devices | |
| KR101237424B1 (en) | Computer comprising non-limited current USB connector | |
| CN112953221B (en) | Voltage conversion device | |
| JP2016099994A (en) | Power supply adjustment circuit and all-in-one personal computer having power supply adjustment circuit | |
| CN214069905U (en) | Multi-power-supply chip control circuit and electronic equipment | |
| CN211702477U (en) | Wireless weak current dry contact adapter | |
| CN109979405B (en) | Time sequence control circuit and display device | |
| CN104881340B (en) | Electronic device | |
| US20070091534A1 (en) | Control circuit for relay | |
| CN110690883A (en) | EC reset circuit and electronic equipment based on composite signal | |
| CN108572891A (en) | Video card connects cue circuit | |
| CN110688260B (en) | EC reset circuit and electronic equipment based on earphone interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |