CN112701044A - Strained germanium channel transistor and method of making the same - Google Patents
Strained germanium channel transistor and method of making the same Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
The invention provides a strained germanium channel transistor and a preparation method thereof, wherein the preparation method of the strained germanium channel transistor comprises the following steps: providing a germanium substrate, depositing a sacrificial layer on the germanium substrate, and selectively etching off part of the sacrificial layer; carrying out inert gas atom doping and thermal annealing treatment on the germanium substrate region with part of the sacrificial layer etched away; carrying out p-type doping again in the germanium substrate area doped and annealed by the inert atoms to form a source region and a drain region of the germanium PMOS device; etching the rest sacrificial layer and depositing an isolation layer, and selectively etching the isolation layer to form a gate region between a source region and a drain region of the germanium PMOS device; oxidizing the grid region, depositing a dielectric layer on the surfaces of the isolation layer and the grid region and selectively etching to expose the source region and the drain region; and manufacturing a gate electrode, a source electrode, a drain electrode and a back electrode of the germanium PMOS device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a novel strain germanium channel germanium transistor and a preparation method thereof, which are used for improving the performance of the germanium transistor.
Background
Silicon microelectronics uses CMOS (complementary metal oxide semiconductor) technology, i.e. the channel carrier transport characteristics of which directly determine the performance of the whole chip, by pairing NMOS and PMOS to form the basic unit of a digital integrated circuit. After the integrated circuit enters the 7nm technology node, the size of a single transistor gradually reaches the double limits of physics and technology, and particularly the carrier transmission performance of a silicon PMOS channel under the extremely small size is seriously influenced, so that the Moore's law is about to fail. Developing new channel materials with high mobility or adopting new processes and new technologies to improve the channel hole mobility becomes an important means for continuing moore's law.
One method that has received much attention and found widespread use is the strained channel technique, i.e., the band structure of the device is modulated by applying stress to the channel, thereby reducing the effective mass of carriers and increasing the carrier mobility of the channel. Since germanium materials compatible with silicon processes have the highest carrier mobility among all semiconductor materials, the carrier mobility enhancement of germanium materials under strained conditions is more significant. Therefore, as silicon scaling technology approaches its limits, the development of high performance strained germanium channel technology has become a critical breakthrough in continuation of moore's law.
Early strain channel technologies, such as silicon capping, lateral isolation, stress memorization, etc., developed primarily utilized the 4.2% lattice difference between silicon and germanium, which has limited strain strength and difficult process integration. After the junction point of 45/32nm is entered, an embedded germanium tin source-drain (GeSn S/D) strain technology is developed, and the improvement of the performance of the germanium transistor is greatly improved due to the larger strain intensity. The core idea of the strain technology is that GeSn alloy is filled in a source region and a drain region of a germanium PMOS (P-channel metal oxide semiconductor) by adopting a selective epitaxy technology, and a device channel is compressed by a larger lattice constant of the GeSn alloy to generate transverse compressive strain, so that the hole mobility of the channel is improved. However, due to the channel impurity scattering and interface roughness scattering, the hole mobility of the strained germanium PMOS channel fabricated by this technique still cannot reach 1/3 of the germanium material. In addition, since the equilibrium solid solubility of Sn in germanium is very low (< 1%), the Sn content should be not less than 8% in order to generate a compressive strain of sufficient strength, and the ultra-high concentration of Sn atoms tends to form a cluster structure during high temperature annealing. Meanwhile, as the electrically activated Sn atoms are positioned in germanium crystal lattice substitution positions, the larger atom size of the Sn atoms can also generate lattice mismatch in a source-drain region to form a large number of lattice defects. The cluster structure and the lattice defects not only can enhance hole scattering and reduce the ohmic contact characteristic of a source electrode and a drain electrode, but also can improve the risk of junction current of the source electrode and the drain electrode, thereby reducing the driving current of the germanium PMOS.
Further studies have shown that, due to the low formation energy of boron (B) atoms, B atoms preferentially replace Sn to form GeSn when GeSn in-situ growth and heat treatment are performed: the further reduction in the concentration of Sn atoms at the sites of the B alloy also leads to strain degradation in the device channel. In summary, the existing GeSn S/D strain technology still has higher process requirements and technical difficulties, and the adoption of the scheme for preparing the planar strained germanium transistor faces a lot of obstacles and challenges, and it is not feasible to further improve the performance of the germanium transistor under the deep nano technology node.
Disclosure of Invention
In view of the above, in order to solve the problems of high source-drain region defect content, large carrier scattering, high junction current risk, strain degradation and the like of the conventional planar strained germanium transistor, the invention provides a method for manufacturing a strained germanium channel transistor, so as to solve at least one of the above technical problems.
In order to achieve the above object, the present invention provides a strained germanium channel transistor and a method for manufacturing the same, wherein in one aspect, the present invention provides a method for manufacturing a strained germanium channel transistor, comprising: providing a germanium substrate, depositing a sacrificial layer on the germanium substrate, and selectively etching off part of the sacrificial layer; carrying out inert gas atom doping and thermal annealing treatment on the germanium substrate region with part of the sacrificial layer etched away; carrying out p-type doping on the germanium substrate area subjected to inert gas atom doping and thermal annealing treatment to form a source area and a drain area of the germanium PMOS device; etching the rest sacrificial layer and depositing an isolation layer, and selectively etching the isolation layer to form a gate region between a source region and a drain region of the germanium PMOS device; oxidizing the grid region, depositing a dielectric layer on the surfaces of the isolation layer and the grid region and selectively etching to expose the source region and the drain region; and manufacturing a gate electrode, a source electrode, a drain electrode and a back electrode of the germanium PMOS device.
According to an embodiment of the present invention, wherein the germanium substrate is an n-type three-dimensional periodic bulk material or a GOI substrate material.
According to an embodiment of the invention, wherein the inert gas atoms comprise at least one of: helium (He), neon (Ne), argon (Ar); the p-type doping atoms are boron atoms.
According to the embodiment of the invention, the inert gas atom doping is gap doping, and the doping concentration is more than or equal to 1% of the atomic number of the germanium substrate;
the thermal annealing adopts pulse laser annealing or flash lamp annealing; the lattice constant of the source region and the drain region is larger than the natural lattice constant of the germanium substrate.
According to an embodiment of the present invention, wherein the channel of the germanium PMOS device is provided with a compressive strain in a direction parallel to the source and drain.
According to the embodiment of the invention, the method for depositing the sacrificial layer, the isolation layer and the dielectric layer by inert gas atom doping by adopting an ion implantation technology comprises the following steps: plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atomic layer deposition, magnetron sputtering.
According to the embodiment of the invention, the sacrificial layer is silicon dioxide, the isolation layer is silicon nitride, and the dielectric layer is hafnium dioxide or silicon dioxide.
According to the embodiment of the invention, the selective etching process adopts a wet photoetching technology, the gate electrode, the source electrode and the drain electrode are prepared by adopting a magnetron sputtering method, and the back electrode is prepared by adopting a vacuum thermal evaporation method.
On the other hand, the invention also provides a strained germanium channel transistor prepared by the preparation method.
According to the technical scheme, the preparation method of the strained germanium channel transistor has at least one of the following beneficial effects:
1. compared with the existing source-drain strain engineering technology based on GeSn alloy, the invention has the advantages that the adopted inert gas atoms have small volume and high solid solubility, and the required atomic concentration is lower when equal tensile strain is achieved, so that the source region and the drain region of the strain germanium channel transistor prepared by adopting the technology can avoid the formation of cluster structures and lattice defects.
2. Compared with the displacement type doping of tin atoms in the existing GeSn alloy, the inert gas atoms adopted by the invention have a closed shell electronic structure, the physical and chemical properties of the alloy are stable, and the alloy is positioned at germanium crystal lattice gap positions of a source region and a drain region after being electrically activated, so that an additional electronic defect state cannot be introduced to the source region and the drain region due to a large amount of crystal lattice loss.
3. The preparation method of the strain germanium channel transistor does not need to change the whole structure and the main body process of the existing planar germanium PMOS transistor, and the related inert atom doping can adopt the ion implantation technology and the pulse laser annealing technology compatible with the silicon process, so the preparation method has high process maturity, good repeatability and low cost and can be carried out at room temperature.
Drawings
FIG. 1 schematically illustrates a strain-inducing mechanism of a strained-channel technique based on inert-atom-doped germanium transistor source and drain regions;
FIG. 2 is a schematic diagram showing strain induced by a change in the lattice structure of a channel of a germanium PMOS device after the source and drain regions are provided with inert gas atoms;
FIG. 3 is a schematic diagram showing the relationship between the lattice constant of a germanium material and the doping species and doping concentration of inert gas atoms;
FIG. 4 schematically illustrates a process flow diagram for the fabrication of a strained germanium channel transistor in accordance with an embodiment of the present invention;
figure 5 schematically illustrates a flow chart of a method of fabricating a strained germanium channel transistor in accordance with an embodiment of the present invention.
Detailed Description
And (3) calculating the lattice structure, the electron wave function distribution and the energy band change after inert atoms (He, Ne and Ar) are placed at partial gap positions of the germanium material by utilizing a first-nature principle density functional theory simulation. The results show that the electrons of the inert atoms are firmly localized near the atomic nucleus, the interaction between the electrons and the covalent electrons of the germanium atoms is negligible, and the influence on the electronic structure of the germanium material is approximately equivalent to the change caused by the expansion of the crystal lattice after the atoms are placed. The inert gas atoms are positioned in the lattice interstitial sites after being placed in the germanium material due to the closed shell electronic structure of the inert gas atoms, no additional electronic defect state is brought, and the whole doping system is thermodynamically stable. In addition, since the inert atoms have a smaller volume and a higher solid solubility than tin atoms, a cluster structure is hardly formed during high-temperature annealing. Therefore, the defects of high defect content, large carrier scattering, high junction current risk and the like of the existing tin doping can be overcome by doping the source drain region with the inert atoms. Finally, theoretical calculation further shows that inert atom doping can reduce the device channel/source-drain interface potential barrier by regulating and controlling the energy band structures of the source region and the drain region, so that the hole transmission characteristic of the device channel is further improved.
Based on the theoretical result, the invention provides a brand new technical approach for realizing the strained germanium PMOS with low cost, high mobility and compatibility with the CMOS process, namely, the source region and the drain region of the existing planar germanium PMOS device are doped by using inert gas atoms with stable electronic shell structures, so that the lattice expansion of the source region and the drain region is induced, and the required transverse compressive strain is introduced into the device channel. The invention will further promote the sustainable development of microelectronics and integrated circuit technology on the basis of maintaining the traditional MOSFET manufacturing process.
For example, fig. 1 schematically illustrates a strain-inducing mechanism of a strained-channel technology based on inert atom doping of germanium transistor source and drain regions; FIG. 2 schematically shows a strain diagram induced by a change in the lattice structure of a channel of a germanium PMOS device after the source region and the drain region are implanted with inert gas atoms.
As shown in fig. 1 and fig. 2, after the inert gas atoms are introduced into the source region and the drain region of the germanium PMOS device, lattice expansion in the horizontal direction and out-of-plane direction is generated in the source region and the drain region of the germanium PMOS device due to doping of the inert gas atoms, and compressive strain is introduced into the device channel due to squeezing.
Fig. 3 is a schematic diagram showing the relationship between the lattice constant of the germanium material and the doping species and doping concentration of the inert gas atoms. As shown in fig. 3, the larger the size of the inert gas atom is, the more the lattice expansion effect is significant at the same doping concentration.
Based on the above theoretical results and experimental findings, the present invention provides a strained germanium channel transistor and a method for manufacturing the strained germanium channel transistor, so that the objects, technical solutions and advantages of the present invention can be more clearly understood.
FIG. 4 schematically illustrates a process flow diagram for the fabrication of a strained germanium channel transistor in accordance with an embodiment of the present invention; figure 5 schematically illustrates a flow chart of a method of fabricating a strained germanium channel transistor in accordance with an embodiment of the present invention.
As shown in fig. 4 and 5, the method includes operations S501 to S506.
In operation 501, a germanium substrate is provided, a sacrificial layer is deposited on the germanium substrate, and portions of the sacrificial layer are selectively etched away.
In an embodiment of the present invention, a high quality n-type germanium substrate is prepared, a sacrificial layer is deposited over the germanium substrate, and the sacrificial layer is selectively etched to form source and drain implant windows (shown as 1-3 in fig. 4) for a germanium PMOS device.
According to the embodiment of the invention, the n-type germanium substrate is a three-dimensional periodic bulk material or a GOI substrate material, and the conductivity is 0.01-0.1 omega cm.
According to the embodiment of the invention, the sacrificial layer is silicon dioxide, and the deposition method for preparing the silicon dioxide of the sacrificial layer can be low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition and magnetron sputtering.
In operation S502, inert gas atom doping and thermal annealing are performed on the germanium substrate region where part of the sacrificial layer is etched away.
In the embodiment of the present invention, the lattice damage of the implanted region is repaired by doping inert gas atoms in the region of the germanium substrate (i.e. the implantation window in step S501) after etching away part of the sacrificial layer, and performing a thermal annealing process on the region (as shown in fig. 4-5).
According to an embodiment of the invention, the inert gas atoms comprise at least one of: helium (He), neon (Ne), argon (Ar); the thermal annealing treatment method can be pulse laser annealing or flash lamp annealing; the inert gas atom doping can adopt an ion implantation technology, and is gap doping.
According to an embodiment of the present invention, to induce lattice expansion of the source and drain regions of a germanium PMOS device, the doping concentration of the inert gas atoms is greater than or equal to 1% of the atomic number of the germanium substrate, higher than the equilibrium solid solubility of the inert gas atoms in the germanium material.
According to the embodiment of the invention, inert gas atoms are doped in the source region and the drain region of the germanium PMOS device by adopting the ion implantation technology compatible with the CMOS process, and because the ion implantation technology is based on the non-equilibrium doping process and the doping atoms are not influenced by the equilibrium solid solubility, the required high-concentration inert gas atoms can be put into the germanium crystal lattice, and the injection distribution can be regulated and controlled by changing the injection conditions.
According to the embodiment of the invention, inert gas atoms are placed into a source region and a drain region of the germanium PMOS device by adopting an ion injection technology compatible with a CMOS (complementary metal oxide semiconductor) process, damaged lattices in the injection region are repaired by adopting a pulse laser annealing technology, required compressive strain is introduced into a channel of the germanium PMOS device, and meanwhile, due to the fact that an electron shell layer of the inert gas atoms is stable in structure, small in size and high in solid solubility, cluster structures and lattice defects can be prevented from being formed in the source region and the drain region, and therefore, the hole mobility of the channel is improved.
In operation S503, p-type doping is performed on the germanium substrate region after the inert gas atom doping and thermal annealing processes are performed, so as to form a source region and a drain region of the germanium PMOS device.
In the embodiment of the present invention, the germanium substrate is p-doped in a partial region (i.e., the implantation window in step S501) obtained after etching away a part of the sacrificial layer, and the doped region is subjected to a second thermal annealing by using a rapid thermal annealing technique, so that the doping atoms are activated to form the source region and the drain region (as shown in fig. 4 at 6-7).
According to the embodiment of the invention, the germanium substrate is doped with boron (B) atoms in a p-type doping mode, and the doped region is subjected to rapid thermal annealing so as to activate the boron atoms to form the source region and the drain region of the germanium PMOS device.
According to the embodiment of the invention, the B atom doping process parameter is the required energy of 10-15 keV, and the doping concentration is 5 multiplied by 1014～1×1016cm-3. Alternatively, the required energies are 10keV, 13keV, 15 keV.
According to the embodiment of the invention, the rapid thermal annealing temperature is 400-600 ℃, and the thermal annealing time is 2-10 min.
Optionally, the thermal annealing temperature is 400 ℃, 450 ℃, 500 ℃, 550 ℃, 600 ℃, and the thermal annealing time is 2min, 5min, 7min, 10 min.
In operation S504, the remaining sacrificial layer is etched away and an isolation layer is deposited, and the isolation layer is selectively etched to form a gate region between the source region and the drain region of the germanium PMOS device.
In the embodiment of the invention, the remaining silicon dioxide sacrificial layer is etched, an isolation layer is deposited on the surface of the germanium substrate, the source region and the drain region, and the isolation layer is selectively etched to manufacture the gate region between the source region and the drain region of the germanium PMOS device (as shown in 8-10 in FIG. 4).
According to the embodiment of the invention, the isolation layer is silicon nitride, and the deposition method for preparing the isolation layer silicon nitride can be low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition and magnetron sputtering.
According to the embodiment of the invention, the lattice constant of the source region and the drain region of the prepared strained germanium PMOS device is larger than the natural lattice constant of the germanium substrate.
In operation S505, the gate region is oxidized, and a dielectric layer is deposited on the surfaces of the isolation layer and the gate region and selectively etched to expose the source region and the drain region.
In an embodiment of the present invention, the gate region is thermally oxidized to obtain germanium oxide (GeO)x) Simultaneously depositing a high dielectric constant dielectric layer on the surface of the residual isolation layer and the surface of the germanium oxide, annealing in a nitrogen atmosphere, and then selectively etching to expose a source region and a drain region of the germanium PMOS device (as shown in 11-14 in figure 4).
According to the embodiment of the invention, the thermal oxidation method can adopt a plasma oxidation method, the process parameters are that the power is 5-10W, and the thermal oxidation time is 20-60 s.
Alternatively, the thermal oxidation power is 5W, 7W and 10W, and the thermal oxidation time is 20s, 30s, 40s, 50s and 60 s.
According to the embodiment of the invention, the annealing temperature in the nitrogen atmosphere is 400-600 ℃, and the annealing time is 1-3 min.
Optionally, the annealing temperature is 400 ℃, 450 ℃, 500 ℃, 550 ℃, 600 ℃, and the annealing time is 1min, 2min, 3 min.
According to the embodiment of the invention, the high-dielectric-constant dielectric layer is hafnium oxide or silicon dioxide, and the method for depositing the high-dielectric-constant dielectric layer can be low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, and magnetron sputtering.
According to an embodiment of the invention, the selective etching used employs a wet lithography technique.
In operation S506, a gate electrode, a source electrode, a drain electrode, and a back electrode of the germanium PMOS device are fabricated.
In the embodiment of the invention, metal layers are respectively deposited on the surface and the back of the germanium PMOS device, and a gate electrode, a source electrode, a drain electrode and a back electrode of the germanium PMOS device are manufactured by selective etching, so that the strained germanium channel transistor (shown as 15-17 in FIG. 4) manufactured by the manufacturing method is obtained. .
According to the embodiment of the invention, the metal layer material can be Au, Ni, Al, Ti; the method for depositing the metal can be a magnetron sputtering method and a vacuum thermal evaporation method.
According to an embodiment of the present invention, the channel of the germanium PMOS device is provided with a compressive strain in a direction parallel to the source and drain.
According to the embodiment of the invention, after a source region and a drain region of a device are defined on the surface of a germanium substrate through a sacrificial layer, inert gas atom doping and crystallization processing are sequentially carried out on the region by adopting an ion implantation technology and a pulse laser annealing technology, and then conventional p-type doping is carried out by adopting B atoms. The inert gas atom doping can induce lattice expansion of a source region and a drain region of the transistor to generate transverse compressive strain, so that the lattice constant of a device channel is shortened, the mobility of charges passing through the channel is improved, and finally the working speed of the PMOS transistor with the help of a hole transfer signal is improved.
While specific embodiments have been provided in accordance with the embodiments of the present invention, it should be noted that these specific embodiments have been described by way of example only, and are not intended to limit the scope of the invention.
For example, a method of fabricating a strained germanium channel transistor using a three-dimensional periodic bulk germanium material having a diamond structure as a substrate is as follows.
S1, depositing a layer of SiO with the thickness of 50nm on the surface of the bulk germanium material substrate by using a low-pressure chemical vapor deposition method2Sacrificial layer and to the SiO2Selectively etching the sacrificial layer to form a source region injection window and a drain region injection window of the germanium PMOS device;
and S2, doping argon (Ar) atoms in the germanium substrate through the injection window by adopting an ion injection technology, and performing primary thermal annealing on the region by adopting a pulse laser annealing technology to repair the lattice damage of the injection region.
And S3, doping B atoms in the germanium substrate through the injection window, carrying out secondary thermal annealing on the doped region by adopting a rapid thermal annealing technology, and activating the doped B atoms to form a source region and a drain region.
Optionally, the process parameters of B atom doping are that the required energy is 12keV, and the doping concentration of B atoms is 5X 1015cm-3(ii) a The rapid thermal annealing temperature is 450 ℃, and the annealing time is 5 min.
S4, etching off the residual SiO2A sacrificial layer, and a Si layer with a thickness of 150nm is deposited on the surface of the germanium substrate and the source region and the drain region by using a plasma enhanced chemical vapor deposition method3N4Barrier layer, and to Si3N4The isolation layer is selectively etched to expose a gate region between the source region and the drain region.
S5, forming germanium oxide (GeO) by plasma oxidation method on the grid regionx) Simultaneously, a layer of 5nm thick high dielectric constant is deposited on the surface of the device by utilizing an atomic layer deposition methodDielectric layer HfO with electric constant2Annealing the substrate in nitrogen atmosphere, and selectively etching to expose the source region and the drain region of the device
Alternatively, the power of the plasma oxidation method is 8W, and the oxidation time is 30 s; the annealing temperature in the nitrogen atmosphere is 500 ℃, and the annealing time is 2 min.
S6, depositing a layer of metal layer Ni with the thickness of 200nm on the surface of the germanium PMOS device by magnetron sputtering, forming a gate electrode, a source electrode and a drain electrode of the germanium PMOS device by selective etching, and then depositing a metal Al layer with the thickness of 50nm on the back surface of the germanium PMOS device by a vacuum thermal evaporation method to be used as a back electrode.
In the present embodiment, the inert gas atoms may be selected to be argon atoms, and the argon atom concentration may be selected to be 1%. It should be noted that, in other embodiments, the implanted atoms may also be helium atoms or neon atoms. According to the relationship between the lattice constant and the doping type and doping concentration of the inert atoms in fig. 3, the larger the size of the inert gas atoms is, the more obvious the lattice expansion effect is, and the lower the required doping concentration under the same strain is. However, considering that large-sized inert atoms will cause more serious lattice damage during ion implantation, the requirement on the pulse laser annealing condition for crystallization is higher, so the inert gas atom species for ion implantation and the pulse laser annealing condition for recrystallization need to be considered in a compromise manner in the device manufacturing process.
In this embodiment, a pulsed laser annealing technique based on a liquid phase epitaxial crystallization mechanism is used to repair the germanium lattice. Because the pulse laser annealing technology has an ultra-fast crystallization rate, the redistribution of inert atoms in the annealing process can be effectively inhibited while the germanium crystal lattice is repaired, thereby avoiding unnecessary junction diffusion and reducing the influence of doping atoms on source-drain and channel interfaces.
The above embodiments describe a strained germanium channel transistor and a method for fabricating the strained germanium channel transistor in detail. It is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; those skilled in the art can make many possible variations and modifications to the invention using the methods and techniques disclosed above, or to modify equivalent embodiments with equivalent variations, without departing from the scope of the invention. Therefore, any modifications, equivalents, improvements and the like made to the above embodiments according to the technical spirit of the present invention should be included in the protection scope of the present invention, unless they depart from the technical spirit of the present invention.
Claims (10)
1. A method of fabricating a strained germanium channel transistor, comprising:
providing a germanium substrate, depositing a sacrificial layer on the germanium substrate, and selectively etching off part of the sacrificial layer;
carrying out inert gas atom doping and thermal annealing treatment on the germanium substrate region with the part of the sacrificial layer etched away;
carrying out p-type doping on the germanium substrate region subjected to the inert gas atom doping and thermal annealing treatment to form a source region and a drain region of the germanium PMOS device;
etching the rest sacrificial layer and depositing an isolation layer, and selectively etching the isolation layer to form a gate region between a source region and a drain region of the germanium PMOS device;
oxidizing the grid region, depositing a dielectric layer on the surfaces of the isolation layer and the grid region and selectively etching to expose the source region and the drain region;
and manufacturing a gate electrode, a source electrode, a drain electrode and a back electrode of the germanium PMOS device.
2. The method of claim 1 wherein the germanium substrate is an n-type three-dimensional periodic bulk material or a GOI substrate material.
3. The method of fabricating a strained germanium channel transistor according to claim 1, wherein the inert gas atoms comprise at least one of: helium (He), neon (Ne), argon (Ar); the p-type doping atoms are boron atoms.
4. The method of claim 1 wherein the noble gas atomic doping is gap doping with a doping concentration greater than or equal to 1% of the atomic number of the germanium substrate.
5. The method of fabricating a strained germanium channel transistor according to claim 1, wherein the thermal anneal is a pulsed laser anneal or a flash lamp anneal; the lattice constant of the source region and the drain region is larger than the natural lattice constant of the germanium substrate.
6. The method of claim 1 wherein the channel of the germanium PMOS device is compressively strained in a direction parallel to the source and drain.
7. The method of claim 1, wherein the inert gas atomic doping employs an ion implantation technique, and the steps of depositing the sacrificial layer, depositing the isolation layer, and depositing the dielectric layer comprise: plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atomic layer deposition, magnetron sputtering.
8. The method of claim 1, wherein the sacrificial layer is silicon dioxide, the isolation layer is silicon nitride, and the dielectric layer is hafnium dioxide or silicon dioxide.
9. The method of claim 1, wherein the selective etching process is performed by a wet lithography technique, the gate electrode, the source electrode and the drain electrode are formed by magnetron sputtering, and the back electrode is formed by vacuum thermal evaporation.
10. A strained germanium channel transistor prepared by the preparation method of any one of claims 1-9.
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