CN112701034A - Method for manufacturing grid - Google Patents

Method for manufacturing grid Download PDF

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Publication number
CN112701034A
CN112701034A CN202011561763.5A CN202011561763A CN112701034A CN 112701034 A CN112701034 A CN 112701034A CN 202011561763 A CN202011561763 A CN 202011561763A CN 112701034 A CN112701034 A CN 112701034A
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photoresist
region
gate
layer
forming
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CN112701034B (en
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付嵛
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention relates to a manufacturing method of a grid, which relates to a manufacturing technology of a semiconductor integrated circuit, wherein the thickness of photoresist is reduced by utilizing the loading effect of an ISO (international organization for standardization) region, so that the reduction rate of the photoresist of the ISO region is correspondingly slower so as to achieve the effect of reducing the thickness difference of the photoresist of different regions; and because the photoresist is thinned, the dry etching program intensity of removing the photoresist on the top layer of the polysilicon gate by EB1 can be correspondingly reduced, so that less photoresist can be consumed in an ISO region EB1, the defect window of the subsequent EB2 can be increased, the problem of insufficient process windows of OX residual and SiGe file dam in the dry etching process can be solved, and the defect problem of the HK28 photoresist after the dry etching process in the back etching process can be solved.

Description

Method for manufacturing grid
Technical Field
The present invention relates to semiconductor integrated circuit manufacturing technologies, and in particular, to a method for manufacturing a gate.
Background
The HKMG process, such as 28nm HKMG, requires the simultaneous formation of a high dielectric constant (HK) gate dielectric layer and a Metal Gate (MG), and the post metal gate process is generally used in the conventional HKMG process. In the post-metal gate process, a gate dielectric layer, a channel region and a source drain region of a device are usually formed by adopting a polysilicon gate (Poly) of a Dummy gate structure, namely Dummy polysilicon gate (Dummy Poly), and then replacement of a metal gate is performed, namely, the polysilicon gate of the Dummy gate structure is removed (Dummy Poly remove, DPR), and then the removed region of the polysilicon gate is filled with metal to form the metal gate. Before removing the polysilicon gate, a Hard Mask (HM) including an oxide layer is formed on the top of the polysilicon gate, so that the oxide layer of the Hard Mask needs to be removed before removing the polysilicon gate. In addition, the density and size of the polysilicon gate on the semiconductor substrate often vary, and specifically, referring to fig. 1a, fig. 1a is a schematic view of a device structure in one conventional gate manufacturing process, as shown in fig. 1a, the semiconductor substrate 100 includes an open region 110, an isolated pattern region (ISO)120 and a dense pattern region (dense) 130, and the device density gradually increases. The dummy polysilicon gate structure includes a gate dielectric layer 210, a polysilicon gate 220, and a hard mask layer 230 formed of a first nitride layer 231 and a second oxide layer 232. And the polysilicon gate comprises a large-sized polysilicon gate and a small-sized polysilicon gate.
The conventional process for removing the oxide layer of the hard mask layer includes: step one, forming a photoresist 310; step two, opening the photoresist on the bulk polysilicon gate through a photolithography process, as shown in a device structure diagram of one of the existing gate manufacturing processes shown in fig. 1 b; step three, opening the photoresist on the rest polysilicon gates through an Etch Back (EB) of Photoresist (PR), namely EB1, mainly in order to overcome the photoresist load (loading) on the bulk polysilicon gates, wherein all the polysilicon gates are already opened, as shown in fig. 1c, which is a schematic view of a device structure in one of the existing gate manufacturing processes; step four, a second etching back process, i.e. EB2, is performed to remove the second oxide layer 232 of the hard mask layer, as shown in fig. 1d, which is a schematic device structure diagram of one of the existing gate manufacturing processes. In the 28nm HKMG process, in order to avoid damage (damage) to other regions such as the active region in the process of removing the oxide layer of the hard mask layer of the polysilicon gate, the other regions are protected by a photoresist, and after EB1, the residual amount of the photoresist on the small polysilicon gate needs to be paid special attention, which is too high, so that the photoresist on the polysilicon gate is not completely opened, and the hard mask layer cannot be completely removed; however, too low photoresist tends to result in no protection of the silicon germanium (SGe) on the surface of the Active Area (AA) on both sides of the polysilicon gate, and even no protection of the AA by the photoresist, which may eventually result in nickel silicide (Nisi) or SiGe dam, resulting in a thinner photoresist in the ISO region and thus insufficient process windows of OX residual and SiGe film dam in the dry etching process. This is mainly due to the difference in height of the photoresist in different regions, as shown in FIG. 1a, the photoresist 310 is 110nm above the dummy gate structure H1 in the dense pattern region (dense) 130, and 160nm above the substrate H1 in the open region 110. And the height of the top of the photoresist decreases in order from the dense pattern region (dense) 130, the isolated pattern region (ISO)120 to the open region 110.
In contrast, the main solution in the prior art is to increase the thickness of the photoresist as much as possible to reduce the loading effect of the photoresist filling so as to make up for the problem of insufficient process windows of OX residual and SiGe file data in the dry etching process, but the practical product shows that the problem is difficult to reduce by thickening the photoresist due to the fact that the ISO region is too large.
Disclosure of Invention
The invention provides a manufacturing method of a grid, comprising the following steps: s1: providing a semiconductor substrate, sequentially forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate, forming a field oxide layer in the semiconductor substrate, and isolating an active region by the field oxide layer, wherein a hollow region, an isolated pattern region and a dense pattern region are respectively positioned in different active regions; s2: forming a hard mask layer on the surface of the polysilicon gate, wherein the hard mask layer is formed by overlapping a first nitride layer and a second oxide layer; s3: photoetching and etching are carried out to form a plurality of pseudo gate structures, and each pseudo gate structure is formed by overlapping the etched gate dielectric layer, the etched polysilicon gate and the hard mask layer; s4: forming a side wall on the side surface of each pseudo gate structure; s5: forming a source region and a drain region of a device in the active regions at two sides of the pseudo gate structure, wherein the process of forming the source region and the drain region of the device comprises an assembly enhancement process, and the assembly enhancement process forms a germanium-silicon layer in the source region or the drain region of the p-type field effect transistor; s6: forming photoresist, wherein the photoresist is higher than the pseudo gate structure by 15nm to 25nm in the dense pattern region and is higher than the substrate by 90nm to 110nm in the open region; s7: carrying out back etching of the photoresist for the first time, and opening the photoresist on all the polysilicon gates; s8: carrying out back etching of the photoresist for the second time, and removing the second oxide layer of the hard mask layer; and S9: and removing the polysilicon gate, and forming a metal gate in the removal region of the polysilicon gate.
Further, the heights of the tops of the photoresist decrease sequentially from the dense pattern region, the isolated pattern region to the open region in S6.
Furthermore, in S6, the photoresist is 20nm higher than the dummy gate structure in the dense pattern region and 100nm higher than the semiconductor substrate in the open region.
Further, the first photoresist etch back in S7 etches 45nm to 65nm of photoresist.
Further, the first photoresist etch back etches away 55nm of photoresist.
Further, between S6 and S7, S61: and opening the photoresist on the large polysilicon gate through a photoetching process.
Furthermore, the semiconductor substrate is a silicon substrate.
Further, the gate dielectric layer includes a high dielectric constant layer.
Furthermore, the field oxide layer is shallow trench field oxide.
Further, the shallow trench field oxide is formed by adopting a shallow trench isolation process
Drawings
Fig. 1a to fig. 1d are schematic device structures of a conventional gate fabrication process.
Fig. 2 a-2 c are schematic device structures of one process of manufacturing a gate according to an embodiment of the invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In an embodiment of the present invention, a method for manufacturing a gate is provided, including: s1: providing a semiconductor substrate, sequentially forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate, forming a field oxide layer in the semiconductor substrate, and isolating an active region by the field oxide layer, wherein a hollow region, an isolated pattern region and a dense pattern region are respectively positioned in different active regions; s2: forming a hard mask layer on the surface of the polysilicon gate, wherein the hard mask layer is formed by overlapping a first nitride layer and a second oxide layer; s3: photoetching and etching are carried out to form a plurality of pseudo gate structures, and each pseudo gate structure is formed by overlapping the etched gate dielectric layer, the etched polysilicon gate and the hard mask layer; s4: forming a side wall on the side surface of each pseudo gate structure; s5: forming a source region and a drain region of a device in the active regions at two sides of the pseudo gate structure, wherein the process of forming the source region and the drain region of the device comprises an assembly enhancement process, and the assembly enhancement process forms a germanium-silicon layer in the source region or the drain region of the p-type field effect transistor; s6: forming photoresist, wherein the photoresist is higher than the pseudo gate structure by 15nm to 25nm in the dense pattern region and is higher than the substrate by 90nm to 110nm in the open region; s7: carrying out back etching of the photoresist for the first time, and opening the photoresist on all the polysilicon gates; s8: carrying out back etching of the photoresist for the second time, and removing the second oxide layer of the hard mask layer; and S9: and removing the polysilicon gate, and forming a metal gate in the removal region of the polysilicon gate.
Specifically, referring to fig. 2a to 2c, fig. 2a to 2c are schematic device structures of a gate manufacturing process according to an embodiment of the invention. The method for manufacturing the grid electrode comprises the following steps:
s1: as shown in fig. 2a, a semiconductor substrate 1000 is provided, a gate dielectric layer 2100 and a polysilicon gate 2200 are sequentially formed on the surface of the semiconductor substrate 1000, a field oxide layer 1010 is formed in the semiconductor substrate 1000, an active region is isolated by the field oxide layer 1010, and a hollow region 1100, an isolated pattern region (ISO)1200 and a dense pattern region (dense) 1300 are respectively located in different active regions.
The semiconductor substrate 1000 is a silicon substrate.
The gate dielectric layer 2100 includes a high dielectric constant layer.
And the device densities of the open region 1100, the isolated pattern region (ISO)1200, and the dense pattern region (dense) 1300 gradually increase. And the polysilicon gates include large-sized polysilicon gates and small-sized polysilicon gates, for example, the polysilicon gates in the isolated pattern region (ISO)1200 are large-sized polysilicon gates, and the polysilicon gates in the dense pattern region (dense) 1300 are small-sized polysilicon gates.
The field oxide layer 1010 is shallow trench field oxide and is formed by a shallow trench isolation process.
S2: as shown in fig. 2a, a hard mask layer 2300 is formed on the surface of the polysilicon gate 2200, wherein the hard mask layer 2300 is formed by overlapping a first nitride layer 2310 and a second oxide layer 2320.
S3: as shown in fig. 2a, photolithography and etching are performed to form a plurality of dummy gate structures, and each of the dummy gate structures is formed by stacking the etched gate dielectric layer 2100, the etched polysilicon gate 2200, and the hard mask layer 2300.
S4: as shown in fig. 2a, a sidewall spacer 2400 is formed on a side surface of each of the dummy gate structures.
The material of the sidewall spacer 2400 includes a nitride layer.
S5: and forming a source region and a drain region of the device in the active regions at two sides of the pseudo gate structure, wherein the forming process of the source region and the drain region of the device comprises an assembly enhancement process, and the assembly enhancement process forms a germanium-silicon layer (SiGe) in the source region or the drain region of the p-type field effect transistor.
S6: as shown in fig. 2a, a photoresist 3100 is formed, wherein the photoresist 3100 is between 15nm and 25nm higher than the dummy gate structure in the dense pattern region (density)1300 and between 90nm and 110nm higher than the substrate in the open region 1100.
More specifically, the top height of the photoresist decreases in order from the dense pattern region (dense) 1300, the isolated pattern region (ISO)1200, to the open region 1100.
I.e. the invention employs a method of reducing the thickness of the photoresist compared to the prior art. As shown in fig. 1a of the prior art, the photoresist 310 is higher than the dummy gate structure 110nm in the dense pattern region (density)130 and higher than the substrate 160nm in the open region 110. Therefore, the thickness of the photoresist formed by the present invention S6 is greatly reduced compared to the prior art.
More specifically, in one embodiment, the photoresist 3100 is 20nm higher than the dummy gate structure in the dense pattern region (dense) 1300 and 100nm higher than the semiconductor substrate in the open region 1100.
S7: as shown in fig. 2b, a first Etch Back (EB) of the Photoresist (PR) is performed, EB1, to open the photoresist on all the polysilicon gates.
Due to the fact that the photoresist formed in S6 is thinner, the strength of the first photoresist etch-back process of the present application may also be reduced correspondingly compared to the prior art, for example, the strength of the first photoresist etch-back process may be reduced by reducing the etching time or power of the first photoresist etch-back process.
The dry etch process intensity of EB1 for removing the top layer photoresist of polysilicon gate can be reduced accordingly due to the thinner photoresist, so that less photoresist can be consumed in ISO region EB1, so as to increase the defect window of the subsequent EB 2.
The first etch back of the photoresist, EB1, etches away 145nm of photoresist as shown in prior art figure 1 c. As shown in fig. 2b, the 45nm to 65nm photoresist is etched by the first etching back EB1, and more specifically, the 55nm photoresist is etched by the first etching back EB 1.
S8: as shown in fig. 2c, an Etch Back (EB) of the second Photoresist (PR) is performed, EB2, to remove the second oxide layer 2320 of the hard mask layer.
S9: and removing the polysilicon gate, and forming a metal gate in the removal region of the polysilicon gate.
In an embodiment of the present invention, between S6 and S7, S61 may be further included: and opening the photoresist on the large polysilicon gate through a photoetching process.
As mentioned above, the inventor of the present application reversely thinks, compared to the conventional manner of the prior art, that the prior art uses an increased photoresist thickness by using the ISO region loading effect, but the thickening ratio of the method to the ISO region is low, the inventor reversely thinks uses a decreased photoresist thickness, so that the decreasing rate of the photoresist in the ISO region is correspondingly slow to achieve the effect of decreasing the difference in the photoresist thickness in different regions; and because the photoresist is thinned, the dry etching program intensity of removing the photoresist on the top layer of the polysilicon gate by EB1 can be correspondingly reduced, so that less photoresist can be consumed in an ISO region EB1, the defect window of the subsequent EB2 can be increased, the problem of insufficient process windows of OX residual and SiGe file dam in the dry etching process can be solved, and the defect problem of the HK28 photoresist back etching (PREB) process after the dry etching process can be improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A method for manufacturing a gate electrode, comprising:
s1: providing a semiconductor substrate, sequentially forming a gate dielectric layer and a polysilicon gate on the surface of the semiconductor substrate, forming a field oxide layer in the semiconductor substrate, and isolating an active region by the field oxide layer, wherein a hollow region, an isolated pattern region and a dense pattern region are respectively positioned in different active regions;
s2: forming a hard mask layer on the surface of the polysilicon gate, wherein the hard mask layer is formed by overlapping a first nitride layer and a second oxide layer;
s3: photoetching and etching are carried out to form a plurality of pseudo gate structures, and each pseudo gate structure is formed by overlapping the etched gate dielectric layer, the etched polysilicon gate and the hard mask layer;
s4: forming a side wall on the side surface of each pseudo gate structure;
s5: forming a source region and a drain region of a device in the active regions at two sides of the pseudo gate structure, wherein the process of forming the source region and the drain region of the device comprises an assembly enhancement process, and the assembly enhancement process forms a germanium-silicon layer in the source region or the drain region of the p-type field effect transistor;
s6: forming photoresist, wherein the photoresist is higher than the pseudo gate structure by 15nm to 25nm in the dense pattern region and is higher than the substrate by 90nm to 110nm in the open region;
s7: carrying out back etching of the photoresist for the first time, and opening the photoresist on all the polysilicon gates;
s8: carrying out back etching of the photoresist for the second time, and removing the second oxide layer of the hard mask layer; and
s9: and removing the polysilicon gate, and forming a metal gate in the removal region of the polysilicon gate.
2. The method of claim 1, wherein the heights of the top portions of the photoresist decrease sequentially from the dense pattern region, the isolated pattern region to the open region in S6.
3. The method of claim 1, wherein in S6, the photoresist is 20nm higher than the dummy gate structure in the dense pattern region and 100nm higher than the semiconductor substrate in the open region.
4. The method of claim 1, wherein the first photoresist etch back in S7 etches away 45nm to 65nm of photoresist.
5. The method of claim 4 wherein the first etch back of the photoresist etches away 55nm of photoresist.
6. The method of claim 1, further comprising, between S6 and S7, S61: and opening the photoresist on the large polysilicon gate through a photoetching process.
7. The method of manufacturing a gate electrode according to claim 1, wherein the semiconductor substrate is a silicon substrate.
8. The method of claim 1, wherein the gate dielectric layer comprises a high-k layer.
9. The method of claim 1 wherein the field oxide layer is shallow trench field oxide.
10. The method of claim 9, wherein the shallow trench field oxide is formed by a shallow trench isolation process.
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