CN112698715B - Execution control method, device, embedded system, equipment and medium - Google Patents
Execution control method, device, embedded system, equipment and medium Download PDFInfo
- Publication number
- CN112698715B CN112698715B CN202011500868.XA CN202011500868A CN112698715B CN 112698715 B CN112698715 B CN 112698715B CN 202011500868 A CN202011500868 A CN 202011500868A CN 112698715 B CN112698715 B CN 112698715B
- Authority
- CN
- China
- Prior art keywords
- processor
- idle
- address space
- target address
- task
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/329—Power saving characterised by the action undertaken by task scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention discloses an execution control method, an execution control device, an embedded system, an embedded device and a medium, comprising the following steps: detecting whether the processor is currently in an idle state in real time; if yes, accessing a target address space with non-cache attributes, and positioning idle tasks stored in the target address space; and continuously accessing the target address space, and circularly executing the idle task. The technical scheme of the embodiment of the invention can avoid frequent access to the cache when the processor executes the idle task, and can effectively reduce the power consumption of the embedded system.
Description
Technical Field
The embodiment of the invention relates to the technical field of computer application, in particular to an execution control method, an execution control device, an embedded system, embedded equipment and a medium.
Background
As a computer system specially designed for meeting a specific field, the embedded system has severe requirements in design and application, and power consumption is an important performance index of the embedded system, and has important influence on the equipment stability and the application field of the embedded system. In an embedded system, in order to reduce the system power consumption, a power management module is generally used for controlling a central processing unit (Central Processing Unit, CPU) to enter a sleep mode when the CPU is idle, and the power management module is used for waking up the CPU when the CPU needs to execute a task, but the method is easy to reduce the real-time performance of the CPU on the task response.
In order to ensure the real-time performance of the CPU response task, when the CPU is idle in the existing embedded system, the CPU is generally not controlled to enter a sleep mode, but is controlled to execute the task with the lowest priority, namely the idle task (hereinafter referred to as idle task). The manner in which the CPU performs the idle task is two: (1) performing a wait operation under a wait instruction wait; (2) Executing preset loop codes, wherein the loop codes are equivalent to the idle tasks.
However, for a CPU (such as a loongson processor) that does not support wait instructions, the second mode can only be used when performing idle tasks, and since the loop code executed by the CPU is set in the address range of the cache, the cache hit rate is high, and the power consumption of the embedded system increases. Taking a Loongson processor in a channel system as an example, assuming that the number of the Loongson processor cores is 4, according to a test result, when 4 cores in the Loongson processor all run idle tasks, the power consumption of the channel system is 20% more than when 1 core runs basic system tasks and the rest 3 cores run idle tasks.
Disclosure of Invention
The embodiment of the invention provides an execution control method, an execution control device, an embedded system, an embedded device and a medium, which can avoid frequent access to a cache when a processor executes idle tasks and can effectively reduce the power consumption of the embedded system.
In a first aspect, an embodiment of the present invention provides an execution control method, which is executed by a processor in an embedded system, the method including:
detecting whether the processor is currently in an idle state in real time;
if yes, accessing a target address space with non-cache attributes, and positioning idle tasks stored in the target address space;
and continuously accessing the target address space, and circularly executing the idle task.
In a second aspect, an embodiment of the present invention further provides an execution control device, executed by a processor in an embedded system, where the device includes:
the idle state detection module is used for detecting whether the processor is in an idle state currently in real time;
the target address space access module is used for accessing a target address space with non-cache attribute when detecting that the target address space is currently in an idle state and positioning idle tasks stored in the target address space;
and the idle task execution module is used for continuously accessing the target address space and circularly executing the idle task.
In a third aspect, an embodiment of the present invention further provides an embedded system, where the embedded system includes:
one or more processors;
a storage means for storing one or more programs;
when the one or more programs are executed by the one or more processors, the one or more processors implement an execution control method provided by any embodiment of the present invention.
In a fourth aspect, an embodiment of the present invention further provides a computer device, where the computer device includes the embedded system provided by any embodiment of the present invention.
In a fifth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements an execution control method provided by any embodiment of the present invention.
The technical scheme of the embodiment of the invention detects whether the processor is in an idle state currently in real time; if yes, accessing a target address space with non-cache attribute, positioning an idle task stored in the target address space, continuously accessing the target address space, and circularly executing the idle task.
Drawings
FIG. 1 is a flow chart of a method of performing control in accordance with a first embodiment of the present invention;
FIG. 2 is a flow chart of a control method according to a second embodiment of the present invention;
fig. 3 is a block diagram of an execution control device in a third embodiment of the present invention;
FIG. 4 is a block diagram of an embedded system in accordance with a fourth embodiment of the present invention;
fig. 5 is a schematic structural diagram of a computer device in a fifth embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Example 1
Fig. 1 is a flowchart of a control method for executing tasks, which is provided in an embodiment of the present invention, and the method may be executed by an execution control device, and the device may be implemented by software and/or hardware and may be generally integrated in a processor in an embedded system, and specifically includes the following steps:
In this embodiment, optionally, the number of task threads currently executed by the processor may be obtained in real time, and if the number of task threads is less than a preset threshold, it may be determined that the processor is currently in an idle state; otherwise, if the number of task threads is greater than or equal to the preset threshold, determining that the processor is not currently in an idle state.
In this embodiment, if it is detected that the processor is currently in an idle state, step 120 is performed; if the processor is detected not to be in the idle state currently, the number of task threads currently executed by the processor is continuously acquired in real time so as to detect whether the processor is in the idle state or not.
In this embodiment, when it is determined that the processor is in the idle state, the control processor accesses a target address space of a non-cache attribute in which idle tasks are stored in advance.
The target address space is different from the address space specified in the cache memory, that is, the target address space has a non-cache attribute (Uncached). The idle task may specifically be a preset program loop code. Optionally, after the processor accesses the target address space, the idle task may be acquired in the target address space according to a preset identifier.
And 130, continuously accessing the target address space, and circularly executing the idle task.
In this embodiment, when the processor is in an idle state, the processor is controlled to continuously access the target address space with non-cache attribute, and execute the idle task in a circulating manner, so that on one hand, the real-time performance of the processor in response to the task can be ensured; on the other hand, the frequent access to the cache when the processor executes the idle task can be avoided, so that the power consumption of the embedded system can be effectively reduced.
The technical scheme of the embodiment of the invention detects whether the processor is in an idle state currently in real time; if yes, accessing a target address space with non-cache attribute, positioning an idle task stored in the target address space, continuously accessing the target address space, and circularly executing the idle task.
Example two
The present embodiment is a further refinement of the first embodiment, and the same or corresponding terms as those of the first embodiment are explained, and the description of the present embodiment is omitted. Fig. 2 is a flowchart of a method for executing control according to a second embodiment of the present invention, in this embodiment, a technical solution of the present embodiment may be combined with one or more methods in the solutions of the foregoing embodiments, and in this embodiment, as shown in fig. 2, the method provided by the embodiment of the present invention may further include:
In this step, the working parameters currently corresponding to the processor may be obtained, where the working parameters may include the number of task threads currently executed by the processor, the occupancy rate of the processor, and the like.
In one implementation of the embodiment of the present invention, the operating parameters include a processor occupancy rate and a processor idle rate; detecting whether the processor is currently in an idle state according to each working parameter comprises the following steps: and if the processor occupancy rate is smaller than a preset first threshold value and the processor idle rate is larger than a preset second threshold value, determining that the processor is in an idle state.
In this step, the occupancy rate may be a percentage of the total resources occupied by the processor by the tasks executed by the processor, and the processor idle rate may be a percentage of the total number of cores in the processor and the number of cores in the processor that do not execute the tasks. In one particular embodiment, the processor may obtain the processor occupancy and the processor idleness according to a getsystemitime function.
In this embodiment, after obtaining the processor occupancy rate and the processor idle rate, comparing the processor occupancy rate with a preset first threshold, comparing the processor idle rate with a preset second threshold, and if the processor occupancy rate is smaller than the preset first threshold and the processor idle rate is greater than the preset second threshold, determining that the processor is in an idle state; otherwise, if the occupancy rate of the processor is greater than or equal to a preset first threshold value or the idle rate of the processor is less than or equal to a preset second threshold value, determining that the processor is not in an idle state, and continuously acquiring the current corresponding working parameters of the processor to detect whether the processor is in the idle state.
Therefore, the accuracy of the processor idle state detection result can be improved by acquiring the processor occupancy rate and the processor idle rate and determining whether the processor is in an idle state according to the processor occupancy rate and the processor idle rate.
In one implementation of this embodiment, the idle task includes an absolute jump instruction directed to the target address space to enable continuous access to the target address space.
By setting the absolute jump instruction in the idle task, the idle task executed by the processor can be ensured to be always located in the target address space, and the situation that the address corresponding to the idle task is located outside the target address space in the process of circularly executing the idle task by the processor is avoided, so that frequent access to a cache when the processor executes the idle task can be avoided, and further the power consumption of the embedded system can be effectively reduced.
In a specific embodiment, the idle task may be program loop code composed of a plurality of assembler instructions, and the target address space may be a kernel segment kseg1 in the processor, where the kseg1 segment has a non-cache attribute. Specifically, the processor may be a processor that does not support wait instructions, typically, the processor may be a Loongson processor, and accordingly, the target address space may be kseg1 segment in the Loongson address space.
In this embodiment, the target address space may be 0xa0000000-0xbfffffff, and the idle task formed by multiple assembler instructions may specifically be as follows:
wherein, "section" _kseg1"" in the assembly instruction indicates that the target address space is set as kseg1 segment in the Loongson address space; ". ent idleloop" represents the name defining an idle task; "1" means that the loop starts to execute idle tasks; "b 1b" represents an absolute jump instruction directed to the target address space; ". end idlelop" indicates that execution of an idle task is ended.
In this embodiment, in the process of circularly executing the idle task, the method further includes: and when a new user task is detected, switching to execute the new user task.
And if the processor detects a new user task in the process of circularly executing the idle task, ending the execution process of the idle task and starting to execute the new user task, thereby ensuring the real-time performance of the response task of the processor.
In a specific embodiment, taking a Loongson processor in a channel system as an example, according to the execution control method provided by the embodiment, after the processor is controlled to execute tasks, the power consumption of the channel system can be reduced by 15% -25% according to the test result.
According to the technical scheme, at least one working parameter is obtained in real time, whether the processor is in an idle state currently is detected according to the working parameters, if so, a target address space with non-cache attribute is accessed, idle tasks stored in the target address space are located, then the target address space is continuously accessed, the idle tasks are circularly executed, frequent access to a cache when the processor executes the idle tasks can be avoided, and power consumption of an embedded system can be effectively reduced.
Example III
Fig. 3 is a block diagram of an execution control device according to a third embodiment of the present invention, where the execution control device is executed by a processor in an embedded system, and the execution control device includes: an idle state detection module 310, a target address space access module 320, and an idle task execution module 330.
The idle state detection module 310 is configured to detect in real time whether the processor is currently in an idle state;
the target address space access module 320 is configured to access a target address space with non-cache attribute and locate an idle task stored in the target address space when detecting that the processor is currently in an idle state;
and the idle task execution module 330 is configured to continuously access the target address space and circularly execute the idle task.
The technical scheme of the embodiment of the invention detects whether the processor is in an idle state currently in real time; if yes, accessing a target address space with non-cache attribute, positioning an idle task stored in the target address space, continuously accessing the target address space, and circularly executing the idle task.
On the basis of the above embodiments, the idle task includes an absolute jump instruction pointing to the target address space to achieve continuous access to the target address space; the target address space is a kernel segment kseg1;
the idle state detection module 310 may include:
the working parameter acquisition unit is used for acquiring at least one working parameter in real time and detecting whether the processor is in an idle state currently according to each working parameter; the working parameters comprise the occupancy rate of the processor and the idle rate of the processor;
and the idle state determining unit is used for determining that the processor is in an idle state when the occupancy rate of the processor is smaller than a preset first threshold value and the idle rate of the processor is larger than a preset second threshold value.
The idle task execution module 330 may include:
and the task switching unit is used for switching and executing the new user task when detecting the new user task.
The execution control device provided by the embodiment of the invention can execute the execution control method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Example IV
Fig. 4 is a schematic structural diagram of an embedded system according to a fourth embodiment of the present invention, as shown in fig. 4, the embedded system includes a processor 410, a memory 420, an input device 430 and an output device 440; the number of processors 410 in the embedded system may be one or more, one processor 410 being taken as an example in fig. 4; the processor 410, memory 420, input device 430, and output device 440 in the embedded system may be connected by a bus or other means, for example in fig. 4. The memory 420 is a computer readable storage medium, and may be used to store a software program, a computer executable program, and modules, such as program instructions/modules corresponding to an execution control method in any embodiment of the present invention (e.g., an idle state detection module 310, a target address space access module 320, and an idle task execution module 330 in an execution control device). The processor 410 executes various functional applications of the embedded system and data processing, i.e., implements one of the execution control methods described above, by running software programs, instructions, and modules stored in the memory 420. That is, the program, when executed by the processor, implements:
detecting whether the processor is currently in an idle state in real time;
if yes, accessing a target address space with non-cache attributes, and positioning idle tasks stored in the target address space;
and continuously accessing the target address space, and circularly executing the idle task.
Example five
Fig. 5 is a schematic structural diagram of a computer device in a fifth embodiment of the present invention, and as shown in fig. 5, the computer device 501 includes an embedded system 502 provided in any embodiment of the present invention, and the embedded system includes a processor 503 provided in any embodiment of the present invention. In this embodiment, the processor 503 detects in real time whether the processor is currently in an idle state; if yes, accessing a target address space with non-cache attribute, positioning an idle task stored in the target address space, continuously accessing the target address space, and circularly executing the idle task.
Example six
The sixth embodiment of the present invention further provides a computer readable storage medium having a computer program stored thereon, where the computer program when executed by a processor implements the method according to any embodiment of the present invention. Of course, a computer-readable storage medium provided by an embodiment of the present invention may perform a related operation in a method for performing control provided by any embodiment of the present invention. That is, the program, when executed by the processor, implements:
detecting whether the processor is currently in an idle state in real time;
if yes, accessing a target address space with non-cache attributes, and positioning idle tasks stored in the target address space;
and continuously accessing the target address space, and circularly executing the idle task.
From the above description of embodiments, it will be clear to a person skilled in the art that the present invention may be implemented by means of software and necessary general purpose hardware, but of course also by means of hardware, although in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, etc., and include several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the embodiments of the present invention.
It should be noted that, in the embodiment of the foregoing positioning device for testing abnormality, each unit and module included are only divided according to the functional logic, but not limited to the above-mentioned division, so long as the corresponding functions can be implemented; in addition, the specific names of the functional units are also only for distinguishing from each other, and are not used to limit the protection scope of the present invention.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. An execution control method executed by a processor in an embedded system, comprising:
detecting whether the processor is currently in an idle state in real time;
if yes, accessing a target address space with non-cache attributes, and positioning idle tasks stored in the target address space;
and continuously accessing the target address space, and circularly executing the idle task.
2. The method according to claim 1, characterized in that:
the idle task includes an absolute jump instruction directed to the target address space to enable continued access to the target address space.
3. The method of claim 1, wherein detecting in real time whether the processor is currently in an idle state comprises:
and acquiring at least one working parameter in real time, and detecting whether the processor is in an idle state currently according to each working parameter.
4. The method of claim 3, wherein the operating parameters include processor occupancy and processor idle rate;
detecting whether the processor is currently in an idle state according to each working parameter comprises the following steps:
and if the processor occupancy rate is smaller than a preset first threshold value and the processor idle rate is larger than a preset second threshold value, determining that the processor is in an idle state.
5. The method of claim 1, further comprising, in cycling through execution of the idle tasks:
and when a new user task is detected, switching to execute the new user task.
6. The method according to any one of claims 1-5, wherein the target address space is a kernel segment kseg1.
7. An execution control device executed by a processor in an embedded system, the device comprising:
the idle state detection module is used for detecting whether the processor is in an idle state currently in real time;
the target address space access module is used for accessing a target address space with non-cache attribute when detecting that the processor is currently in an idle state, and positioning idle tasks stored in the target address space;
and the idle task execution module is used for continuously accessing the target address space and circularly executing the idle task.
8. An embedded system, comprising:
one or more processors;
a storage means for storing one or more programs;
the execution control method of any one of claims 1-6 is implemented when the one or more programs are executed by the one or more processors, such that the one or more processors execute the programs.
9. A computer device comprising the embedded system of claim 8.
10. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when executed by a processor, implements the execution control method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011500868.XA CN112698715B (en) | 2020-12-17 | 2020-12-17 | Execution control method, device, embedded system, equipment and medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011500868.XA CN112698715B (en) | 2020-12-17 | 2020-12-17 | Execution control method, device, embedded system, equipment and medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112698715A CN112698715A (en) | 2021-04-23 |
| CN112698715B true CN112698715B (en) | 2023-07-04 |
Family
ID=75509009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011500868.XA Active CN112698715B (en) | 2020-12-17 | 2020-12-17 | Execution control method, device, embedded system, equipment and medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112698715B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103218205A (en) * | 2013-03-26 | 2013-07-24 | 中国科学院声学研究所 | Circular buffering device and circular buffering method |
| JPWO2012172694A1 (en) * | 2011-06-17 | 2015-02-23 | 富士通株式会社 | Arithmetic processing device, information processing device, and control method of arithmetic processing device |
| CN104714779A (en) * | 2013-12-12 | 2015-06-17 | 华为技术有限公司 | Command processing method and device |
| CN107003712A (en) * | 2014-12-27 | 2017-08-01 | 英特尔公司 | System low power state is enabled when computing element is movable |
| CN108491334A (en) * | 2018-03-08 | 2018-09-04 | 北京东土科技股份有限公司 | A kind of the physical memory management method and device of embedded real time system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9904623B2 (en) * | 2015-05-01 | 2018-02-27 | Advanced Micro Devices, Inc. | Early cache prefetching in preparation for exit from idle mode |
| EP4187881A1 (en) * | 2017-08-28 | 2023-05-31 | Bright Data Ltd. | Improving content fetching by selecting tunnel devices grouped according to geographic location |
-
2020
- 2020-12-17 CN CN202011500868.XA patent/CN112698715B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2012172694A1 (en) * | 2011-06-17 | 2015-02-23 | 富士通株式会社 | Arithmetic processing device, information processing device, and control method of arithmetic processing device |
| CN103218205A (en) * | 2013-03-26 | 2013-07-24 | 中国科学院声学研究所 | Circular buffering device and circular buffering method |
| CN104714779A (en) * | 2013-12-12 | 2015-06-17 | 华为技术有限公司 | Command processing method and device |
| CN107003712A (en) * | 2014-12-27 | 2017-08-01 | 英特尔公司 | System low power state is enabled when computing element is movable |
| CN108491334A (en) * | 2018-03-08 | 2018-09-04 | 北京东土科技股份有限公司 | A kind of the physical memory management method and device of embedded real time system |
Non-Patent Citations (4)
| Title |
|---|
| "Instruction fetch energy reduction using loop caches for embedded applications with small tight loops";Lea Hwang Lee等;《ACM》;第267-269页 * |
| "SoC存储子系统系统级性能优化技术研究";浦汉来;《中国优秀博硕士学位论文全文数据库 (博士) 信息科技辑》;第I137-9页 * |
| "The Application of Low Power Dissipation and Reconfigurable Technology on SoC Cache";Yilei Wang等;《IEEE》;第7222-7225页 * |
| "标志预访问和组选择历史相结合的低功耗指令cache";张宇弘等;《电子学报》(第08期);第1286-1289页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112698715A (en) | 2021-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102490908B1 (en) | Resource scheduling method and terminal device | |
| CN108665239B (en) | Workflow processing method, workflow processing device, computer equipment and storage medium | |
| US20140380101A1 (en) | Apparatus and method for detecting concurrency error of parallel program for multicore | |
| CN108459913B (en) | Data parallel processing method and device and server | |
| US9268609B2 (en) | Application thread to cache assignment | |
| KR102563165B1 (en) | Memory access request scheduling method, device, apparatus, and storage medium | |
| KR20150036684A (en) | Method and device for controlling terminal and terminal thereof | |
| US20130080809A1 (en) | Server system and power managing method thereof | |
| CN109446225B (en) | Data caching method and device, computer equipment and storage medium | |
| CN111723112A (en) | Data task execution method and device, electronic equipment and storage medium | |
| EP3422186B1 (en) | Method, device and system for preventing memory data loss | |
| CN112698715B (en) | Execution control method, device, embedded system, equipment and medium | |
| US20120180063A1 (en) | Method and Apparatus for Providing Management of Parallel Library Implementation | |
| US20160179716A1 (en) | Timer management apparatus | |
| US10310857B2 (en) | Systems and methods facilitating multi-word atomic operation support for system on chip environments | |
| US10621008B2 (en) | Electronic device with multi-core processor and management method for multi-core processor | |
| CN114153494B (en) | Hot code optimization method and device based on thermodynamic diagram | |
| Abdelmotalib et al. | Power management techniques in smartphones operating systems | |
| CN114020416A (en) | Large-page memory dynamic management method and device and computer equipment | |
| CN105183668B (en) | Cache flush method and device | |
| CN112346949A (en) | AOP-based operation log recording method and system, electronic device and medium | |
| US9489246B2 (en) | Method and device for determining parallelism of tasks of a program | |
| CN110688239A (en) | Model calling method, device, equipment and computer readable storage medium | |
| CN111817895B (en) | Master control node switching method, device, equipment and storage medium | |
| CN105740064A (en) | Method and device for preventing server from restarting in Linux system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |