CN112687656A - Semiconductor packaging structure and preparation method thereof - Google Patents
Semiconductor packaging structure and preparation method thereof Download PDFInfo
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- CN112687656A CN112687656A CN202110284566.1A CN202110284566A CN112687656A CN 112687656 A CN112687656 A CN 112687656A CN 202110284566 A CN202110284566 A CN 202110284566A CN 112687656 A CN112687656 A CN 112687656A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
- H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/24998—Reinforcing structures, e.g. ramp-like support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a semiconductor packaging structure and a preparation method thereof, wherein the structure comprises the following steps: a slide having a receiving recess; the chip to be bonded is mounted in the accommodating groove and forms a side wall gap; the side wall compensation bridging layer is connected with the chip and the surface of the slide glass and enables the side wall gap to be communicated with the outside; and the seed layer and the interconnection metal layer are formed on the side wall compensation bridging layer to realize the interconnection of the chip and the carrier. The invention is based on the design of a side wall compensation bridging layer, bridging is manufactured between the side wall of a cavity and the side wall of a chip, and subsequently prepared RDLs pass through the bridge deck. The invention can solve the problems that the gap is difficult to realize effective filling, bubbles exist in the filling and the like, and prevent the bubbles from influencing the subsequent packaging process. In addition, a smooth curved surface can be formed between the surface of the chip and the surface of the slide glass, and the subsequent interconnection is facilitated. The method has simple process, is suitable for chips with various thicknesses, and continuously provides guarantee for a subsequent seed layer while protecting the chip to be bonded, so that the subsequent electroplating process of the RDL can be carried out.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor packaging structure and a preparation method thereof.
Background
With the rapid development of the semiconductor industry, the radio frequency semiconductor module is widely applied to the fields of high-speed data communication, automobile radars, airborne missile tracking systems, space spectrum detection, imaging and the like, and becomes a new industry. The new application puts new requirements on the electrical performance, compact structure and system reliability of the product, and the wireless transmitting and receiving system cannot be integrated on the same chip (SOC) at present, so that different chips including a radio frequency unit, a filter, a power amplifier and the like need to be integrated into a separate system to realize the functions of transmitting and receiving signals.
The traditional mode of making radio frequency semiconductor module is through PCB board or ceramic substrate to different materials, and the chip of different functions is fixed through surface mounting and routing interconnection's mode, forms the radio frequency system module, but can increase the volume and the weight of radio frequency system like this. A novel semiconductor micro-system using a silicon-based semiconductor technology as a technical support directly mounts relevant chips on the surface of a wafer through a wafer-level chip mounting and wafer-level semiconductor interconnection process, and then RDL interconnection and signal fan-out are carried out through a wafer-level packaging process, however, the chips forming the micro-system and a carrier wafer are not on the same plane, and therefore processes such as RDL interconnection, ball mounting and the like after chip mounting cannot be effectively carried out.
However, for more advanced embedded interconnects, there is a gap between the embedded chip and the carrier wafer cavity, which is also not conducive to subsequent RDL interconnects. In the Fan-out packaging mode of high-density integration, chips with different thicknesses and sizes are embedded into a cavity of a carrier plate for fixation, and then RDL interconnection is performed on the surface. However, the gap between the cavity and the chip must be filled before RDL, providing support for RDL routing. Due to the fact that the thickness of the chip is different, the aspect ratio of the formed gap is also different, the existing glue filling process cannot meet gap filling formed by the chip with the overlarge thickness, if the gap cannot be filled normally, gas covered in the gap can be blown out, large bubbles are formed on the surface of the RDL, and therefore follow-up steps cannot be conducted. The vent holes are formed by exposure or etching processes, but the photoresist that is too thick is often not completely exposed or developed. The industry is then forced to apply thinning processes to the chips, but chip thinning presents problems of breakage and insufficient mechanical support.
Therefore, it is necessary to provide a semiconductor package structure and a method for fabricating the same to solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor package structure and a method for manufacturing the same, which are used to solve the problems in the prior art that it is difficult to effectively interconnect a chip in a carrier groove and a carrier.
To achieve the above and other related objects, the present invention provides a semiconductor package structure, comprising:
the slide glass is provided with a plurality of accommodating grooves;
the chip to be bonded is attached in the accommodating groove, the chip to be bonded is provided with a chip interconnection region, the slide is provided with a slide interconnection region, and a side wall gap is formed between the side wall of the chip to be bonded and the side wall of the accommodating groove;
the side wall compensation bridging layer is formed around the chip to be bonded and connected with the surface of the chip to be bonded and the surface of the slide glass, and the side wall compensation bridging layer is filled in the side wall gap and enables the side wall gap to be communicated with the outside;
the seed layer is continuously formed on the side wall compensation bridging layer, the chip interconnection area and the slide glass interconnection area;
and the interconnection metal layer is formed on the seed layer so as to connect the chip interconnection area and the slide glass interconnection area.
Optionally, the sidewall gap has an aspect ratio of between 2:1 and 10: 1.
Optionally, the depth of the accommodating groove is between 1-700 μm.
Optionally, a preset distance is formed between the bottom of the sidewall compensation bridging layer and the bottom of the accommodating groove, and the preset distance is greater than 0 and smaller than or equal to 690 μm.
Optionally, the material of the carrier includes any one of a wafer, glass, quartz, silicon carbide, alumina, epoxy resin, and polyurethane.
Optionally, the slide has a thickness between 200 μm and 2000 μm.
Optionally, the thickness of the chip to be bonded is between 50 and 690 μm.
Optionally, the material of the seed layer includes at least one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
Optionally, the seed layer has a thickness between 1nm and 100 μm.
Optionally, the sidewall compensation bridge layer includes a gel, and the gel includes at least one of a UV gel and a thermosetting gel.
Optionally, the sidewall compensation bridge layer includes a plurality of sidewall compensation bridge portions, and the sidewall compensation bridge portions are distributed at intervals around the to-be-bonded chip.
Optionally, the number of the chips to be bonded is at least two, and the chips to be bonded have different thicknesses and correspond to the sidewall gaps with different aspect ratios.
Optionally, an auxiliary compensation layer is formed between the chip to be bonded and the carrier, and the characteristics of the auxiliary compensation layer include at least one of the following conditions: A1) the auxiliary compensation layer comprises at least one of a copper-tin solder layer and a colloid layer; A2) the thickness of the auxiliary compensation layer is between 1 μm and 100 μm.
In addition, the invention also provides a preparation method of the semiconductor packaging structure, wherein the semiconductor packaging structure is preferably prepared by the preparation method of the packaging structure, and the preparation method comprises the following steps:
providing a slide glass, and manufacturing a plurality of accommodating grooves in the slide glass;
providing a chip to be bonded, and mounting the chip to be bonded in the accommodating groove in a pasting manner, wherein the chip to be bonded is provided with a chip interconnection region, the slide is provided with a slide interconnection region, and a side wall gap is formed between the side wall of the chip to be bonded and the side wall of the accommodating groove;
forming a side wall compensation bridging layer around the chip to be bonded, wherein the side wall compensation bridging layer is connected with the surface of the chip to be bonded and the surface of the slide glass, and the side wall compensation bridging layer is filled in the side wall gap and enables the side wall gap to be communicated with the outside;
preparing continuous seed layers on the surfaces of the chip to be bonded, the side wall compensation bridging layer and the slide glass;
preparing a graphical mask layer on the seed layer, wherein the graphical mask layer is provided with a target opening, and the target opening corresponds to the side wall compensation bridging layer, the chip interconnection area and the slide glass interconnection area so as to define a target interconnection area;
preparing an interconnection metal layer on the seed layer corresponding to the target interconnection region to connect the chip interconnection region and the slide interconnection region; and
and removing the graphical mask layer and the seed layer around the interconnection metal layer to obtain the packaging structure.
Optionally, the sidewall gap has an aspect ratio of between 2:1 and 10: 1.
Optionally, the depth of the accommodating groove is between 1-700 μm.
Optionally, the sidewall compensation bridge layer includes a plurality of sidewall compensation bridge portions, and the sidewall compensation bridge portions are distributed at intervals around the to-be-bonded chip.
Optionally, the forming manner of the sidewall compensation bridging layer includes any one of dispensing, spraying and screen printing.
Optionally, the number of the chips to be bonded is at least two, and the chips to be bonded have different thicknesses and correspond to the sidewall gaps with different aspect ratios.
Optionally, an auxiliary compensation layer is formed between the chip to be bonded and the carrier, and the characteristics of the auxiliary compensation layer include at least one of the following conditions: A1) the auxiliary compensation layer comprises at least one of a copper-tin solder layer and a colloid layer; A2) the thickness of the auxiliary compensation layer is between 1 μm and 100 μm.
As described above, the semiconductor package structure and the method for manufacturing the same according to the present invention are based on the design of the sidewall compensation bridging layer, the edge of the embedded chip is sealed with the glue, the glue forms a smooth curved surface between the surface of the chip and the surface of the carrier, and a bridge is formed between the sidewall of the cavity and the sidewall of the chip to allow the RDL to pass through the bridge surface. The problems that effective filling of gaps is difficult to achieve, bubbles exist in filling and the like can be solved, and the influence of the bubbles on a subsequent packaging process is prevented. The invention has simple process and is suitable for chips with various thicknesses. The chip to be bonded is protected, and meanwhile, the subsequent seed layer is continuously guaranteed, so that the subsequent electroplating process of the RDL can be carried out. The chip mounting interconnection process can greatly simplify the cost and the process difficulty of the signal fan-out process.
Drawings
Fig. 1 is a flow chart illustrating a process for fabricating a semiconductor package structure according to an embodiment of the present invention.
Fig. 2 to 12 are schematic structural diagrams obtained in the steps of manufacturing the package structure based on the method in the embodiment of the present invention.
Description of the element reference numerals
101-a slide; 101 a-a receiving recess; 101 b-sidewall gaps; 102-an auxiliary compensation layer; 103-chip to be bonded; 104-sidewall compensation bridge layer; 104 a-sidewall compensating bridge; 105-a seed layer; 106-a layer of masking material; 107-patterning the mask layer; 107 a-target window; 108-metal interconnect layer; s1 to S7.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In addition, "between … …" as used herein includes both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for manufacturing a semiconductor package structure, the method comprising:
s1, providing a slide, and manufacturing a plurality of accommodating grooves in the slide;
s2, providing a chip to be bonded, mounting the chip to be bonded in the accommodating groove, wherein the chip to be bonded is provided with a chip interconnection region, the slide is provided with a slide interconnection region, and a side wall gap is formed between the side wall of the chip to be bonded and the side wall of the accommodating groove;
s3, forming a sidewall compensation bridging layer around the chip to be bonded, wherein the sidewall compensation bridging layer connects the surface of the chip to be bonded and the surface of the slide, and the sidewall compensation bridging layer is filled in the sidewall gap and enables the sidewall gap to be communicated with the outside;
s4, preparing continuous seed layers on the surfaces of the chip to be bonded, the side wall compensation bridging layer and the slide;
s5, preparing a graphical mask layer on the seed layer, wherein the graphical mask layer is provided with a target opening, and the target opening corresponds to the side wall compensation bridging layer, the chip interconnection area and the slide glass interconnection area so as to define a target interconnection area;
s6, preparing an interconnection metal layer on the seed layer corresponding to the target interconnection area so as to connect the chip interconnection area and the slide chip interconnection area;
s7, removing the patterned mask layer and the seed layer around the interconnection metal layer to obtain the packaging structure.
The method for manufacturing a semiconductor package structure according to the present invention will be described in detail with reference to the accompanying drawings, wherein it should be noted that the above sequence does not strictly represent the manufacturing sequence of the method for manufacturing a semiconductor package structure protected by the present invention, and the skilled person can change the sequence according to the actual process steps, and fig. 1 represents only the manufacturing steps of the method for manufacturing a semiconductor package structure according to an example of the present invention.
First, as shown in S1 of fig. 1 and fig. 2, step S1 is performed to provide a slide 201, and a plurality of accommodating grooves 201a are formed in the slide 201.
By way of example, the carrier sheet comprises any one of a wafer, glass, quartz, silicon carbide, alumina, epoxy, and polyurethane. That is, the slide 101 may be a 4, 6, 8, 12 inch wafer. Of course, the carrier sheet 101 may be made of other materials, such as inorganic materials, e.g., glass, quartz, silicon carbide, alumina, etc., or organic materials, e.g., epoxy resin, polyurethane, etc., for providing a supporting function. In one example, the carrier itself is not conductive, and after the carrier is embedded in the chip, metal interconnection RDL lines are formed on the surfaces of the carrier and the chip to connect the chip and the carrier together. The carrier sheet may provide a supporting substrate for the chip.
By way of example, the slide 101 may have a thickness of between 200 and 2000 μm, and may be, for example, 400 μm, 500 μm, 800 μm, 1000 μm, 1200 μm, 1500 μm.
In addition, the accommodating grooves 101a may be formed by etching or the like, and the number and layout thereof are actually selected.
As an example, the depth of the receiving groove 101a is between 1-700 μm. For example, it may be 10 μm, 50 μm, 100 μm, 200 μm, 300 μm, 500 μm, 600 μm, 650 μm. In addition, the shape of the top view of the accommodating groove is square, circular, etc., but is not limited thereto.
Next, as shown in S2 of fig. 1 and fig. 3, step S2 is performed to provide a chip 103 to be bonded, and the chip 103 to be bonded is mounted in the accommodating groove 101a, and a sidewall gap 101b is formed between a sidewall of the chip 103 to be bonded and a sidewall of the accommodating groove 101 a. The number, the type, and the like of the chips 103 to be bonded can be selected according to practical requirements.
Wherein the chip to be bonded 103 has a chip interconnection area, and the chip 101 has a chip interconnection area. In one example, the chip to be bonded 103 has a chip interconnection surface, and the chip interconnection area is located on the chip interconnection surface; the slide 101 is provided with a slide interconnection surface, and the slide interconnection area is positioned on the slide interconnection surface; in this example, the chip interconnection surface is attached to the bottom of the accommodating groove in an opposite direction, and the chip interconnection surface and the carrier interconnection surface are located on the same horizontal plane.
In addition, the sidewall gap 101b may be formed around the chip to be bonded 103 and have a ring structure. In one example, the sidewall gap 101b has an aspect ratio of between 2:1 and 10:1, and may be 4:1, 5:1, 6:1, 7:1, 8:1, 9: 1. As is known, the aspect ratio may be a ratio of a depth of a certain position to a width of a corresponding position. In an alternative example, the aspect ratio of each position of the sidewall gap 101b is the same.
In one example, the thickness of the chip to be bonded 103 is between 50 μm and 690 μm, and may be 100 μm, 200 μm, 400 μm, 500 μm, 550 μm, 600 μm, 650 μm, for example.
As an example, an auxiliary compensation layer 102 is formed between the chip to be bonded 103 and the bottom surface of the accommodating recess 101 a.
As an example, the auxiliary compensation layer 102 characteristics include at least one of the following conditions: A1) the auxiliary compensation layer comprises at least one of a copper-tin solder layer and a colloid layer; A2) the thickness of the auxiliary compensation layer is between 1 and 100 mu m.
Specifically, the auxiliary compensation layer 102 is formed between the chip 103 to be bonded and the surface of the bottom of the accommodating groove 101a, and the auxiliary compensation layer 102 may serve as an adhesion layer to fix the chip 103 to be bonded and the carrier 101. In addition, based on the mode that the adhesion layer realizes surface mounting, the chip and the slide glass are effectively fixed, the simplification of subsequent packaging can be facilitated, the flexibility is provided for subsequent processes, and for example, the adhesive dispensing interconnection can be further facilitated.
The auxiliary compensation layer 102 may be formed of an initial material layer formed on a surface of at least one of the chip to be bonded 103 and a bottom of the receiving groove 101a of the carrier. That is, the auxiliary compensation layer 102 may be formed by applying glue to the cavity (accommodating groove) of the carrier or the surface of the chip to be bonded, and then the chip to be bonded 103 is mounted in the accommodating groove 101a of the carrier. The auxiliary compensation layer 102 may be a copper-tin solder or a colloid, the colloid may be a UV glue, a thermosetting glue, etc., where the colloid may also be a double-sided tape, leaving an intermediate adhesion layer.
Next, as shown in S3 in fig. 1 and fig. 4-5, step S3 is performed to form a sidewall compensation bridge layer 104 around the chip 103 to be bonded, where the sidewall compensation bridge layer 104 connects the surface of the chip 103 to be bonded and the surface of the carrier 101, and the sidewall compensation bridge layer 104 fills the sidewall gap 101b and connects the sidewall gap 101b with the outside.
Specifically, the sidewall compensation bridging layer 104 is designed to form a bridging region in the sidewall gap 101b around the chip 103 to be bonded, which is equivalent to form a bridge between the sidewall of the cavity and the sidewall of the chip, so that the subsequently prepared RDL passes through the bridge floor to connect the chip interconnection region and the carrier interconnection region, and the sidewall compensation bridging layer 104 is formed while maintaining the sidewall gap 101b to be communicated with the external atmosphere, thereby preventing the formation of filled bubbles. The above mode can effectively solve the packaging and interconnection of any chip with required thickness in the accommodating groove, can prevent the problem of bubbles generated in the gap filling process, prevents the bubbles from forming the influence on the subsequent process, does not need to change the thickness of the chip to be bonded, and can form effective interconnection packaging.
As an example, the number of the chips 103 to be bonded is at least two, and different thicknesses of the chips 103 to be bonded are different, and correspond to the sidewall gaps 101b with different aspect ratios.
That is to say, based on the scheme of this application, can effectual realization be at the integrated chip of different thickness on same slide, among the prior art, to having set up the recess of the different degree of depth on a slide, paste the condition of different thickness chips, be difficult to effectual realization effectively fills in the lateral wall clearance of different aspect ratios, be difficult to realize effectual integrated encapsulation, and the process based on the lateral wall compensation bridging layer of this application, can effectively solve above-mentioned problem. For example, in one example, there are three chips to be bonded, with thicknesses of 100 μm, 300 μm, 600 μm, respectively. Of course, the number and thickness of the chips can be selected according to actual needs.
By way of example, the sidewall compensation bridge layer 104 includes a glue including at least one of a UV glue and a thermosetting glue. In addition, through the side wall compensation bridging layer 104, a smooth curved surface can be further formed between the surface of the chip and the surface of the carrier, so that the formation of a subsequent seed layer and a metal interconnection layer is further facilitated, the subsequent seed layer is continuously ensured, and the subsequent electroplating process of the RDL is carried out. The colloid is made at the edge of the chip, the colloid is attached to the side wall of the chip after being solidified, and two ends of a curved surface formed by the colloid are connected with the front surface of the chip and the front surface of the slide glass, so that the process is simplified, and the interconnection of the chip and the slide glass is effectively realized. For example, the glue is applied to the edge of the chip by dispensing, and the glue may be UV glue, thermosetting glue, or the like. After the colloid is solidified, the gap between the chip and the cavity can be filled, so that the surface of the chip is interconnected with the surface of the carrier.
For example, the sidewall compensation bridge layer 104 may be formed by any one of dispensing, spraying, and screen printing. In an optional example, a dispensing mode is selected, so that the process is simplified, and the formation of a smooth curved surface is facilitated.
In addition, in an example, a predetermined distance is provided between the bottom of the sidewall compensation bridging layer 104 and the bottom of the receiving groove 101a, and the predetermined distance is greater than 0 and smaller than or equal to 690 μm, and may be, for example, 10 μm, 50 μm, 100 μm, 200 μm, or 400 μm. To further facilitate the improvement of defects based on filling bubbles.
In one example, the sidewall compensation bridging layer is formed only at the position where the chip and the slide glass need to be connected, so that the release of bubbles is effectively realized while the interconnection requirement is effectively realized, and the stability of the interconnection structure is ensured. For example, in a specific example, the sidewall compensation bridge portion is formed at a groove gap position through which a straight line formed by the chip interconnection region and the center of the chip interconnection region passes, for example, by dispensing.
As an example, the sidewall compensating bridge layer 104 (e.g., a gel) may have a height of 1 μm to 1000 μm. For example, it may be 10 μm, 50 μm, 100 μm, 200 μm, 500 μm, 600 μm, 800 μm, in order to ensure mechanical strength of the filled trench.
In addition, the thickness of the auxiliary compensation layer 102 is preferably between 20-80 μm, for example, 30 μm, 40 μm, 50 μm, 60 μm. Thereby facilitating the achievement of the effect of the sidewall-based compensation bridge layer 104 while achieving effective die attachment. In addition, in another optional example, the edge of the auxiliary compensation layer 102 exceeds the edge of the chip 103 to be bonded by a preset distance, and further, the auxiliary compensation layer 102 covers the entire surface of the bottom of the accommodating recess 101a, so as to prevent air bubbles from remaining.
In one example, the sidewall compensation bridge layer 104 is consistent with the material selection of the auxiliary compensation layer 102.
In another example, as shown in fig. 6 and 7, fig. 7 is a top view, and the sidewall compensation bridge layer 104 includes a plurality of sidewall compensation bridges 104a, and the sidewall compensation bridges 104a are spaced around the chip to be bonded 103. For example, in one example, the arrangement is provided in a uniformly spaced arrangement.
In one example, the chip interconnect region, and the sidewall compensation bridge are in one-to-one correspondence. For example, the chip to be bonded has a plurality of chip interconnection regions, the carrier has a plurality of carrier interconnection regions, and a sidewall compensation bridging portion is arranged between each chip interconnection region and the corresponding carrier interconnection region to realize the interconnection of the chip interconnection region and the carrier interconnection region.
Next, as shown in S4 of fig. 1 and fig. 8, step S4 is performed to prepare a continuous seed layer 205 on the surfaces of the chip to be bonded 103, the sidewall compensation bridge layer 104 and the carrier sheet 101.
As an example, the material of the deposited seed layer 105 may be at least one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel; the seed layer may be composed of one or more material layers.
In addition, in one example, the thickness of the seed layer 105 is between 1nm and 100 μm, and in a further example, the thickness may be between 100nm and 10 μm, such as 800nm, 1 μm, 5 μm, and 8 μm. In an example, the seed layer is formed on the surfaces of the carrier, the chip to be bonded, and the sidewall compensation bridge layer 104, and the above thickness design can further compensate the sidewall compensation bridge layer 104, which is beneficial to obtaining a continuous material layer on the basis of the sidewall compensation bridge layer 104, thereby facilitating the preparation of the subsequent interconnection metal.
Next, as shown in S5 of fig. 1 and fig. 9-10, step S5 is performed to prepare a patterned mask layer 107 on the seed layer 105, where the patterned mask layer 107 has a target opening 107a, and the target opening 207a at least corresponds to the sidewall compensation bridge layer 104, the chip interconnection region and the chip interconnection region, so as to define a target interconnection region.
In an example, the patterned mask layer 107 may be formed by first forming a mask material layer 106 on the structure on which the seed layer 105 is formed, as shown in fig. 9. Here, a photoresist may be coated or sprayed on the surface of the seed layer 105 as the mask material layer 106. Next, the masking material layer 106 is patterned, as shown in fig. 10. Wherein the pattern region may be defined by exposure and development.
As an example, the target opening 107a at least correspondingly exposes the sidewall compensation bridge layer 104, the chip interconnection region and the chip interconnection region, that is, the preferred opening area is larger than the projection areas of the sidewall compensation bridge layer 104, the chip interconnection region and the chip interconnection region, so as to effectively realize the interconnection between the chip and the chip.
Next, as shown in S6 of fig. 1 and fig. 11, step S6 is performed to form an interconnection metal layer 108 on the seed layer 105 corresponding to the target opening 107a to connect the chip interconnection region and the chip interconnection region. The chip to be bonded may have a pad thereon, the chip may also have a pad thereon that needs to be electrically connected, and the seed layer and the metal interconnection layer may be electrically connected to both the chip to be bonded and the pad on the chip, except for covering the sidewall compensation bridge layer.
By way of example, the interconnect metal layer 108 may be deposited using an electroplating process. In one example, the thickness of the interconnect metal layer 108 is between 1nm and 100 μm, and may be 100nm or 500 nm. In addition, the interconnection metal layer 108 may alternatively be formed by one or more layers of materials, and the metal material may be at least one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc., may be a single layer of material, or may be a multi-layer stack of one or more layers.
Finally, as shown in S7 in fig. 1 and fig. 12, step S7 is performed to remove the patterned mask layer 107 and the seed layer 105 around the interconnection metal layer 108, so as to obtain the package structure. In this step, the photoresist and seed layer are removed, for example, to complete the electrical interconnection of the chip and the carrier. The removal process may employ existing processes for material selection.
In addition, as shown in fig. 12 and referring to fig. 1 to 11, the present invention further provides another semiconductor package structure, wherein the package structure is preferably prepared by the method for preparing the package structure in the embodiment of the present invention, but may be prepared by other methods. The characteristics and descriptions of the material layers in the package structure can be referred to the description of the method for manufacturing the package structure in this embodiment, and are not repeated herein.
Wherein, the semiconductor packaging structure includes:
the slide glass 101, wherein a plurality of accommodating grooves 101a are formed in the slide glass;
a chip to be bonded 103 formed in the accommodating groove 101a, the chip to be bonded having a chip interconnection region, the carrier having a carrier interconnection region, and a sidewall gap 101b formed between a sidewall of the chip to be bonded and a sidewall of the accommodating groove;
a sidewall compensation bridge layer 104 formed around the chip 103 to be bonded and connecting the surface of the chip 103 to be bonded and the surface of the carrier 101, wherein the sidewall compensation bridge layer 104 is filled in the sidewall gap 101b and makes the sidewall gap 101b communicate with the outside;
a seed layer 105 continuously formed on the sidewall compensation bridge layer 104, the chip interconnection region and the slide interconnection region; the seed layer 105 is a seed layer remaining after the patterned mask layer and a part of the seed layer are removed after the interconnection metal layer is formed;
and the interconnection metal layer 108 is formed on the seed layer and is connected with the chip interconnection area and the slide glass interconnection area.
By way of example, the sidewall gap has an aspect ratio of between 2:1 and 10: 1.
As an example, the depth of the receiving groove 101a is between 1-700 μm.
By way of example, the thickness of the bonded chip 103 is between 50-690 μm.
As an example, the material of the seed layer 105 includes at least one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel.
Illustratively, the seed layer 105 has a thickness of between 1nm and 100 μm.
By way of example, the sidewall compensation bridge layer 104 includes a glue including at least one of a UV glue and a thermosetting glue.
As an example, a predetermined distance is formed between the bottom of the sidewall compensation bridge layer 104 and the bottom of the receiving groove 101a, and the predetermined distance is greater than 0 and smaller than or equal to 690 μm.
As an example, the sidewall compensation bridge layer 104 includes several sidewall compensation bridge portions 104a, and the sidewall compensation bridge portions are distributed at intervals around the to-be-bonded chip.
As an example, an auxiliary compensation layer 102 is formed between the chip to be bonded and the accommodating groove.
As an example, the number of the chips to be bonded is at least two, and the chips to be bonded have different thicknesses and correspond to the sidewall gaps with different aspect ratios.
As an example, the auxiliary compensation layer characteristic comprises at least one of the following conditions:
A1) the auxiliary compensation layer comprises at least one of a copper-tin solder layer and a colloid layer; A2) the thickness of the auxiliary compensation layer is between 1 and 100 mu m. Preferably, both conditions occur simultaneously.
In summary, the semiconductor package structure and the method for manufacturing the same according to the present invention are based on the design of the sidewall compensation bridging layer, the edge of the embedded chip is sealed with the glue, the glue forms a smooth curved surface between the surface of the chip and the surface of the carrier, and a bridge is formed between the sidewall of the cavity and the sidewall of the chip, so that the subsequently manufactured RDL can pass through the bridge floor. The problems that effective filling of gaps is difficult to achieve, bubbles exist in filling and the like can be solved, and the influence of the bubbles on a subsequent packaging process is prevented. The invention has simple process and is suitable for chips with various thicknesses. The chip to be bonded is protected, and meanwhile, the subsequent seed layer is continuously guaranteed, so that the subsequent electroplating process of the RDL can be carried out. The chip mounting interconnection process can greatly simplify the cost and the process difficulty of the signal fan-out process. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A semiconductor package, comprising:
the slide glass is provided with a plurality of accommodating grooves;
the chip to be bonded is attached in the accommodating groove, the chip to be bonded is provided with a chip interconnection region, the slide is provided with a slide interconnection region, and a side wall gap is formed between the side wall of the chip to be bonded and the side wall of the accommodating groove;
the side wall compensation bridging layer is formed around the chip to be bonded and connected with the surface of the chip to be bonded and the surface of the slide glass, and the side wall compensation bridging layer is filled in the side wall gap and enables the side wall gap to be communicated with the outside;
the seed layer is continuously formed on the side wall compensation bridging layer, the chip interconnection area and the slide glass interconnection area;
and the interconnection metal layer is formed on the seed layer so as to connect the chip interconnection area and the slide glass interconnection area.
2. The semiconductor package structure of claim 1, wherein the sidewall gap has an aspect ratio of between 2:1 and 10: 1; and/or the depth of the accommodating groove is between 1 and 700 mu m.
3. The semiconductor package structure of claim 1, wherein a predetermined distance is provided between the bottom of the sidewall compensation bridge layer and the bottom of the receiving groove, and the predetermined distance is greater than 0 and smaller than or equal to 690 μm.
4. The semiconductor package structure of claim 1, wherein the carrier comprises any one of a wafer, glass, quartz, silicon carbide, alumina, epoxy resin, and polyurethane; and/or the thickness of the slide glass is between 200 and 2000 mu m; and/or the thickness of the chip to be bonded is between 50 and 690 mu m.
5. The semiconductor package structure of claim 1, wherein the seed layer comprises at least one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, and nickel; and/or the thickness of the seed layer is between 1nm and 100 mu m.
6. The semiconductor package structure of claim 1, wherein the sidewall compensation bridge layer comprises a glue, the glue comprising at least one of a UV glue and a thermosetting glue.
7. The semiconductor package structure of claim 1, wherein the sidewall compensation bridge layer comprises a plurality of sidewall compensation bridge portions, and the sidewall compensation bridge portions are spaced around the chip to be bonded.
8. The semiconductor package structure of claim 1, wherein the number of the chips to be bonded is at least two, and the thickness of the chips to be bonded is different and corresponds to the sidewall gaps with different aspect ratios.
9. The semiconductor package structure of any one of claims 1-8, wherein an auxiliary compensation layer is formed between the chip to be bonded and the carrier, and the characteristics of the auxiliary compensation layer include at least one of the following conditions: A1) the auxiliary compensation layer comprises at least one of a copper-tin solder layer and a colloid layer; A2) the thickness of the auxiliary compensation layer is between 1 μm and 100 μm.
10. A preparation method of a semiconductor packaging structure is characterized by comprising the following steps:
providing a slide glass, and manufacturing a plurality of accommodating grooves in the slide glass;
providing a chip to be bonded, and mounting the chip to be bonded in the accommodating groove in a pasting manner, wherein the chip to be bonded is provided with a chip interconnection region, the slide is provided with a slide interconnection region, and a side wall gap is formed between the side wall of the chip to be bonded and the side wall of the accommodating groove;
forming a side wall compensation bridging layer around the chip to be bonded, wherein the side wall compensation bridging layer is connected with the surface of the chip to be bonded and the surface of the slide glass, and the side wall compensation bridging layer is filled in the side wall gap and enables the side wall gap to be communicated with the outside;
preparing continuous seed layers on the surfaces of the chip to be bonded, the side wall compensation bridging layer and the slide glass;
preparing a graphical mask layer on the seed layer, wherein the graphical mask layer is provided with a target opening, and the target opening corresponds to the side wall compensation bridging layer, the chip interconnection area and the slide glass interconnection area so as to define a target interconnection area;
preparing an interconnection metal layer on the seed layer corresponding to the target interconnection region to connect the chip interconnection region and the slide interconnection region; and
and removing the graphical mask layer and the seed layer around the interconnection metal layer to obtain the packaging structure.
11. The method of claim 10, wherein the sidewall gap has an aspect ratio of 2:1 to 10: 1; and/or the depth of the accommodating groove is between 1 and 700 mu m; and/or the side wall compensation bridging layer comprises a plurality of side wall compensation bridging parts which are distributed on the periphery side of the chip to be bonded at intervals.
12. The method of claim 10, wherein the number of the chips to be bonded is at least two, and the chips to be bonded have different thicknesses and correspond to the sidewall gaps with different aspect ratios.
13. The method of claim 10, wherein the sidewall compensation bridge layer is formed by any one of dispensing, spraying and screen printing.
14. The method for manufacturing a semiconductor package structure according to any one of claims 10 to 13, wherein an auxiliary compensation layer is formed between the chip to be bonded and the carrier, and the characteristics of the auxiliary compensation layer include at least one of the following conditions: A1) the auxiliary compensation layer comprises at least one of a copper-tin solder layer and a colloid layer; A2) the thickness of the auxiliary compensation layer is between 1 μm and 100 μm.
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