CN112687456A

CN112687456A - Switching transformer and electronic system including the same

Info

Publication number: CN112687456A
Application number: CN202011091329.5A
Authority: CN
Inventors: 郑元准; 姜昇勋; 孙基龙
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2019-10-18
Filing date: 2020-10-13
Publication date: 2021-04-20
Also published as: DE102020123684A1

Abstract

Switching transformers and electronic systems including switching transformers are provided. A switching transformer, comprising: a driver amplifier configured to output an input signal by amplifying a source signal; a primary circuit comprising a primary inductor bank, a primary switch, and a first primary connection line, the primary inductor bank configured to receive the input signal at a first primary input/output terminal, the primary switch configured to adjust an inductance of the primary inductor bank based on a first switching operation, and the first primary connection line configured to electrically connect the first primary input/output terminal to a first end of the primary switch; and a secondary circuit configured to electromagnetically couple to each other the first primary connection line and at least one primary inductor of the primary inductor group.

Description

Switching transformer and electronic system including the same

Cross Reference to Related Applications

This application claims the benefit of korean patent application No. 10-2019-.

Technical Field

Example embodiments relate to a switching transformer, and more particularly, to a switching transformer used in a transmitter and/or a receiver for wireless communication.

Background

The transformer may electromagnetically couple the primary circuit to the secondary circuit with a coupling coefficient via magnetic fluxes generated by alternating currents flowing in the primary coil and the secondary coil.

As the price of packaging increases, the chip size of Radio Frequency Integrated Circuits (RFICs) used for wireless mobile communications becomes smaller. Another consideration is that RFICs used for wireless mobile communications are capable of producing the required output at low power. Recently, as mobile communication has evolved from third generation (3G) to Long Term Evolution (LTE) to fifth generation (5G), the size of an RFIC chip has increased to maintain high power efficiency even with signal characteristics having a high peak-to-average power ratio (PAPR).

An RFIC for wireless communication may include a transformer supporting 5G and multiple links (e.g., Radio Frequency (RF) links) supporting different frequencies.

According to the related art, the RFIC may obtain the target bandwidth by controlling the capacitance of the transformer at the output terminal to have the target frequency range. However, such RFICs can only obtain limited bandwidth. In addition, since it is difficult to control the inductance of the transformer, the load size is fixed, thereby reducing power efficiency.

The inductance or capacitance of the transformer may be reduced to increase the bandwidth, but there is a structural limitation in reducing the capacitance and parasitic capacitance of the drain of the driving amplifier.

A switch may be provided between the inductors of the transformer to reduce the inductance. However, the transmitter has a large output power, linearity is important for the transmitter, and as the process size is reduced, it is more difficult to implement the transmitter. Therefore, it is difficult to provide a switch between inductors in the existing structure. For example, the reliability of the switch may be reduced due to the large output power. Further, when the transformer of the transmitter includes a switch, magnetic flux may be lost due to the switch, and the coupling coefficient may be reduced.

Disclosure of Invention

Example embodiments provide a switching transformer including a connection line having a meta structure to increase a coupling coefficient between a primary circuit and a secondary circuit, and an electronic system including the switching transformer.

Example embodiments also provide a switching transformer including a switch having a plurality of transistors connected in series with each other through source/drain terminals thereof to increase reliability of the switch, and an electronic system including the switching transformer.

Example embodiments also provide a switching transformer capable of matching impedances between circuits respectively connected to input and output terminals of a driving amplifier, and an electronic device including the switching transformer.

According to an example embodiment, there is provided a switching transformer, including: a driver amplifier configured to output an input signal by amplifying a source signal; a primary circuit comprising a primary inductor bank, a primary switch, and a first primary connection line, the primary inductor bank configured to receive the input signal at a first primary input/output terminal, the primary switch configured to adjust an inductance of the primary inductor bank based on a first switching operation, and the first primary connection line configured to electrically connect the first primary input/output terminal to a first end of the primary switch; and a secondary circuit configured to electromagnetically couple to each other the first primary connection line and at least one primary inductor of the primary inductor group.

According to an example embodiment, there is provided an electronic system comprising: a mixer configured to output a source signal based on frequency translation; a driver amplifier configured to output an input signal by amplifying the source signal; a drive input circuit comprising an input capacitor, an input inductor bank, and an input switch, and electrically connected to the input terminal of the drive amplifier, the input switch configured to adjust an inductance of the input inductor bank based on a first switching operation; a primary circuit comprising a primary inductor bank, a primary switch, and a first primary connecting line, the primary inductor bank configured to receive the input signal at a first primary input/output terminal, the primary switch configured to adjust an inductance of the primary inductor bank based on a second switching operation, and the first primary connecting line configured to electrically connect the first primary input/output terminal to a first end of the primary switch; and a processing circuit configured to control the first switching operation and the second switching operation.

According to an example embodiment, there is provided an electronic system comprising: a primary circuit comprising a primary inductor bank, a primary switch, and a primary connecting line, the primary inductor bank configured to receive an input signal at a primary input/output terminal, the primary switch configured to adjust an inductance of the primary inductor bank based on a first switching operation, and the primary connecting line configured to electrically connect the primary input/output terminal to one end of the primary switch; a secondary circuit including a secondary inductor group, a secondary switch, and a secondary connection line, the secondary circuit being electromagnetically coupled to the primary connection line and at least one of the primary inductors of the primary inductor group, the secondary inductor group being configured to output a signal induced from the primary circuit to a secondary input/output terminal electrically connected to a load, the secondary switch being configured to adjust an inductance of the secondary inductor group based on a second switching operation, and the secondary connection line being configured to electrically connect the secondary input/output terminal to one end of the secondary switch; and a processing circuit configured to control at least one of the first switching operation and the second switching operation based on at least one of a frequency of the input signal and a size of the load.

Drawings

Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a block diagram for describing a Radio Frequency Integrated Circuit (RFIC) according to an example embodiment;

FIG. 2 is a circuit diagram depicting a switching transformer module according to an example embodiment;

fig. 3A and 3B are circuit diagrams for describing a switching operation of an input switch according to an example embodiment;

FIG. 4 is a block diagram depicting a switching transformer circuit according to an example embodiment;

FIG. 5 is a circuit diagram for describing a switch transformer circuit according to an example embodiment;

fig. 6A and 6B are diagrams for describing a primary circuit according to an example embodiment;

FIG. 7 is a circuit diagram of a stacked switch according to an example embodiment;

fig. 8A and 8B are diagrams for describing a secondary circuit according to an example embodiment;

fig. 9A and 9B are diagrams for describing a secondary circuit further including secondary connection lines as compared with fig. 8A and 8B;

fig. 10A to 11B are diagrams for describing a primary circuit and a secondary circuit according to example embodiments;

fig. 12A to 12D are circuit diagrams of a primary circuit in a primary switching operation and a secondary circuit in a secondary switching operation according to example embodiments;

fig. 13 is a block diagram of a communication device according to an example embodiment.

Detailed Description

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram for describing a Radio Frequency Integrated Circuit (RFIC) according to an example embodiment.

Referring to fig. 1, an electronic system 1000 may include a switching transformer module 1, a filter 2, a mixer 3, a phase-locked loop (PLL)4, and/or a load 5. The switching transformer module 1 may include a plurality of switches, for example, an input switch SW0, a primary switch SW1, and/or a secondary switch SW 2. For example, electronic system 1000 may correspond to an RFIC, or may be included in a transmitter and/or receiver of an RFIC. However, for ease of description, the electronic system 1000 is shown as being included in a transmitter.

According to an example embodiment, the switching transformer module 1 may perform a switching operation based on the received signal. For example, the switching transformer module 1 may adjust the inductance value and/or the capacitance value by controlling at least one of the input switch SW0, the primary switch SW1, and/or the secondary switch SW2 based on the frequency of the received signal. The switching transformer module 1 may also perform a switching operation based on the load size. For example, the switching transformer module 1 may adjust the inductance value and/or the capacitance value by controlling at least one of the input switch SW0, the primary switch SW1, and/or the secondary switch SW2 based on the impedance value of the load 5.

The electronic system 1000 may receive an external signal SX through an input terminal of the filter 2 to send the signal to the load 5. For example, the filter 2 may receive the first external signal SX1 and the second external signal SX2 through differential input terminals. The filter 2 may be a circuit configured to control the amplitude and/or phase of the external signal SX, and may include at least one selected from, for example, a low-pass filter, a band-pass filter, and/or a high-pass filter. The filter 2 may output the filtered signal SF by filtering the external signal SX. The filter 2 may output the first filtered signal SF1 and the second filtered signal SF2 through differential output terminals.

The mixer 3 may frequency-convert the filtered signal SF based on the reference signal output from the PLL 4, and may output the source signal SS based on the frequency conversion. For example, the mixer 3 may perform up-conversion on the filtered signal SF (e.g., the first filtered signal SF1 and the second filtered signal SF2) based on the frequency of the reference signal output from the PLL 4. The mixer 3 may output the first source signal SS1 and the second source signal SS2 as a result of the up-conversion.

According to an example embodiment, the switching transformer module 1 may adjust the impedance value by opening or closing the input switch SW0 based on the frequency of the source signal SS. For example, the switching transformer module 1 may adjust the magnitude of the input impedance by resonating the input impedance using the frequency of the source signal SS. The input impedance may comprise the impedance seen when looking from the mixer 3 towards the driver amplifier of the switching transformer module 1. Accordingly, the driving amplifier can smoothly perform an amplifying or driving operation. This will be described below with reference to fig. 2.

According to an example embodiment, the switching transformer module 1 may adjust the mutual inductance of the primary circuit and the secondary circuit by opening or closing at least one of the primary switch SW1 and/or the secondary switch SW2 based on the frequency of the source signal SS. For example, the switching transformer module 1 may reduce the inductance of the primary circuit by closing the primary switch SW1, and the primary switch SW1 may be connected in parallel to at least one inductor of a plurality of inductors included in the primary circuit. The secondary switch SW2 may be similar to the primary switch SW1 described above. This will be described below with reference to fig. 4.

Fig. 2 is a circuit diagram depicting a switching transformer module according to an example embodiment.

Referring to fig. 2, the switching transformer module 1 may include a switching transformer circuit 10, a Driving Amplifier (DA)20, and/or a driving input circuit 30. The drive input circuit 30 may include a plurality of input inductors LI 1-LI 3 (which may also be referred to herein as input inductors or input inductor groups), an input capacitor CI (e.g., a variable capacitor), and/or an input switch SW 0. Electronic system 1000 may also include control logic 40. According to an example embodiment, the control logic 40 may include a storage device (e.g., a memory) configured to store (e.g., include a look-up table (LUT)) information about the frequency of the input signal SI and/or information about the impedance of the load 5.

According to an example embodiment, the driving input circuit 30 may be connected in parallel to the input terminal of the DA20, and may control the input capacitor CI and the input switch SW0 based on the first control command CTR 1. The drive input circuit 30 may adjust the capacitance value of the input capacitor CI based on the electrical signal included in the first control command CTR 1. The input capacitor CI may be implemented by a capacitor bank including a plurality of capacitor elements. The input switch SW0 may be connected in parallel to at least one of the input inductors LI 1-LI 3, e.g., input inductor LI 2. The input switch SW0 may be opened or closed based on an electrical signal included in the first control command CTR 1. In other words, the control logic 40 may send a first control command CTR1 to the drive input circuit 30, which first control command CTR1 indicates the capacitance value of the input capacitor CI and the opening or closing of the input switch SW 0. In an example embodiment, the source signals SS (e.g., the first source signal SS1 and the second source signal SS2) may be amplified by the DA20 to generate the input signals SI (e.g., the first input signal SI1 and the second input signal SI 2). The driving input circuit 30 can change equivalent or similar inductance values of the input inductors LI1 to LI3 by controlling the input switch SW0, and can control impedance viewed from the DA20 by adjusting capacitance values of the input capacitors CI connected in parallel to the input inductors LI1 to LI 3. Accordingly, an appropriate load impedance can be provided to the switching transformer circuit 10, and the unit cell (unit cell) of the DA20 can be turned on according to the fixed load impedance, so that the target output voltage can be generated.

Fig. 3A and 3B are circuit diagrams for describing a switching operation of an input switch according to an example embodiment.

Referring to fig. 2 through 3B, the control logic 40 may open or close the input switch SW0 and/or adjust the magnitude of the input impedance ZIa or ZIb (e.g., the input impedance ZI) according to the frequency of the source signal SS.

The control logic 40 may generate an impedance value that may minimize or reduce the power consumption of the DA20 by resonating the input capacitor CI and the input inductors LI1 to LI3, which are connected in parallel with each other. In the case where the drive input circuit 30 includes only the input capacitor CI and no input inductors LI 1-LI 3, the impedance value seen at DA20 decreases as the frequency increases. As the impedance value decreases, the magnitude of the input current increases, which may increase power consumption. Therefore, when the input impedance value is increased by generating resonance between the input inductors LI1 to LI3 and the input capacitor C1, a rapid increase in high-frequency input current can be prevented or reduced, thereby reducing power consumption. When the impedance value of the drive input circuit 30 connected in parallel with the mixer 3 and DA20 increases, the magnitude of the input impedance ZIa may also increase. DA20 may output input signal SI by effectively driving source signal SS based on input impedance ZIa, which has increased.

Referring to fig. 2 and 3A, when the frequency of the source signal SS is less than a preset frequency or a given frequency (e.g., a frequency value and/or a threshold value), the control logic 40 may control the driving input circuit 30 to have a target resonant impedance at a target frequency by opening the input switch SW 0. For example, the frequency of the source signal SS may be in an ultra high frequency band (UHB) for wireless communication, and may be in a frequency band from about 3.3GHz to about 4.6 GHz. When the input switch SW0 is turned off, the total inductance of the driving input circuit 30 may be increased by the input inductors LI1 to LI3 connected in series with each other. The frequency of the source signal SS may correspond to the resonant frequency of the drive input circuit 30. Because the resonant frequency is relatively low, the control logic 40 may increase the number of inductors. This is because the resonant frequency is inversely proportional to the inductance and capacitance as shown below.

[ equation 1]

In equation 1, ω_rMay be a resonant frequency (e.g., the frequency of the source signal SS), L may be an inductance (e.g., the total inductance of the input inductors LI 1-LI 3), and C may be a capacitance (e.g., the capacitance of the input capacitor CI). In other words, the drive input circuit 30 can be controlled to resonate at or closer to the frequency of the source signal SS by increasing the inductance. Adjusting the inductance value by controlling input switch SW0 may be referred to as coarse tuning.

After increasing the inductance of the drive input circuit 30 by opening the input switch SW0, the control logic 40 may adjust the capacitance of the input capacitor C1. For example, to finely adjust the frequency range of the drive input circuit 30, the control logic 40 may perform fine tuning by adjusting the capacitance. In other words, the control logic 40 may perform coarse tuning by adjusting the inductance to a wide range by opening or closing the input switch SW0, and may perform fine tuning by adjusting the capacitance of the input capacitor C1 to a narrow range. For example, coarse tuning may be performed to change the resonance frequency to another frequency band by controlling the inductance within a wide range, and fine tuning is provided to change the resonance frequency to a target frequency in the frequency band. When a number of switches are provided in the input inductors LI1 to LI3 connected in series with each other, an equivalent or similar inductance can be finely adjusted. However, the use of many switches results in increased power consumption. Thus, a wide frequency range may be first adjusted via coarse tuning of the control inductance, and then fine tuning may be performed to approach a particular frequency range through the variable capacitance.

Referring to fig. 2 and 3B, when the frequency of the source signal SS is greater than or equal to a preset frequency or a given frequency (e.g., a frequency value and/or a threshold value), the control logic 40 may close the input switch SW 0. For example, the frequency of the source signal SS may be in an enhanced licensed assisted access (eLAA) frequency band for wireless communication, and may be in a frequency band from about 4.4GHz to about 6 GHz. When the input switch SW0 is closed, a current path to the input inductor LI2 is not established and the total inductance of the drive input circuit 30 may be reduced. Because the resonant frequency is relatively high, the control logic 40 may reduce the number of inductors.

After reducing the inductance of the drive input circuit 30 by closing the input switch SW0, the control logic 40 may adjust the capacitance of the input capacitor C1. For example, to finely adjust the frequency range of the drive input circuit 30, the control logic 40 may perform fine tuning by adjusting the capacitance.

Referring back to fig. 2, the control logic 40 may control the input switch SW0 driving the input circuit 30 to optimize or improve the input impedance ZI according to the frequency of the source signal SS. Thus, the DA20 may cover various frequency values of the source signal SS. DA20 may amplify source signal SS and output input signal SI, and switching transformer circuit 10 may perform voltage conversion based on second control signal CTR 2. According to an example embodiment, the control logic 40 may include a look-up table (LUT). The LUT may refer to a mapping table that stores predetermined values or given values of control signals (e.g., the first control signal CTR1 and/or the second control signal CTR2) for each frequency band of an input signal (e.g., the source signal SS). For example, when the frequency of the source signal SS corresponds to the n77 frequency band of 3.7GHz, the control logic 40 may output a control signal mapped to the n77 frequency band. In another example, when the frequency of the source signal SS corresponds to the n79 frequency band of 4.7GHz, the control logic 40 may output a control signal mapped to the n79 frequency band. When the frequency corresponds to the n77 frequency band, the control signal output should resonate at a relatively low frequency, as compared with the case where the frequency corresponds to the n79 frequency band, and thus may include information indicating to turn off the input switch SW0 that drives the input circuit 30.

Fig. 4 is a block diagram for describing a switching transformer circuit according to an example embodiment.

Referring to fig. 4, the switching transformer circuit 10 may include a primary circuit 110 and a secondary circuit 120 that are electromagnetically coupled to each other based on a coupling coefficient "k". The primary circuit 110 may include a primary switch SW1, and the secondary circuit 120 may include a secondary switch SW 2.

The DA20 may provide the input signal SI to the primary circuit 110. The primary circuit 110 may generate a magnetic flux based on the input signal SI, and the secondary circuit 120 may generate the output signal SO based on the magnetic flux. In this case, the control logic 40 may provide the second control signal CTR2 to close or open the primary switch SW1 and/or the secondary switch SW2, which may adjust the inductance of the primary circuit 110 and the inductance of the secondary circuit 120, respectively.

Fig. 5 is a circuit diagram for describing a switching transformer circuit according to an example embodiment.

Referring to fig. 5, the primary circuit 110 may include a primary input/output (I/O) terminal IT, a primary capacitor CP, a plurality of primary inductors LP1, LP2, and/or LP3 (the third primary inductor may also be referred to herein as a primary connection line LP3), and/or a primary switch SW 1. The secondary circuit 120 may include a secondary I/O terminal OT, a plurality of secondary inductors LS1, LS2, and/or LS3 (the third secondary inductor may also be referred to herein as a secondary connection line LS3), and/or a secondary switch SW 2.

Referring to fig. 4 and 5, the primary circuit 110 may include a primary I/O terminal IT, which may include differential input terminals, e.g., a first primary I/O terminal IT1 and a second primary I/O terminal IT 2. The input signals SI may include a first input signal SI1 and a second input signal SI 2. The primary circuit 110 may receive the first input signal SI1 and the second input signal SI2 through differential input terminals (e.g., a first primary I/O terminal IT1 and a second primary I/O terminal IT2), respectively. The first and second input signals SI1 and SI2 may correspond to the in-phase (I) and quadrature-phase (Q) signals, respectively, amplified by DA 20. The secondary circuit 120 may include a secondary I/O terminal OT, which may be a single output terminal. The output signal SO may comprise a single-ended signal and the secondary circuit 120 may output the output signal SO to the load 5 through the secondary I/O terminal OT.

The primary capacitor CP may be connected in parallel to the primary I/O terminal IT. For example, the primary capacitor CP may be connected in parallel to the first primary I/O terminal IT1 and the second primary I/O terminal IT 2. The primary capacitor CP may also be connected in parallel to the primary inductor LP. The primary capacitor CP may be a variable capacitor whose capacitance is adjusted according to the frequency of the input signal SI when the inductance is adjusted by the switching operation of the primary switch SW1 and/or the secondary switch SW 2. For example, the control logic 40 may adjust the capacitance of the primary capacitor CP based on the second control signal CTR 2.

Fig. 6A and 6B are diagrams for describing a primary circuit according to an example embodiment.

Referring to fig. 5-6B, the plurality of primary inductors (which may also be referred to herein as primary inductors LP and/or primary inductor groups) may include a first primary inductor LP1 and a second primary inductor LP 2. The primary circuit 110 may include a primary connection line LP 3.

Referring to fig. 6A and 6B, the primary inductor LP may be connected to a primary I/O terminal IT, and the primary I/O terminal IT may receive the input signal SI through differential terminals (e.g., a first primary I/O terminal IT1 and a second primary I/O terminal IT2 terminal). In detail, both ends of the primary inductor LP may be electrically connected to the first and second primary I/O terminals IT1 and IT2, respectively.

The primary connection line LP3 may include a first primary connection line LP3a and a second primary connection line LP3 b. The first primary connection line LP3a may be electrically connected to the first primary I/O terminal IT1 and to one end of the primary switch SW1 through the first node N1, and the second primary connection line LP3b may be electrically connected to the second primary I/O terminal IT2 and to an opposite end of the primary switch SW1 through the second node N2.

The primary connection line LP3 may have an inter-digit structure with respect to the first primary inductor LP 1. For example, the primary connection line LP3 may extend parallel to one side of the first primary inductor LP1 and thus generate a magnetic flux in a direction that reinforces the magnetic flux of the first primary inductor LP 1. Therefore, the coupling coefficient between the primary circuit 110 and the secondary circuit 120 may be increased compared to when the primary connection line LP3 is not present.

The inductance value of the primary connection line LP3 may be equal to or substantially equal to the inductance value of the primary inductor LP. In other words, the inductance value of the primary connection line LP3 may be equal to or substantially equal to the sum of the inductance value of the first primary inductor LP1 and the inductance value of the second primary inductor LP 2. The width of the primary connection line LP3 may be less than the width of the primary inductor LP. For example, the width of the first primary inductor LP1 may be equal or substantially equal to the width of the second primary inductor LP2, and the width of the primary connection line LP3 may be less than the width of each of the first primary inductor LP1 and the second primary inductor LP 2. As described above, it is observed through repeated experiments that the coupling coefficient is increased due to the inductance value and the width of the primary connection line LP 3.

The primary connection line LP3 and the primary inductor LP may be formed on a first semiconductor layer, and the primary switch SW1 may be formed on a second semiconductor layer stacked on the first semiconductor layer. However, example embodiments are not limited thereto, and the first semiconductor layer may be stacked on the second semiconductor layer. The first substrate on which the primary connection line LP3 and the primary inductor LP are formed may be on a different layer from the second substrate on which the primary switch SW1 is formed. In this way, the volume of the primary circuit 110 can be reduced, and the integration of the switching transformer circuit 10 can be improved. The primary connection line LP3 and the primary inductor LP may be connected to the primary switch SW1 located on a different layer through a conductive via structure filling a via hole. Example embodiments are not limited to the particular structure, materials, and electrical characteristics of the via and conductive via structures.

The primary switch SW1 may perform a switching operation (on or off) based on the frequency of the input signal SI. The primary switch SW1 may be connected to a portion of the primary inductor LP to adjust the total inductance of the primary inductor LP based on the switching operation. The control logic 40 may receive information about the frequency of the input signal SI, which information is stored in a storage means. Alternatively, the control logic 40 may measure the frequency of the input signal SI and receive information about the measured frequency (e.g., from a frequency sensor). The control logic 40 may transmit a second control signal CTR2 to the primary switch SW1 based on the information about the frequency, thereby closing or opening the primary switch SW 1.

Referring to fig. 6A, when the frequency of the input signal SI is less than a preset frequency or a given frequency, the control logic 40 may open the primary switch SW 1. When the primary switch SW1 is turned off, the inductance value of the primary inductor LP may increase. For example, when the primary switch SW1 is turned off, a sense current may flow in the first primary inductor LP1, the second primary inductor LP2, and the primary connection line LP3, but not in the primary switch SW 1. Based on the increased inductance value of the primary inductor LP, the primary circuit 110 may resonate according to the relatively low frequency of the input signal SI. In other words, the primary capacitor CP and the primary inductor LP may resonate at a relatively low frequency of the input signal SI. After primary switch SW1 is open, control logic 40 may adjust the capacitance value of primary capacitor CP to allow primary circuit 110 to be in a stable resonant state (e.g., so that primary capacitor CP and primary circuit 110 resonate with each other). In other words, the control logic 40 may perform fine tuning using the primary capacitor CP.

Referring to fig. 6B, when the frequency of the input signal SI is greater than or equal to a preset frequency or a given frequency, the control logic 40 may close the primary switch SW 1. When primary switch SW1 is closed, the inductance value of primary inductor LP may decrease. For example, when the primary switch SW1 is closed, a sense current may flow in the first primary inductor LP1, the primary switch SW1, and the primary connection line LP3, but not in the second primary inductor LP 2. Based on the reduced inductance value of the primary inductor LP, the primary circuit 110 may resonate according to the relatively high frequency of the input signal SI. In other words, the primary capacitor CP and the primary inductor LP may resonate at a relatively high frequency of the input signal SI. After primary switch SW1 is closed, control logic 40 may adjust the capacitance value of primary capacitor CP to allow primary circuit 110 to be in a stable resonant state.

Referring to fig. 6A and 6B, the primary switch SW1 may be connected in parallel to a portion of the primary inductor LP. In detail, the primary switch SW1 may include switch I/O terminals at both ends of the primary switch SW1, respectively, to selectively connect a portion of the primary inductor LP to another portion of the primary inductor LP. For example, the primary switch SW1 may be connected to the primary connection line LP3 through the first and second nodes N1 and N2, and may be connected to the first and second primary inductors LP1 and LP2 through the third and fourth nodes N3 and N4. As described above, the first to fourth nodes N1 to N4 may each be an electrical node formed of a conductive path structure formed by a via hole.

Fig. 7 is a circuit diagram of a stacked switch according to an example embodiment.

Referring to fig. 7, the stack switch SWS may include a plurality of transistors (e.g., first to third transistors TR1 to TR3) and/or a plurality of resistors RG, RS, and/or RB. At least one of the input switch SW0, the primary switch SW1, and/or the secondary switch SW2, which have been described above with reference to the drawings, may be implemented as a stack switch SWs. For example, primary switch SW1 and/or secondary switch SW2 may be implemented as stacked switches SWs to provide higher reliability relative to the relatively high power of the transmitter (e.g., the high power output by DA 20).

The enable signal EN may be applied to a gate terminal of each of the first to third transistors TRl to TR3, and the driving voltage VDD may be applied to a body terminal (body terminal) thereof. The first to third transistors TR1 to TR3 may be opened or closed in response to the enable signal EN and the driving voltage VDD. The enable signal EN may be included in at least one of the first control signal CTR1 and/or the second control signal CTR 2.

The first to third transistors TR1 to TR3 may be connected in series with each other through source/drain terminals thereof. For example, when three transistors (e.g., first to third transistors TR1 to TR3) are connected in series with each other, the stack switch SWS may be referred to as a 3-stack switch (3-stack switch). For example, a source terminal of the first transistor TR1 may be connected to a drain terminal of the second transistor TR2, and a source terminal of the second transistor TR2 may be connected to a drain terminal of the third transistor TR 3. A drain terminal of the first transistor TR1 may be connected to the terminal T1 of the stack switch SWS, and a source terminal of the third transistor TR3 may be connected to the other terminal T2 of the stack switch SWS. Terminals T1 and T2 may be connected to a portion of the primary inductor LP and/or a portion of the secondary inductor LS, and/or may be connected in parallel to the input inductor LI 2.

Fig. 8A and 8B are diagrams for describing a secondary circuit according to example embodiments, and fig. 9A and 9B are diagrams for describing a secondary circuit further including a secondary connection line as compared with fig. 8A and 8B.

Referring to fig. 8A and 8B, a secondary inductor LS (which may also be referred to herein as a secondary inductor bank) may include a first secondary inductor LS1 and a second secondary inductor LS 2. The secondary circuit 120 may include a secondary inductor LS connected to the secondary I/O terminal OT. The secondary switch SW2 may perform a switching operation based on the second control signal CTR 2. The secondary switch SW2 may be connected to at least a portion of the secondary inductor LS and may adjust the inductance of the secondary inductor LS based on the switching operation. The secondary inductor LS may output a signal sensed from the primary inductor LP to the secondary I/O terminal OT. For example, one end of the secondary inductor LS may be connected to the secondary I/O terminal OT, and the opposite end of the secondary inductor LS may be connected to the ground terminal GND.

Referring to fig. 9A and 9B, the secondary circuit 120 may further include a secondary connection line LS3, which may include a first secondary connection line LS3a and a second secondary connection line LS 3B. The secondary connection line LS3 may extend in parallel with one side of the first secondary inductor LS1, thereby generating magnetic flux in a direction that enhances the magnetic flux of the first secondary inductor LS 1. The first secondary connection line LS3a may be electrically connected to the secondary I/O terminal OT and one end of the secondary switch SW2, and the second secondary connection line LS3b may be electrically connected to the ground terminal GND and the opposite end of the secondary switch SW 2.

Referring to fig. 4 and 8A to 9B, the inductance of the secondary inductor LS of the secondary circuit 120 may be adjusted based on the switching operation of the secondary switch SW 2. The control logic 40 may send a second control signal CTR2 to the secondary circuit 120 to adjust the inductance of the secondary inductor LS. Control logic 40 may open secondary switch SW2 when the impedance of load 5 is less than a preset or setpoint value and/or control logic 40 may close secondary switch SW2 when the impedance of load 5 is greater than or equal to a preset or setpoint value.

The secondary switch SW2 may be connected in parallel to a portion of the secondary inductor LS. When the secondary switch SW2 is open, the inductance value of the secondary inductor LS may increase. For example, referring to fig. 8A and 9A, a sensing current may flow in the first secondary inductor LS1, the second secondary inductor LS2, and/or the secondary connection line LS 3. When the secondary switch SW2 is closed, the inductance value of the secondary inductor LS may decrease. For example, referring to fig. 8B, the induced current may flow in the first secondary inductor LS1 but not in the second secondary inductor LS 2. Referring to fig. 9B, a sensing current may flow in the first secondary inductor LS1 and the secondary connection line LS3, but not in the second secondary inductor LS 2.

The control logic 40 may receive information about the impedance of the load 5, which information is stored in a memory device. Alternatively, the control logic 40 may detect the impedance of the load 5 by receiving a signal (e.g., from an impedance sensor) that measures the impedance of the load 5. The detailed structure and characteristics of the secondary circuit 120 are the same as or similar to those of the primary circuit 110 described above, and thus are omitted.

Fig. 10A to 11B are diagrams for describing a primary circuit and a secondary circuit according to example embodiments.

Referring to fig. 10A and 10B, the switching transformer circuit 10 may include the primary inductor LP and the primary connection line LP3 already described with reference to fig. 6A and 6B and the secondary inductor LS described with reference to fig. 8A and 8B. In other words, the switching transformer circuit 10 may include the primary inductor LP, the primary connection line LP3, and the secondary inductor LS formed on the same semiconductor layer or similar semiconductor layers.

Referring to fig. 11A and 11B, the switching transformer circuit 10 may include a primary inductor LP described with reference to fig. 6A and 6B and a secondary inductor LS described with reference to fig. 8A and 8B. In other words, the switching transformer circuit 10 may include the primary inductor LP and the secondary inductor LS formed on the same semiconductor layer or similar semiconductor layers.

Referring to fig. 10A and 11A, when the frequency of the input signal SI is less than a preset frequency or a given frequency (e.g., a frequency value and/or a frequency threshold), the primary switch SW1 may be opened and the inductance of the primary circuit 110 may increase. When the magnitude of the load 5 is less than a preset or given magnitude (e.g., a magnitude and/or magnitude threshold), the secondary switch SW2 may open and the inductance of the secondary circuit 120 may increase. Referring to fig. 10A, since the magnetic flux is enhanced by the primary connection line LP3 in the switching transformer circuit 10, a coupling coefficient (e.g., 0.64) between the primary inductor LP and the secondary inductor LS may be increased. Referring to fig. 11A, since the primary connection line LP3 is not present, the coupling coefficient (e.g., 0.63) may be reduced in the switching transformer circuit 10.

Referring to fig. 10B and 11B, when the frequency of the input signal SI is greater than or equal to a preset frequency or a given frequency (e.g., a frequency value and/or a frequency threshold), the primary switch SW1 may be closed and the inductance of the primary circuit 110 may be reduced. When the magnitude of the load 5 is greater than or equal to a preset magnitude or a given magnitude (e.g., a magnitude value and/or a magnitude threshold), the secondary switch SW2 may close and the inductance of the secondary circuit 120 may decrease. Referring to fig. 10B, since the magnetic flux is enhanced by the primary connection line LP3 in the switching transformer circuit 10, a coupling coefficient (e.g., 0.65) between the primary inductor LP and the secondary inductor LS may be increased. Referring to fig. 11B, since the primary connection line LP3 is not present, the coupling coefficient (e.g., 0.53) may be reduced in the switching transformer circuit 10.

Fig. 12A to 12D are circuit diagrams of a primary circuit in a primary switching operation and a secondary circuit in a secondary switching operation according to example embodiments.

Referring to fig. 12A, the frequency of the input signal SI may be less than a preset frequency or a given frequency, and the primary switch SW1 may be turned off. The secondary switch SW2 may be open when the magnitude of the load 5 is less than a preset or set value. In response to the primary switch SW1 being open, current may flow in the second primary inductor LP2 without flowing in the primary switch SW 1. Based on the first primary inductor LP1, the second primary inductor LP2, and the primary connection line LP3, the inductance value of the primary circuit 110 may be relatively large. In response to secondary switch SW2 being open, current does not flow in secondary switch SW2, but may flow in second secondary inductor LS 2. Based on the first secondary inductor LS1, the second secondary inductor LS2, and the secondary connection line LS3, the inductance value of the secondary circuit 120 may be relatively large.

Referring to fig. 12B, the frequency of the input signal SI may be less than a preset frequency or a given frequency, and the primary switch SW1 may be turned off. As described above, the inductance value of the primary circuit 110 may be relatively large. The secondary switch SW2 may be closed when the magnitude of the load 5 is greater than or equal to a preset or given value. In response to secondary switch SW2 closing, current may flow in secondary switch SW2 but not in second secondary inductor LS 2. Based on the first secondary inductor LS1 and the secondary connection line LS3, the inductance value of the secondary circuit 120 may be relatively small.

Referring to fig. 12C, the frequency of the input signal SI may be greater than or equal to a preset frequency or a given frequency, and the primary switch SW1 may be closed. In response to the primary switch SW1 being closed, current may flow in the primary switch SW1 but not in the second primary inductor LP 2. Based on the first primary inductor LP1 and the primary connection line LP3, the inductance value of the primary circuit 110 may be relatively small. As described above, when the size of the load 5 is less than the preset value or the given value, the secondary switch SW2 may be turned off, and the inductance value of the secondary circuit 120 may be relatively large based on the first secondary inductor LS1, the second secondary inductor LS2, and the secondary connection line LS 3.

Referring to fig. 12D, the frequency of the input signal SI may be greater than or equal to a preset frequency or a given frequency, and the size of the load 5 may be greater than or equal to a preset value or a given value. In this case, the primary switch SW1 and the secondary switch SW2 are closed, and thus, the inductance of each of the primary circuit 110 and the secondary circuit 120 may be relatively small.

Referring to fig. 13, a communication device (or communication system) 600 may include an Application Specific Integrated Circuit (ASIC)610, an application specific instruction set processor (ASIP)630, a memory 650, a main processor 670, and/or a main memory 690. At least two selected from the ASIC 610, the ASIP 630, and/or the host processor 670 may communicate with each other. At least two selected from the ASIC 610, the ASIP 630, the memory 650, the main processor 670, and/or the main memory 690 may be embedded in one chip.

ASIP 630 is customized for a particular purpose and may support an instruction set specific to a particular application and execute instructions included in the instruction set. Memory 650 may be in communication with ASIP 630 and may serve as a non-transitory storage device storing instructions that may be executed by ASIP 630. By way of non-limiting example, memory 650 may include any type of memory accessible by ASIP 630, such as Random Access Memory (RAM), Read Only Memory (ROM), magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof.

The main processor 670 may control the communication device 600 by executing instructions. For example, the host processor 670 may control the ASIC 610 and/or the ASIP 630 and may process data received over a wireless communication network or user input to the communication device 600. The main memory 690 may be in communication with the main processor 670 and may serve as a non-transitory storage device storing a plurality of instructions that may be executed by the main processor 670. By way of non-limiting example, main memory 690 may include any type of memory accessible by main processor 670, such as RAM, ROM, magnetic tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof.

At least one selected from the switching transformer module 1, the switching transformer circuit 10, the driving input circuit 30, and/or the electronic system 1000 may be included in all or some elements of the communication apparatus 600 of fig. 13. For example, the switching transformer circuit 10 and/or the driving input circuit 30 may be included in an element using an output signal generated by transforming an input signal, and may also be included in an element using a transformation ratio controlled according to a frequency of the input signal. The method of operation of the switching transformer circuit 10 and/or the drive input circuit 30 may be performed by at least one element of the communication device 600 of fig. 13. For example, the operations of control logic 40 in fig. 2 may be implemented by a plurality of instructions stored in memory 650, and ASIP 630 may perform at least one operation in the method of operation of switching transformer circuit 10 and/or drive input circuit 30 by executing the plurality of instructions stored in memory 650. In an example embodiment, at least one operation of the operation methods of the switching transformer circuit 10 and/or the driving input circuit 30 may be performed by a hardware block designed using logic synthesis, wherein the hardware block may be included in the ASIC 610. In an example embodiment, at least one of the operations of the switching transformer circuit 10 and/or the operation method of the driving input circuit 30 may be implemented by a plurality of instructions stored in the main memory 690, and the main processor 670 may perform at least one of the operations of the switching transformer circuit 10 and/or the operation method of the driving input circuit 30 by executing the plurality of instructions stored in the main memory 690.

Conventional transformers include switches for reducing the inductance of the transformer to increase the bandwidth. However, conventional switches included in conventional transformers become unreliable due to the high output power of conventional transformers. Moreover, the switch reduces the magnetic flux in a conventional transformer, resulting in a reduced coupling coefficient.

However, example embodiments provide an improved transformer. The improved transformer may include improved switches implemented as stacked switches that provide greater reliability in the high output power environment of the improved transformer. Also, the improvement transformer may include a primary connection line and/or a secondary connection line connected in parallel with one side of the first primary inductor and/or the secondary inductor, thereby generating a magnetic flux that enhances a magnetic flux of the first primary and/or the secondary inductor and increasing a coupling coefficient of the improvement transformer.

According to an example embodiment, operations described herein as being performed by the electronic system 1000, the switching transformer module 1, the filter 2, the mixer 3, the PLL 4, the input switch SW0, the primary switch SW1, the secondary switch SW2, the switching transformer circuit 10, the Drive Amplifier (DA)20, the drive input circuit 30, the control logic 40, the primary circuit 110, and/or the secondary circuit 120 may be performed by a processing circuit. The term "processing circuitry" as used in this disclosure may refer to, for example: hardware including logic circuitry; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and so forth.

The various operations of the methods described above may be performed by any suitable device capable of performing the operations, such as the processing circuitry described above. For example, as described above, the operations of the above-described methods may be performed by various hardware and/or software implemented in some form of hardware (e.g., a processor, an ASIC, etc.).

The software may comprise an ordered listing of executable instructions for implementing logical functions, and may be embodied in any "processor-readable medium" for use by or in connection with an instruction execution system, apparatus, or device, such as a single-core or multi-core processor or a system including a processor.

The blocks or operations of the methods or algorithms and functions described in connection with the example embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a tangible, non-transitory computer-readable medium (e.g., the memory of control logic 40). For example, a software module may reside in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), electrically programmable ROM (eprom), electrically erasable programmable ROM (eeprom), registers, hard disk, a removable disk, a CD ROM, or any other form of storage medium known in the art.

For ease of description, spatially relative terms, such as "below … …," "below … …," "below … …," "above … …," "above … …," "above … …," and the like, may be used herein to describe one element or feature's relationship to another element or feature. For example, as used herein, the terms "above … …," "higher," "above … …," and/or "top" may refer to an element or feature that is in a particular direction relative to another element or feature, while the terms "below … …" and/or "below … …" may refer to an element or feature that is in an opposite direction relative to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below … …" can encompass both an orientation above … … and below … …. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

While example embodiments have been particularly shown and described with reference to examples, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A switching transformer, comprising:

a driver amplifier configured to output an input signal by amplifying a source signal;

a primary circuit comprising a primary inductor bank, a primary switch, and a first primary connection line, the primary inductor bank configured to receive the input signal at a first primary input/output terminal, the primary switch configured to adjust an inductance of the primary inductor bank based on a first switching operation, and the first primary connection line configured to electrically connect the first primary input/output terminal to a first end of the primary switch; and

a secondary circuit configured to electromagnetically couple to each other with the first primary connection line and at least one primary inductor of the primary inductor group.

2. The switching transformer of claim 1, further comprising:

a processing circuit configured to control the first switching operation by:

controlling the primary switch to turn off based on the frequency of the input signal being less than a frequency value, an

Controlling the primary switch to close based on the frequency of the input signal being greater than or equal to the frequency value.

3. The switching transformer as recited in claim 2 wherein said controlling said primary switch to open increases an inductance of said primary inductor bank and said controlling said primary switch to close decreases said inductance of said primary inductor bank.

4. The switching transformer of claim 2, further comprising:

a primary capacitor for the primary side of the capacitor,

wherein the content of the first and second substances,

the first primary input/output terminal is one of a plurality of primary input/output terminals configured to receive the input signal,

the primary capacitor is connected in parallel to the plurality of primary input/output terminals, and

the processing circuit is configured to control a capacitance of the primary capacitor based on the frequency of the input signal such that the primary capacitor and the primary circuit resonate with each other.

5. The switching transformer of claim 1, wherein the primary switch is configured to selectively connect a first primary inductor of the primary inductor bank to a second primary inductor of the primary inductor bank.

6. The switching transformer of claim 1, wherein the secondary circuit comprises a secondary inductor bank configured to output a signal sensed from the primary circuit to a secondary input/output terminal, a secondary switch configured to adjust an inductance of the secondary inductor bank based on a second switching operation, and a secondary connection line configured to electrically connect the secondary input/output terminal to one end of the secondary switch.

7. The switching transformer according to claim 1,

the first primary input/output terminal is one of a plurality of differential terminals including the first primary input/output terminal and a second primary input/output terminal, the plurality of differential terminals configured to receive the input signal;

the first primary connection line is one of a plurality of primary connection lines including the first primary connection line and a second primary connection line;

both ends of the primary inductor group are electrically connected to the first primary input/output terminal and the second primary input/output terminal, respectively; and is

The second primary connection line is configured to electrically connect the second primary input/output terminal with a second end of the primary switch opposite the first end.

8. The switching transformer according to claim 1, wherein an inductance value of the first primary connection line is substantially equal to an inductance value of the primary inductor group.

9. The switching transformer according to claim 1, wherein the primary inductor group and the first primary connection line are formed on a first semiconductor layer, and the primary switch is formed on a second semiconductor layer stacked on the first semiconductor layer.

10. The switching transformer according to claim 9, wherein the primary inductor group and the first primary connecting line are connected to the primary switch by a conductive via structure filling a via hole.

11. The switching transformer of claim 1, wherein a width of the first primary connection line is less than a width of each primary inductor of the primary inductor group.

12. The switching transformer of claim 1, wherein the primary switch comprises a plurality of transistors connected in series, each individual transistor of the plurality of transistors connected to another transistor of the plurality of transistors by a source or a drain of the individual transistor, each transistor of the plurality of transistors having a gate terminal configured to receive an enable signal, and each transistor of the plurality of transistors having a bulk terminal configured to receive a drive voltage.

13. The switching transformer of claim 12, wherein the primary switch comprises a 3-stack switch and the plurality of transistors comprises three transistors.

14. An electronic system, comprising:

a mixer configured to output a source signal based on frequency translation;

a driver amplifier configured to output an input signal by amplifying the source signal;

a drive input circuit comprising an input capacitor, an input inductor bank, and an input switch, and electrically connected to the input terminal of the drive amplifier, the input switch configured to adjust an inductance of the input inductor bank based on a first switching operation;

a primary circuit comprising a primary inductor bank, a primary switch, and a first primary connecting line, the primary inductor bank configured to receive the input signal at a first primary input/output terminal, the primary switch configured to adjust an inductance of the primary inductor bank based on a second switching operation, and the first primary connecting line configured to electrically connect the first primary input/output terminal to a first end of the primary switch; and

a processing circuit configured to control the first switching operation and the second switching operation.

15. The electronic system of claim 14, wherein the processing circuit is configured to control the first switching operation by:

controlling the primary switch to increase an inductance of the input inductor bank based on a frequency of the source signal being less than a frequency value; and

based on the frequency of the source signal being greater than or equal to the frequency value, controlling the primary switch to reduce an inductance of the input inductor bank.

16. The electronic system of claim 14, further comprising:

a secondary circuit comprising a secondary inductor bank, a secondary switch, and a secondary connection line, the secondary inductor bank configured to output a signal sensed from the primary circuit to a secondary input/output terminal, the secondary switch configured to adjust an inductance of the secondary inductor bank based on a third switch operation, and the secondary connection line configured to electrically connect the secondary input/output terminal to one end of the secondary switch.

17. The electronic system of claim 16, wherein the processing circuit is configured to control the third switching operation of the secondary switch based on a size of a load connected to the secondary input/output terminal.

18. The electronic system of claim 17, wherein the processing circuit is configured to control the third switching operation by:

based on the magnitude of the load being less than a magnitude value, controlling the secondary switch to increase an inductance of the secondary inductor bank; and

based on the magnitude of the load being greater than or equal to the magnitude value, controlling the secondary switch to reduce an inductance of the secondary inductor group.

19. The electronic system of claim 14,

the first primary input/output terminal is one of a plurality of differential terminals including the first primary input/output terminal and a second primary input/output terminal, the plurality of differential terminals configured to receive the input signal; and is

The first primary connection line is one of a plurality of primary connection lines including the first primary connection line and a second primary connection line configured to electrically connect the second primary input/output terminal to a second end of the primary switch opposite the first end.

20. An electronic system, comprising:

a primary circuit comprising a primary inductor bank, a primary switch, and a primary connecting line, the primary inductor bank configured to receive an input signal at a primary input/output terminal, the primary switch configured to adjust an inductance of the primary inductor bank based on a first switching operation, and the primary connecting line configured to electrically connect the primary input/output terminal to one end of the primary switch;

a secondary circuit including a secondary inductor group, a secondary switch, and a secondary connection line, the secondary circuit being electromagnetically coupled to the primary connection line and at least one of the primary inductors of the primary inductor group, the secondary inductor group being configured to output a signal induced from the primary circuit to a secondary input/output terminal electrically connected to a load, the secondary switch being configured to adjust an inductance of the secondary inductor group based on a second switching operation, and the secondary connection line being configured to electrically connect the secondary input/output terminal to one end of the secondary switch; and

a processing circuit configured to control at least one of the first switching operation and the second switching operation based on at least one of a frequency of the input signal and a magnitude of the load.