CN112687317B - Semiconductor device and erasing and verifying method for semiconductor device - Google Patents

Semiconductor device and erasing and verifying method for semiconductor device Download PDF

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Publication number
CN112687317B
CN112687317B CN202110010734.8A CN202110010734A CN112687317B CN 112687317 B CN112687317 B CN 112687317B CN 202110010734 A CN202110010734 A CN 202110010734A CN 112687317 B CN112687317 B CN 112687317B
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memory cell
cell string
select transistor
unselected
semiconductor device
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CN112687317A (en
Inventor
贾建权
李达
游开开
李楷威
罗哲
田瑶瑶
刘畅
李姗
张安
靳磊
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202210370104.6A priority Critical patent/CN114863982A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits

Abstract

The application discloses a semiconductor device and an erasing and verifying method for the same, wherein the semiconductor device comprises a plurality of memory blocks, a selected memory block in the plurality of memory blocks comprises a plurality of memory cell strings, and each memory cell string comprises a plurality of memory cells; the erasing and verifying method comprises the following steps: erasing a plurality of memory cells in each memory cell string in an erase operation stage; in a verification operation phase, including a pre-turn-on phase and a verification phase, the plurality of memory cell strings include selected memory cell strings and unselected memory cell strings; setting at least one of the selected memory cell string and the unselected memory cell string to a channel conducting state in a pre-conduction stage; in the verify phase, a threshold voltage of at least one memory cell in the selected memory cell string is verified, and unselected memory cell strings are set to a channel off state. The method and the device can avoid the risk of hot carrier injection, and are favorable for improving the accuracy of erasing verification of the semiconductor device.

Description

Semiconductor device and erasing and verifying method for semiconductor device
Technical Field
The present disclosure relates to a semiconductor device and an erasing and verifying method thereof, and more particularly, to a semiconductor device and an erasing and verifying method for a semiconductor device that can avoid a risk of hot carrier injection.
Background
Semiconductor memory is widely used in a variety of electronic devices, such as cellular telephones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, and non-mobile computing devices. Non-volatile memory allows information to be stored and maintained. Examples of the nonvolatile memory include flash memories (e.g., NAND-type and NOR-type flash memories) and electrically erasable programmable read only memories (electrically erasable programmable read only memories, EEPROMs).
Recently, ultra-high density memory devices using a three-dimensional (3D) stacked memory structure, sometimes referred to as a bit-cost scalable (BiCS) architecture, have been proposed. For example, a 3D NAND stack flash memory device may be formed from an array of alternating conductive and dielectric layers. Storage holes are drilled in the layers to define many storage layers simultaneously. The NAND string is then formed by filling the storage hole with an appropriate material. The control gates of the memory cells are provided by conductive layers. Each planar NAND memory is constituted by a memory cell array connected by a plurality of word lines and bit lines. Data is programmed into or read out of the planar NAND memory page by page, and erased (erase) from the planar NAND memory block by block, i.e., a block is a unit of a conventional erase operation and a page is a unit of a conventional program operation.
For the existing three-dimensional NAND flash memory structure, after the erase phase, a verify (verify) phase is required to verify whether the erase was successful. However, when erasing the memory cells in the NAND string, there is a risk of HCI (hot carrier injection), which is not favorable for improving the accuracy of the erase verification.
Disclosure of Invention
The application provides a semiconductor device and an erasing and verifying method for the same, which can avoid the risk of hot carrier injection and are beneficial to improving the erasing and verifying accuracy of the semiconductor device.
The application provides a semiconductor device and an erasing and verifying method for the semiconductor device, wherein the semiconductor device comprises a plurality of memory blocks, a selected memory block in the plurality of memory blocks comprises a plurality of memory cell strings, and each memory cell string comprises a plurality of memory cells which are arranged in series;
the erasing and verifying method comprises the following steps:
erasing a plurality of memory cells in each of the memory cell strings during an erase operation;
in a verification operation stage, a pre-conduction stage and a verification stage are included, the plurality of memory cell strings comprise selected memory cell strings and unselected memory cell strings, and the selected memory cell strings are to-be-verified memory cell strings;
setting at least one of the selected memory cell string and the unselected memory cell string to a channel conducting state in the pre-conduction phase; in the verify phase, a threshold voltage of at least one memory cell in the selected memory cell string is verified, and the unselected memory cell strings are set to a channel off state.
Optionally, each of the storage unit strings further includes at least one virtual storage unit arranged in series with the plurality of storage units;
the erase and verify method further comprises:
providing a first turn-on voltage to a word line of the at least one dummy memory cell to turn on a channel of the at least one dummy memory cell in the pre-turn-on phase and the verification phase.
Optionally, each of the memory cell strings further includes a top selection transistor and a bottom selection transistor, and the plurality of memory cells and the at least one dummy memory cell are located between and arranged in series with the top selection transistor and the bottom selection transistor;
the erase and verify method further comprises:
in the pre-turn-on phase and the verify phase, a top select transistor and a bottom select transistor of the selected memory cell string are turned on.
Optionally, the setting at least one of the selected memory cell string and the unselected memory cell string to a channel conducting state includes:
providing a second turn-on voltage to word lines of a plurality of memory cells of the selected memory cell string;
the verifying a threshold voltage of at least one memory cell in the selected memory cell string comprises:
providing a verification voltage to a word line of at least one memory cell in the selected memory cell string to check whether a threshold voltage of the at least one memory cell is a preset value; wherein the verify voltage is lower than the second turn-on voltage.
Optionally, the setting at least one of the selected memory cell string and the unselected memory cell string to a channel conducting state further includes:
the second turn-on voltage is provided to word lines of a plurality of memory cells of the unselected memory cell string, and a top select transistor and a bottom select transistor of the unselected memory cell string are turned on.
Optionally, the setting at least one of the selected memory cell string and the unselected memory cell string to a channel conducting state includes:
a second turn-on voltage is provided to word lines of a plurality of memory cells of the unselected memory cell string, and a top select transistor and a bottom select transistor of the unselected memory cell string are turned on.
Optionally, the erasing and verifying method further includes:
during the pre-turn-on phase and the verify phase, the bottom select transistor of the unselected memory cell string remains in a conductive state;
said turning on top and bottom select transistors of said unselected memory cell strings comprises the steps of:
providing a third turn-on voltage to an unselected top select transistor of the unselected memory cell string to turn on the unselected top select transistor.
Optionally, the second turn-on voltage is greater than 0V, and the verification voltage is less than 0V.
Optionally, the first turn-on voltage is higher than the verify voltage.
Optionally, the semiconductor device includes a plurality of stacked layers arranged in a stack; the stacked layer comprises a plurality of gate layers and dielectric layers which are alternately stacked; the plurality of strings of memory cells extend vertically through the plurality of stack layers;
each said string of storage units comprises a string of child storage units located in each said stack layer, and said at least one virtual storage unit is located between any two adjacent strings of said child storage units; the sub memory cell string includes the plurality of memory cells.
Optionally, each of the memory cell strings further includes a top selection transistor and a bottom selection transistor, and the plurality of memory cells and the at least one dummy memory cell are arranged in series with and between the top selection transistor and the bottom selection transistor;
the at least one dummy memory cell is located between the top select transistor and the plurality of memory cells, or between the plurality of memory cells and the bottom select transistor, or between any two adjacent memory cells.
The present application also provides a semiconductor device including:
a plurality of memory blocks, selected ones of the plurality of memory blocks comprising a plurality of memory cell strings, each of the memory cell strings comprising a plurality of memory cells arranged in series;
a control circuit in signal connection with the plurality of memory blocks; the control circuit is configured to perform the erase and verify method described above.
In the semiconductor device and the erasing and verifying method for the semiconductor device, after the erasing operation is executed, the verifying operation is divided into a pre-conduction stage and a verifying stage, and in the pre-conduction stage, at least one of a selected memory cell string and an unselected memory cell string in a plurality of memory cell strings is kept in a channel conduction state, so that the whole channel of the selected memory cell string and/or the unselected memory cell string is ensured to be conducted, the risk of HCI in the selected memory cell string and/or the unselected memory cell string can be avoided, and the erasing and verifying accuracy of the semiconductor device can be improved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a 3D NAND memory device according to an embodiment of the present application.
Fig. 2 is a schematic partial cross-sectional view of a semiconductor device with a dual stack structure according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of a selected memory cell string and an unselected memory cell string in a semiconductor device according to an embodiment of the present application.
Fig. 4 is a schematic flowchart of an erasing and verifying method for a semiconductor device according to an embodiment of the present disclosure.
FIG. 5 is a timing diagram illustrating an erase operation and a verify operation of a selected memory cell string according to an embodiment of the present disclosure.
FIG. 6 is a timing diagram illustrating an erase operation and a verify operation of an unselected string of memory cells according to an embodiment of the present invention.
Fig. 7 is a timing diagram illustrating an erase operation and a verify operation of a selected memory cell string according to a second embodiment of the present application.
Fig. 8 is a timing diagram illustrating an erase operation and a verify operation of an unselected cell string according to the second embodiment of the present application.
Fig. 9 is a timing diagram of an erase operation and a verify operation of a selected memory cell string according to a third embodiment of the present application.
Fig. 10 is a timing diagram illustrating an erase operation and a verify operation of an unselected cell string according to a third embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
As shown in fig. 1, the 3D NAND memory device 10 includes a memory array 11 and a control circuit 12. Control circuitry 12 is configured to perform read, write, erase and verify operations on memory array 11, and control circuitry 12 may include word line drivers, bit line drivers, column decoders, sense circuitry, data buffers, program verify logic and erase verify circuitry. The memory array 11 is divided into a plurality of memory BLOCKs, represented as BLOCKs1～BLOCKIWherein I is a positive integer. Each memory block including a bit line BL1～BLMAnd a group of common word lines WL1～WLNA set of NAND strings (i.e., strings of memory cells) 13 is accessed, where M and N are integers greater than 1. One terminal of NAND string 13 is selected via the topA transistor (connected to the top select gate line SGTL) is connected to a corresponding bit line, and the other terminal is connected to a Common Source Line (CSL) via a bottom select transistor (connected to the bottom select gate line SGBL).
Each memory block is typically divided into PAGEs (PAGE), as indicated by the dashed lines. The memory block is a unit of a conventional erase operation, and the page is a unit of a conventional program operation. However, other units of erase/programming may be used.
When the control circuit 12 performs an erase operation in units of memory blocks, a corresponding verify operation must be performed to ensure that the corresponding memory cells are erased, thereby preventing data retention or meta-stability, which would lead to a reduction in the lifetime of the 3D NAND memory device.
In one embodiment, each NAND string includes a top select transistor, a bottom select transistor, a plurality of Memory Cells (MC), and at least one Dummy Memory Cell (DMC) arranged in series; wherein the plurality of memory cells and the at least one dummy memory cell are located between the top select transistor and the bottom select transistor. Specifically, the dummy memory cell is located between the top selection transistor and the plurality of memory cells, or between the plurality of memory cells and the bottom selection transistor, or between any two adjacent memory cells. The top select transistor is arranged for connecting the NAND string to a bit line via a bit line contact, and can be controlled by applying an appropriate voltage to the top select gate line. The bottom select transistor is arranged for connecting the NAND string to a Common Source Line (CSL), and can be controlled by applying an appropriate voltage to the bottom select gate line. Each memory cell is connected to a corresponding Word Line (WL), each dummy memory cell is connected to a corresponding Dummy Word Line (DWL), word lines of memory cells located in the same page receive the same electrical signal, and dummy word lines of dummy memory cells located in the same page receive the same electrical signal. The memory cell and the dummy memory cell are both in transistor structures, and the word line of the memory cell and the dummy word line of the dummy memory cell are both the same as the control gate and are used for controlling the memory cell and the dummy memory cell to be in on or off states.
When the control circuit executes the erasing operation, only the plurality of memory cells in the selected memory block are erased, and the virtual memory cells are not erased, so that the threshold voltage of the virtual memory cells is not changed. When the control circuit performs the verify operation, in the selected NAND string, the word lines of the selected memory cells are applied with the verify voltage, the word lines of the unselected memory cells are applied with the pass voltage, and the corresponding dummy word lines of the dummy memory cells are applied with the higher pass voltage Vpass to open the channel. Therefore, in the verify phase, since the pass voltage Vpass applied to the dummy word line has a high potential (much higher than the threshold voltage of the erased memory cell), a high potential region is easily formed in the unselected NAND string, which causes a strong electric field between the dummy word line and the adjacent word line, resulting in band-to-band (band-to-band) tunneling, thereby causing a risk of Hot Carrier Injection (HCI). Moreover, as the control gate length Lg and the control gate spacing Ls are reduced in the manufacturing process, the risk of HCI increases, which seriously affects the threshold voltage of the memory cell near the dummy memory cell, the erase effect and the verification accuracy. In addition, if the erase effect of the memory cell is poor, the threshold voltage of the selected memory cell is not low enough during verification, that is, the verification voltage is lower than the threshold voltage, which may cause channel pinch-off and also cause HCI risk.
It should be noted that, the selected memory block described in this application is a target memory block to be subjected to an erase operation; the selected NAND string is the target NAND string on which the verify operation is to be performed; the selected memory cell is a target memory cell on which a verify operation is to be performed.
In order to solve the technical problem, embodiments of the present application provide a semiconductor device and an erasing and verifying method for the semiconductor device. Reference is made in particular to the following examples.
Example one
The embodiment of the application provides an erasing and verifying method for a semiconductor device.
Specifically, as shown in conjunction with fig. 1 to 3, the semiconductor device 20 is a three-dimensional memory device, such as a 3D NAND memory device 10. The semiconductor device 20 includes a plurality of memory BLOCKs, selected ones of which include a plurality of memory cell strings 21, such as a plurality of NAND strings. As shown in fig. 3, each memory cell string 21 includes a top select transistor Q1, a bottom select transistor Q2, a plurality of memory cells MC, and at least one dummy memory cell DMC arranged in series. In this embodiment, the number of the virtual memory units DMC is plural, but is not limited thereto. Wherein the plurality of memory cells MC and the plurality of dummy memory cells DMC are located between the top select transistor Q1 and the bottom select transistor Q2. The plurality of dummy memory cells DMC are located between the top select transistor Q1 and the plurality of memory cells MC, or between the plurality of memory cells MC and the bottom select transistor Q2, or between any adjacent two memory cells MC. The present embodiment will be described by taking an example in which a plurality of dummy memory cells DMC are located between two adjacent memory cells MC.
As shown in fig. 3, the plurality of memory cell strings include a selected memory cell string 39 and an unselected memory cell string 40, wherein the selected memory cell string 39 is a memory cell string to be verified (target memory cell string) in the verification stage. It will be appreciated that during the erase phase, the selected memory cell string 39 and the unselected memory cell string 40 in the selected memory block perform erase operations simultaneously.
In a particular embodiment, semiconductor device 20 includes a substrate 22 and a plurality of stacked layers stacked disposed on substrate 22; each stack layer comprises a plurality of gate layers and dielectric layers which are alternately stacked; the plurality of memory cell strings vertically penetrate through the plurality of stack layers; each storage unit string comprises a plurality of sub-storage unit strings positioned in a plurality of stack layers, and a plurality of virtual storage units DMC are positioned between any two adjacent sub-storage unit strings; each sub-memory cell string includes a plurality of memory cells. As can be appreciated, the plurality of virtual memory cells are located at a connection region of two adjacent sub-memory cell strings.
As shown in fig. 2 and fig. 3, the semiconductor device 20 of the dual stack structure will be described as an example in the embodiment of the present application, where the semiconductor device 20 includes a lower stack layer 23 and an upper stack layer 24 disposed on a substrate 22, and each of the lower stack layer 23 and the upper stack layer 24 includes a plurality of gate layers 28 and dielectric layers 29 alternately stacked. Each memory cell string 21 includes a first sub-memory cell string 25 located in the lower stack layer 23, a second sub-memory cell string 26 located in the upper stack layer 24, and a virtual memory layer 27 located between the first sub-memory cell string 25 and the second sub-memory cell string 26. The virtual storage layer 27 comprises a plurality of virtual storage units DMC. It will be appreciated that the portion of the virtual storage tier 27 adjacent the first sub-string 25 of storage cells is located in the lower stack tier 23 and the portion adjacent the second sub-string 26 of storage cells is located in the upper stack tier 24. The first sub-memory cell string 25 includes a bottom select transistor Q2 disposed near the substrate 22 and a plurality of memory cells MC located on a side of the bottom select transistor Q2 remote from the substrate 22; the second sub-memory cell string 26 includes a top select transistor Q1 disposed in a direction away from the substrate 22 and a plurality of memory cells MC between the top select transistor Q1 and the plurality of dummy memory cells DMC. Substrate 22 includes a P-type well region (PW), such as a high voltage P-type well region (HVPW).
Specifically, the memory cell string 21 includes a channel structure 30 that penetrates the lower and upper stacked layers 23 and 24 in a direction perpendicular to the substrate 22. In some embodiments, the channel structure 30 may include a channel hole filled with a semiconductor material (e.g., as a semiconductor channel 31) and a dielectric material (e.g., as a memory film 32). The material of the semiconductor channel 31 includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. The memory film 32 includes a composite dielectric layer of a tunnel layer 33, a storage layer 34 (also referred to as a "charge trapping/storage layer 34"), and a blocking layer 35. The channel structure 30 may have a cylindrical shape (e.g., a cylindrical shape). The semiconductor channel 31, the tunnel layer 33, the storage layer 34 and the barrier layer 35 are arranged radially in this order from the center of the pillar to the outer surface of the pillar. Of course, in a specific embodiment, the trench structure 30 may further include a filling dielectric layer 36 filled on a side of the semiconductor trench 31 away from the tunnel layer 33. The tunnel layer 33 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 34 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Barrier layer 35 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the storage film 32 may include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).
The memory cell string 21 may further include a semiconductor plug 37 in a lower portion of the memory cell string 21. Semiconductor plug 37 may comprise a semiconductor material, such as monocrystalline silicon, epitaxially grown in any suitable direction from substrate 22. Semiconductor plug 37 may serve as part of the channel of bottom select transistor Q2 of memory cell string 21. The memory cell string 21 may further include a channel plug 38 in an upper portion of the memory cell string 21. The channel plug 38 can serve as a channel of the top selection transistor Q1 of the memory cell string 21.
The gate layer 28 of a memory cell string 21 may include multiple control gates for multiple memory cell strings 21 and may extend laterally as word lines ending at the edge of the stacked layers.
As shown in fig. 4, the erasing and verifying method provided in the embodiment of the present application specifically includes steps S401 and S402.
Step S401: in the erase operation phase, a plurality of memory cells in each memory cell string are erased.
As shown in connection with fig. 3 and 5, during the erase operation phase (period T0 to T1), in the selected memory block, the top select transistor Q1, the plurality of dummy memory cells DMC, the bottom select transistor Q2, and the common source line CSL of each memory cell string (including the selected memory cell string 39 and the unselected memory cell string 40) are floated, the word line WL corresponding to each memory cell MC is grounded, and the P-type well region (PW) of the substrate 22 is supplied with the erase voltage Ve, so that electrons trapped in the floating gate of the corresponding memory cell MC are attracted by the high erase voltage Ve of the P-type well region and leave the floating gate, thereby erasing the corresponding memory cell MC.
It is understood that, in the erase phase, the dummy memory cell DMC is not erased, the threshold voltage of the dummy memory cell DMC is maintained as it is, and the threshold voltage of the dummy memory cell DMC is maintained in a higher level state compared to the threshold voltage of the memory cell MC after the erase.
Step S402: in the verification operation stage, a pre-conduction stage and a verification stage are included, the plurality of memory cell strings comprise selected memory cell strings and unselected memory cell strings, and the selected memory cell strings are to-be-verified memory cell strings; in a pre-conduction stage, setting a selected memory cell string and an unselected memory cell string to be in a channel conduction state; in the verify phase, a threshold voltage of at least one memory cell in the selected memory cell string is verified, and unselected memory cell strings are set to a channel off state.
Specifically, as shown in fig. 3 and 5, during the whole verification operation phase (time period T2 to T4, including the pre-turn-on phase and the verification phase): providing a first pass voltage Vpass1 to the dummy word line DWL of each dummy memory cell DMC to pass a channel of each dummy memory cell DMC; also, the top select transistor Q1 and the bottom select transistor Q2 of the selected memory cell string 39 are turned on, for example, high level voltages are respectively supplied to the top select gate line SGTL and the bottom select gate line SGBL of the selected memory cell string 39, so that the top select transistor Q1 and the bottom select transistor Q2 of the selected memory cell string 39 are turned on; in addition, the common source line CSL and the P-type well region are grounded.
As shown in conjunction with fig. 3 and 5, in the pre-turn-on phase (time period T2 to T3), the second turn-on voltage Vpass2 is supplied to the word lines WL of the plurality of memory cells MC (including the selected memory cell and the unselected memory cell) of the selected memory cell string 39 among the plurality of memory cell strings to turn on the channels of the plurality of memory cells MC of the selected memory cell string 39. It is to be understood that, as shown in fig. 6, the word lines of the plurality of memory cells MC of the unselected memory cell string 40 are also supplied with the second pass voltage Vpass2 to open the channels of the plurality of memory cells MC of the unselected memory cell string 40 in the pre-pass phase. Also, in the pre-conduction phase, the top select transistor Q1 and the bottom select transistor Q2 of the unselected memory cell string 40 are turned on.
Specifically, as shown in fig. 6, during the entire verification operation phase (time period T2 to T4 including the pre-conduction phase and the verification phase), the bottom select gate line of the unselected memory cell string 40 is always supplied with a high level voltage to keep the corresponding bottom select transistor Q2 in a conduction state, and then during the pre-conduction phase, the third conduction voltage Vpass3 needs to be supplied to the unselected top select transistor Q1 of the unselected memory cell string 40 to make the unselected top select transistor Q1 conduct. For example, during the Pre-conduction phase, a Pre-pulse (Pre-pulse) is applied to the unselected top select gate lines of the unselected memory cell strings 40 to open the channel of the unselected top select transistor Q1, turning on the unselected top select transistor Q1. Note that the unselected top select transistor Q1 refers to the top select transistor Q1 that is in an off state before the third pass voltage Vpass3 is supplied. Of course, in another embodiment, the bottom select transistor Q2 of the unselected memory cell string 40 is only turned on during the pre-turn-on phase and is in the off state during the verify phase.
As shown in fig. 5, in the verify phase (T3-T4 period), a verify voltage Vv is supplied to the word line WL of the selected memory cell string 39 to check whether the threshold voltage (Vth) of the selected memory cell MC is a preset value; wherein the verify voltage Vv is lower than the second pass voltage Vpass 2. In one embodiment, the second pass voltage Vpass2 is greater than 0V and the verify voltage Vv is less than 0V. For example, the second pass voltage Vpass2 is 0.5V and the verify voltage Vv is-0.5V. Specifically, the first pass voltage Vpass1 is higher than the verify voltage Vv, and in one embodiment, the first pass voltage Vpass1 is greater than 5V.
It should be noted that, during the verification phase (time period T3 to T4), the number of the selected memory cells of the selected memory cell string 39 may be one, that is, the plurality of memory cells of the selected memory cell string 39 are verified one by one during the verification phase, for example, during the verification phase, the word line of the selected memory cells of the selected memory cell string 39 is provided with the verification voltage Vv, and the other word lines are provided with the pass voltages to open the channel; of course, the number of selected memory cells of the selected memory cell string 39 may also be multiple during the verify phase, i.e., multiple memory cells are simultaneously verified, e.g., during the verify phase, the verify voltage Vv is simultaneously supplied to the word lines of multiple selected memory cells of the selected memory cell string 39 to simultaneously verify the multiple memory cells.
It is to be understood that the WL in fig. 5 represents a word line of a selected memory cell in a selected memory cell string, the WL in fig. 6 represents a word line of a memory cell in an unselected memory cell string, and the word line of the memory cell is disposed on the same page as the word line of the selected memory cell in the selected memory cell string.
Also, in the verify phase, at least one of the top select transistor Q1 and the bottom select transistor Q2 of the unselected memory cell string 40 is put in an off state to set the unselected memory cell string 40 to a channel off state. For example, as shown in fig. 6, in the verify phase, an electrical signal of a low level is supplied to the top select gate line SGTL of the unselected memory cell string 40 to turn off the top select transistor Q1 of the unselected memory cell string 40.
It will be appreciated that during the verify phase, the word lines, top select gate lines and bottom select gate lines of the unselected memory cells of the selected memory cell string 39 are supplied with a turn-on voltage to ensure that the channel of the selected memory cell string 39 is open. And in the verify phase, the word lines of the memory cell strings of the unselected memory cell strings 40 are supplied with the same voltage as the word lines of the selected memory cell string 39 located in the same page, for example, in the verify phase, the word lines of the unselected memory cell strings 40 corresponding to the unselected memory cells of the selected memory cell string 39 are supplied with a verify voltage, and the other word lines are supplied with a turn-on voltage (not shown in fig. 5 and 6); of course, when all memory cells of the selected memory cell string 39 are selected, all word lines are supplied with the verify voltage Vv.
In another embodiment, the time of the pre-on phase of the selected memory cell string 39 may be greater than the time of the pre-on phase of the unselected memory cell strings 40. It will be appreciated that for the selected memory cell string 39, all word lines are still supplied with the second pass voltage Vpass2 during the initial phase of the verify phase to extend the discharge time of the channel of the selected memory cell string 39 to further reduce charge accumulation, after which the normal verify operation will be performed.
Of course, the erasing and verifying method provided by this embodiment further includes the following steps:
if the threshold voltage of the selected memory cell reaches a preset value in the verification stage, the verification is finished;
if the threshold voltage of the selected memory cell is not reached to the preset value in the verification stage, entering the next erasing operation and verification operation stage.
In this embodiment, after the erase operation is performed on the selected memory block, the verify operation is divided into a pre-turn-on phase and a verify phase. In the pre-conduction stage, the selected memory cell string and the unselected memory cell string in the plurality of memory cell strings are kept in a channel conduction state, so that the whole channels of the selected memory cell string and the unselected memory cell string are ensured to be conducted, on one hand, the influence of a strong electric field generated by a first conduction voltage Vpass1 on a virtual word line of a virtual memory cell DMC on the threshold voltage of part of memory cells MC in the unselected memory cell strings can be avoided, and therefore the risk of HCI is avoided, on the other hand, the phenomenon that the threshold voltage of the memory cells MC is too high due to incomplete erasing in the selected memory cell string can be avoided, and therefore the phenomenon that channel pinch occurs in the selected memory cell string (charge accumulation in the channel of the selected memory cell string is avoided), and therefore the risk of HCI is avoided. In the verification stage, because the pre-conduction stage finishes the evacuation (discharge process) of the accumulated charges in the selected memory cell string, even if the applied verification voltage is low, the phenomenon of channel pinch-off in the selected memory cell string can be avoided, so that the HCI risk caused by channel pinch-off is avoided. Therefore, the method and the device can avoid the HCI risk in the verification operation process, and are beneficial to improving the accuracy of the erasing verification of the semiconductor device.
Example two
The embodiment of the present application further provides an erasing and verifying method for a semiconductor device, which is different from the above embodiments in step S402. The embodiment can solve the negative influence of incomplete erasing on the verification process of the selected memory cell string.
In this embodiment, in the verification operation phase, the verification operation phase is sequentially divided into a pre-on phase and a verification phase; setting a selected memory cell string of the plurality of memory cell strings to a channel conduction state in a pre-conduction stage; in a verification phase, verifying the threshold voltage of a selected memory cell in a selected memory cell string; and the unselected memory cell strings are set to the channel off state throughout the verify operation phase.
Specifically, as shown in fig. 3, 7 and 8, during the whole verification operation phase (time period T2 to T4, including the pre-turn-on phase and the verification phase): providing a first pass voltage Vpass1 to a word line of each dummy memory cell DMC to pass a channel of each dummy memory cell DMC; also, the top select transistor Q1 and the bottom select transistor Q2 of the selected memory cell string 39 are turned on, and at least one of the top select transistor Q1 and the bottom select transistor Q2 of the unselected memory cell string 40 is turned off, e.g., the top select transistor Q1 of the unselected memory cell string 40 is turned off, while the bottom select transistor Q2 of the unselected memory cell string 40 is turned on; in addition, the common source line CSL and the P-type well region are grounded.
It should be noted that WL in fig. 7 represents a word line of a selected memory cell in a selected memory cell string, and the number of the selected memory cells may be one or multiple, which is not described herein again; WL in fig. 8 represents a word line of a memory cell in an unselected memory cell string, and the word line of the memory cell is disposed on the same page as the word line of a selected memory cell in a selected memory cell string.
As shown in fig. 7, in the pre-turn-on phase (time period T2 to T3), the second pass voltage Vpass2 is supplied to the word lines of the plurality of memory cells MC (including the selected memory cell and the unselected memory cell) of the selected memory cell string 39 among the plurality of memory cell strings to open the channels of the plurality of memory cells MC of the selected memory cell string 39. It is to be understood that, as shown in fig. 8, the word lines of the plurality of memory cells MC of the unselected memory cell string 40 are also supplied with the second pass voltage Vpass2 in the pre-pass phase.
As shown in fig. 7, in the verify phase (time period T3-T4), a verify voltage Vv is supplied to the word line of the selected memory cell MC of the selected memory cell string 39 to check whether the threshold voltage of the selected memory cell MC is a preset value.
In this embodiment, after the erase operation is performed on the selected memory block, the verify operation is divided into a pre-turn-on phase and a verify phase. In the pre-conduction stage, a selected memory cell string in the plurality of memory cell strings is kept in a channel conduction state to ensure that the whole channel of the selected memory cell string is conducted, so that the problem that the threshold voltage of the memory cell MC is too high due to incomplete erasing can be avoided, and the channel pinch-off phenomenon (charge accumulation in the channel of the selected memory cell string) in the selected memory cell string is avoided, thereby avoiding the risk of HCI. In the verification stage, because the pre-conduction stage finishes the evacuation (discharge process) of the accumulated charges of the selected memory cell string, even if the applied verification voltage is low, the phenomenon of channel pinch-off in the selected memory cell string can be avoided, so that the HCI risk caused by the channel pinch-off is avoided. Therefore, the method and the device can avoid the HCI risk in the verification operation process, and are beneficial to improving the accuracy of the erasing verification of the semiconductor device.
EXAMPLE III
The embodiment of the present application further provides an erasing and verifying method for a semiconductor device, which is different from the above embodiments in step S402. The present embodiment can solve the influence of a strong electric field generated by the first pass voltage Vpass1 on the dummy word line of the dummy memory cell DMC on the unselected memory cell strings.
In this embodiment, in the verification operation phase, the verification operation phase is sequentially divided into a pre-on phase and a verification phase; in a pre-conduction stage, setting unselected memory cell strings in the plurality of memory cell strings to be in a channel conduction state, and setting selected memory cell strings in the plurality of memory cell strings to be in a channel cutoff state; in the verify phase, unselected memory cell strings are set to a channel off state, and the threshold voltages of selected memory cells in the selected memory cell strings are verified.
Specifically, as shown in fig. 3, 9 and 10, during the whole verification operation phase (time period T2 to T4, including the pre-turn-on phase and the verification phase): providing a first pass voltage Vpass1 to a word line of each dummy memory cell DMC to pass a channel of each dummy memory cell DMC; also, the bottom select transistor Q2 of the selected memory cell string 39 and the bottom select transistor Q2 of the unselected memory cell string 40 are turned on; in addition, the common source line CSL and the P-type well region are grounded. Of course, in another embodiment, the bottom select transistor Q2 of the selected memory cell string 39 may be turned off only during the pre-turn-on phase and turned on during the verify phase; the bottom select transistor Q2 of the unselected memory cell string 40 may be turned on only during the pre-on phase and turned off during the verify phase.
It should be noted that WL in fig. 9 represents a word line of a selected memory cell in a selected memory cell string, and the number of the selected memory cells may be one or multiple, which is not described herein again; WL in fig. 10 represents a word line of a memory cell in an unselected memory cell string, and the word line of the memory cell is disposed on the same page as the word line of a selected memory cell in a selected memory cell string.
As shown in fig. 10, in the pre-turn-on phase (time period T2 to T3), the second turn-on voltage Vpass2 is supplied to the word lines WL of the plurality of memory cells MC of the unselected memory cell string 40 among the plurality of memory cell strings to open the channels of the plurality of memory cells MC of the unselected memory cell string 40. The second pass voltage Vpass2 may be applied in the form of a pre-pulse. It is to be understood that, as shown in fig. 9, during the pre-pass phase, word lines of a plurality of memory cells MC (including selected memory cells and unselected memory cells) of the selected memory cell string 39 are also supplied with the second pass voltage Vpass 2. Also, in the pre-on phase, the top select transistor Q1 of the selected memory cell string 39 is turned off, for example, as shown in fig. 9, the top select gate line SGTL of the selected memory cell string 39 is supplied with a low level voltage; and the top select transistor Q1 of the unselected memory cell string 40 is turned on, for example, as shown in fig. 10, the top select gate line SGTL of the unselected memory cell string 40 is supplied with a high level voltage.
Specifically, as shown in fig. 10, the bottom select transistor Q2 of the unselected memory cell string 40 remains in a conductive state throughout the verify operation phase, and then the third pass voltage Vpass3 may be provided to the top select gate line SGTL of the unselected top select transistor Q1 of the unselected memory cell string 40 during the pre-conduction phase to turn on the unselected top select transistor Q1. For example, during the pre-turn-on phase, a pre-pulse is applied to the unselected top select gate lines SGTL of the unselected memory cell strings 40 to open the channels of the unselected top select transistors, turning on the unselected top select transistors Q1.
As shown in fig. 9, in the verify phase (time period T3-T4), a verify voltage Vv is supplied to the word line of the selected memory cell MC of the selected memory cell string 39 to check whether the threshold voltage of the selected memory cell MC is a preset value. Also, during the verify phase, the top select transistor Q1 of the selected memory cell string 39 is turned on, and the top select transistor Q1 of the unselected memory cell string 40 is turned off.
In this embodiment, after the erase operation is performed on the selected memory block, the verify operation is divided into a pre-turn-on phase and a verify phase. In the pre-conduction stage, unselected memory cell strings in the plurality of memory cell strings are kept in a channel conduction state to ensure that the whole channel of the unselected memory cell strings is conducted, so that the influence of a strong electric field generated by a first conduction voltage on a virtual word line of a virtual memory cell DMC on the threshold voltage of part of memory cells MC in the unselected memory cell strings can be avoided, the threshold voltage of the memory cells MC after being erased is prevented from being higher, and on the other hand, the charge accumulation in the channel of the unselected memory cell strings can be avoided, so that the risk of HCI is avoided, and the accuracy of the erasing verification of the semiconductor device is improved.
Example four
As shown in fig. 1 and 2, the embodiment of the present application also provides a semiconductor device 20, in particular, a 3D NAND memory device 10. The semiconductor device 20 includes a plurality of memory BLOCKs, which constitute the memory array 11, and a control circuit 12. Wherein a selected memory block of the plurality of memory blocks comprises a plurality of memory cell strings 21 (e.g., NAND strings 13), each memory cell string 21 comprising a plurality of memory cells MC and at least one virtual memory cell DMC arranged in series; the control circuit 12 is in signal connection with the plurality of memory blocks and is configured to perform any one of the erasing and verifying methods of the first embodiment, the second embodiment, and the third embodiment.
In particular, the control circuit 12 may include word line drivers, bit line drivers, column decoders, sense circuits, data buffers, program verify logic, and erase verify circuitry. The structure of the memory block can refer to the structure in the above embodiments, and is not described herein again.
In this embodiment, the semiconductor device 20 can avoid the HCI risk during the verification operation, which is beneficial to improving the accuracy of the erase verification of the semiconductor device 20.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing detailed description is directed to a semiconductor device and an erasing and verifying method for a semiconductor device provided in the embodiments of the present application, and specific examples are applied herein to explain the principles and implementations of the present application, and the descriptions of the foregoing embodiments are only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (12)

1. An erasing and verifying method for a semiconductor device, wherein the semiconductor device includes a plurality of memory blocks, selected ones of the plurality of memory blocks including a plurality of memory cell strings; each of the memory cell strings includes a plurality of memory cells arranged in series;
the erasing and verifying method comprises the following steps:
erasing a plurality of memory cells in each of the memory cell strings during an erase operation;
in a verification operation stage, a pre-conduction stage and a verification stage are included, the plurality of memory cell strings comprise selected memory cell strings and unselected memory cell strings, and the selected memory cell strings are to-be-verified memory cell strings;
setting at least one of the selected memory cell string and the unselected memory cell string to a channel conducting state in the pre-conduction phase; in the verify phase, a threshold voltage of at least one memory cell in the selected memory cell string is verified, and the unselected memory cell strings are set to a channel off state.
2. An erasing and verifying method for a semiconductor device according to claim 1, wherein each of said memory cell strings further includes at least one dummy memory cell provided in series with said plurality of memory cells;
the erase and verify method further comprises:
providing a first turn-on voltage to a word line of the at least one dummy memory cell to turn on a channel of the at least one dummy memory cell in the pre-turn-on phase and the verification phase.
3. An erase and verify method for a semiconductor device, according to claim 2, wherein each of said memory cell strings further comprises a top select transistor and a bottom select transistor, said plurality of memory cells and said at least one dummy memory cell being located between and arranged in series with said top select transistor and said bottom select transistor;
the erase and verify method further comprises:
in the pre-turn-on phase and the verify phase, a top select transistor and a bottom select transistor of the selected memory cell string are turned on.
4. An erase and verify method for a semiconductor device according to claim 3, wherein said setting at least one of said selected memory cell string and said unselected memory cell string to a channel conducting state comprises the steps of:
providing a second turn-on voltage to word lines of a plurality of memory cells of the selected memory cell string;
the verifying a threshold voltage of at least one memory cell in the selected memory cell string comprises:
providing a verification voltage to a word line of at least one memory cell in the selected memory cell string to check whether a threshold voltage of the at least one memory cell is a preset value; wherein the verify voltage is lower than the second turn-on voltage.
5. The erase and verify method for a semiconductor device, according to claim 4, wherein said setting at least one of said selected memory cell string and said unselected memory cell string to a channel conducting state, further comprises the steps of:
the second turn-on voltage is provided to word lines of a plurality of memory cells of the unselected memory cell string, and a top select transistor and a bottom select transistor of the unselected memory cell string are turned on.
6. An erase and verify method for a semiconductor device according to claim 3, wherein said setting at least one of said selected memory cell string and said unselected memory cell string to a channel conducting state comprises the steps of:
a second turn-on voltage is provided to word lines of a plurality of memory cells of the unselected memory cell string, and a top select transistor and a bottom select transistor of the unselected memory cell string are turned on.
7. The erase and verify method for a semiconductor device according to claim 5 or 6, further comprising:
during the pre-turn-on phase and the verify phase, the bottom select transistor of the unselected memory cell string remains in a conductive state;
said turning on top and bottom select transistors of said unselected memory cell strings comprises the steps of:
providing a third turn-on voltage to an unselected top select transistor of the unselected memory cell string to turn on the unselected top select transistor.
8. The erasing and verifying method for a semiconductor device as claimed in claim 4, wherein the second turn-on voltage is greater than 0V, and the verifying voltage is less than 0V.
9. The erasing and verifying method for a semiconductor device according to claim 4, wherein the first turn-on voltage is higher than the verifying voltage.
10. An erase and verify method for a semiconductor device according to claim 2, wherein said semiconductor device comprises a plurality of stacked layers arranged in a stack; the stacked layer comprises a plurality of gate layers and dielectric layers which are alternately stacked; the plurality of strings of memory cells extend vertically through the plurality of stack layers;
each said string of storage units comprises a string of child storage units located in each said stack layer, and said at least one virtual storage unit is located between any two adjacent strings of said child storage units; the sub memory cell string includes the plurality of memory cells.
11. The erase and verify method for a semiconductor device, according to claim 2, wherein each of the memory cell strings further comprises a top select transistor and a bottom select transistor, the plurality of memory cells and the at least one dummy memory cell being arranged in series with and between the top select transistor and the bottom select transistor;
the at least one dummy memory cell is located between the top select transistor and the plurality of memory cells, or between the plurality of memory cells and the bottom select transistor, or between any two adjacent memory cells.
12. A semiconductor device, comprising:
a plurality of memory blocks, selected ones of the plurality of memory blocks comprising a plurality of memory cell strings, each of the memory cell strings comprising a plurality of memory cells arranged in series;
a control circuit in signal connection with the plurality of memory blocks; the control circuit is configured to perform the erase and verify method of any of claims 1 to 11.
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