CN112687316A - Method and device for improving read-write speed and NAND flash memory - Google Patents
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Abstract
The embodiment of the invention provides a method and a device for improving read-write speed and a NAND flash memory, wherein the NAND flash memory comprises an SRAM, N register areas connected with the SRAM and N charging selection signals in one-to-one correspondence with the N register areas, the period of the N charging selection signals comprises delay time, time delay exists among the N charging selection signals, the delay time in the N charging selection signal periods is equal to the routing delay of the register selection signals of the N register areas after being superposed, and the method comprises the following steps: receiving a register address; determining a register area to be read and written according to the register address; and setting the charging selection signal corresponding to the register area to be read and written to be effective. The invention effectively reduces the time of reading and writing the register by the SRAM and greatly improves the speed of reading and writing the register by the SRAM.
Description
Technical Field
The invention relates to the technical field of storage, in particular to a method for improving read-write speed, a device for improving read-write speed and a NAND flash memory.
Background
NAND Flash (Flash memory) is a non-volatile memory, has the advantages of large storage capacity, large data throughput, and the like, and is widely applied to various electronic products. The NAND Flash reads and writes the memory array unit according to Page capacity, and the common Page capacity is 1KB/2KB/4KB/16KB and the like. The number of registers of the NAND Flash is consistent with the size of the Page capacity, the registers are used for storing data input and data output according to read-write addresses, and thousands of registers in the NAND Flash are sequentially and transversely arranged.
The prior art adopts the following method to realize the reading and writing of the register by the SRAM: setting a charging selection signal PREB 'to be effective, charging bus nodes Q and QB between the SRAM and the register, decoding a register selection signal SELC' corresponding to the register according to the register address, setting the register selection signal SELC 'to be effective, enabling the register corresponding to the register selection signal SELC' to be connected with the bus nodes Q and QB, and reading and writing the register by the SRAM. The circuit structure of the NAND Flash for reading and writing data from and from the register through the SRAM is shown in fig. 1.
The mode of reading and writing the register by the SRAM in the prior art also has the following defects: because thousands of registers in the NAND Flash are sequentially and laterally arranged, a fixed total routing delay time tdly ' exists between the register selection signal SELC1 ' with the closest routing in the NAND Flash and the register selection signal SELCN ' with the farthest routing. Since one SRAM in the NAND Flash is connected to many registers, that is, bus nodes Q and QB between the SRAM and the registers are connected to many registers, in order to ensure that the charge selection signal PREB 'and the register selection signal SELCN' are not valid at the same time, the falling edge of the charge selection signal PREB 'must wrap the falling edge of the register selection signal SELCN' farthest from the trace. At this time, the waveforms of the charge selection signal PREB ', the register selection signal SELC1 ', and the register selection signal SELCN ' are as shown in fig. 2. Therefore, the period of the SRAM read/write register is increased by tdly ', the speed of the SRAM read/write register is slowed down, and the larger the Page capacity of the NAND Flash is, the longer the routing of the register selection signal SELCN ' will be, and the larger the tdly ', the larger the period of the SRAM read/write register will be, thereby limiting the read/write frequency on the large-capacity NAND Flash interface.
Disclosure of Invention
In view of the foregoing problems, an object of the embodiments of the present invention is to provide a method for increasing a read/write speed, an apparatus for increasing a read/write speed, and a NAND flash memory, so as to solve the problem of slow read/write speed in the prior art in which an SRAM reads and writes a register.
In order to solve the above problem, an embodiment of the present invention discloses a method for increasing a read-write speed, which is applied to a NAND flash memory, where the NAND flash memory includes a SRAM, N register areas connected to the SRAM, and N charge selection signals in one-to-one correspondence with the N register areas, a cycle of the N charge selection signals includes a delay time, the N charge selection signals have a time delay with each other, and the delay time in the N charge selection signal cycles is equal to a total delay time of routing of the register selection signals of the N register areas after being superimposed, and the method includes:
receiving a register address;
determining a register area to be read and written according to the register address;
and setting the charging selection signal corresponding to the register area to be subjected to the read-write operation to be effective.
Optionally, the determining, according to the register address, a register area to be subjected to a read-write operation includes:
determining the register area to be read and written according to the high K bit address of the register address; wherein N is 2K。
Optionally, a falling edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is behind a falling edge of the register selection signal of the mth register in the register area to be subjected to the read-write operation; and the Mth register is a register with the farthest routing of the register selection signal in the register area to be subjected to the read-write operation.
Optionally, a rising edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is before a rising edge of the register selection signal of the first register in the register area to be subjected to the read-write operation; the first register is the register with the nearest routing of the register selection signal in the register area to be read and written.
In order to solve the above problem, an embodiment of the present invention further discloses a device for increasing a read-write speed, which is applied to a NAND flash memory, where the NAND flash memory includes a SRAM, N register areas connected to the SRAM, and N charge selection signals in one-to-one correspondence with the N register areas, a cycle of the N charge selection signals includes a delay time, the N charge selection signals have a time delay from each other, and the delay time in the N charge selection signal cycles is equal to a total delay time of routing register selection signals of the N register areas after being superimposed, and the device includes:
the receiving module is used for receiving the register address;
the register area determining module is used for determining a register area to be read and written according to the register address;
and the setting module is used for setting the charging selection signal corresponding to the register area to be subjected to the read-write operation to be effective.
Optionally, the register area determination module includes:
the register area determining unit is used for determining the register area to be read and written according to the high-K bit address of the register address; wherein N is 2K。
Optionally, a falling edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is behind a falling edge of the register selection signal of the mth register in the register area to be subjected to the read-write operation; and the Mth register is a register with the farthest routing of the register selection signal in the register area to be subjected to the read-write operation.
Optionally, a rising edge of the charging selection signal corresponding to the register area to be subjected to the read-write operation is before a rising edge of the register selection signal of the first register in the register area to be subjected to the read-write operation; the first register is the register with the nearest routing of the register selection signal in the register area to be read and written.
In order to solve the above problem, an embodiment of the present invention further discloses a NAND flash memory, where the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charging selection signals in one-to-one correspondence with the N register areas, a cycle of the N charging selection signals includes delay time, time delay exists between the N charging selection signals, and the delay time in the N charging selection signal cycles is equal to total delay time of routing of the register selection signals of the N register areas after being superimposed.
Optionally, the N register areas have the same size, the delay time difference of the charging selection signals corresponding to two adjacent register areas is total delay time/N of the register selection signal routing, and the total delay time of the register selection signal routing is the register selection signal routing delay between the register in the N register areas where the register selection signal routing is closest and the register in the N register areas where the register selection signal routing is farthest.
The embodiment of the invention has the following advantages: the NAND flash memory comprises an SRAM, N register areas connected with the SRAM and N charging selection signals in one-to-one correspondence with the N register areas, the period of the N charging selection signals comprises delay time, time delay exists among the N charging selection signals, and the delay time in the N charging selection signal periods is equal to the total delay time of routing of the register selection signals of the N register areas after being overlapped. After receiving the register address, determining a register area to be read and written according to the register address, and further setting the charging selection signal corresponding to the register area to be read and written to be effective. Therefore, the invention selects the charging selection signal by regions through the register address, the delay time in the period of the charging selection signal is far shorter than the routing delay, the time for the SRAM to read and write the register is effectively reduced, the speed for the SRAM to read and write the register is greatly improved, the read and write frequency on a high-capacity NAND flash memory interface is convenient to improve, and the realization is simple.
Drawings
FIG. 1 is a schematic diagram of a circuit structure of a NAND Flash for reading and writing data from a register through an SRAM in the prior art;
fig. 2 is a schematic diagram of a waveform of a charge selection signal PREB ', a waveform of a register selection signal SELC1 ', and a waveform of a register selection signal SELCN ' in the prior art;
FIG. 3 is a flowchart illustrating steps of an embodiment of a method for improving read/write speed according to the present invention;
FIG. 4 is a flow chart illustrating steps of another embodiment of a method for improving read/write speed;
FIG. 5 is a block diagram of an embodiment of an apparatus for increasing read/write speed according to the present invention;
FIG. 6 is a block diagram of an embodiment of an apparatus for increasing read/write speed according to the present invention;
FIG. 7 is a block diagram of the structure of one embodiment of a NAND flash memory of the present invention;
FIG. 8 is a circuit diagram of the SRAM reading data from the register in the NAND flash memory embodiment of the present invention;
FIG. 9 is a timing diagram of the SRAM reading and writing of the first register in the first register area in one embodiment of the NAND flash memory of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 3, it shows a flowchart of steps of an embodiment of a method for increasing a read-write speed according to the present invention, where the method for increasing a read-write speed is applied to a NAND flash memory, the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charge selection signals in one-to-one correspondence with the N register areas, a cycle of the N charge selection signals includes a delay time, time delays exist between the N charge selection signals, and the delay time in the N charge selection signal cycles is overlapped to be equal to a total delay time of register selection signal routing of the N register areas. Wherein, N register areas are transversely distributed into a row in turn. N is an integer greater than or equal to 2.
Optionally, when the sizes of the N register areas are the same, the delay time difference value of the charging selection signals corresponding to two adjacent register areas is the total delay time/N of the routing of the register selection signals. The total delay time of the register selection signal routing is the register selection signal routing delay between the register with the nearest register selection signal routing in the N register areas and the register with the farthest register selection signal routing.
For example, if N register areas are four register areas, the four register areas have the same size, and the total delay time of the register selection signal routing lines in the four register areas is tdly, the delay time included in the cycle of the N charging selection signals is tdly/4, the delay time difference of the charging selection signals corresponding to two adjacent register areas is tdly/4, and at this time, the cycle of the N charging selection signals is reduced by 3 tdly/4.
Referring to fig. 3, the method may specifically include the following steps:
s1, receiving the register address.
The register address is the read-write address of the register.
And S2, determining the register area to be read and written according to the register address.
For example, assuming that the N register areas are 2 register areas (a first register area and a second register area), if the register address is the address of the first register area, step S2 determines that the register area to be subjected to the read/write operation is the first register area, and if the register address is the address of the second register area, step S2 determines that the register area to be subjected to the read/write operation is the second register area.
And S3, setting the charging selection signal corresponding to the register area to be read and written to be effective.
Specifically, although the delay time in the charge selection signal period corresponding to the register area to be subjected to the read-write operation in step S3 is much shorter than the total delay time of the routing, since the size of the register area to be subjected to the read-write operation is much smaller than the size of all registers in the NAND flash memory, the register selection signal routing delay between the register closest to the register selection signal routing in the register area and the register farthest from the register selection signal routing is also much shorter than the total delay time of the routing. Therefore, after step S3, the SRAM can still correctly read and write the register area to be read and written. Because the delay time in the charging selection signal period corresponding to the register area to be read and written is far shorter than the total routing delay time, the method for improving the read and write speed effectively reduces the time for reading and writing the register of the SRAM and greatly improves the speed for reading and writing the register of the SRAM.
Optionally, in another embodiment of the present invention, referring to fig. 4, the step S2 determining, according to the register address, a register area to be read or written, may include:
s21, determining a register area to be read and written according to the high K bit address of the register address; wherein N is 2K。
For example, if N is 2, that is, the NAND flash memory includes 2 register areas (a first register area and a second register area), K is 1. At this time, if the high K bit address of the register address is 0, step S21 determines that the register area to be read/written is the first register area, and if the high K bit address of the register address is 1, step S21 determines that the register area to be read/written is the second register area; or, if the high K bit address of the register address is 1, step S21 determines that the register area to be read/written is the first register area, and if the high K bit address of the register address is 0, step S21 determines that the register area to be read/written is the second register area.
Optionally, in an embodiment of the present invention, a falling edge of the charging selection signal corresponding to the register area to be subjected to the read/write operation is after a falling edge of the register selection signal of the mth register in the register area to be subjected to the read/write operation; the Mth register is a register with the farthest routing of the register selection signal in the register area to be read and written. Therefore, the situation that the charging selection signal and the register selection signal are simultaneously effective can be avoided when the register area to be read and written is read and written, and the data in the register can be protected.
Optionally, in an embodiment of the present invention, a rising edge of the charging selection signal corresponding to the register area to be subjected to the read/write operation is before a rising edge of the register selection signal of the first register in the register area to be subjected to the read/write operation; the first register is a register with the nearest routing of the register selection signal in the register area to be read and written. Therefore, the situation that the charging selection signal and the register selection signal are simultaneously effective can be avoided when the register area to be read and written is read and written, and the data in the register can be protected.
The method for improving the read-write speed of the embodiment of the invention has the following advantages: the NAND flash memory comprises an SRAM, N register areas connected with the SRAM and N charging selection signals in one-to-one correspondence with the N register areas, the period of the N charging selection signals comprises delay time, time delay exists among the N charging selection signals, and the delay time in the N charging selection signal periods is equal to the total delay time of routing of the register selection signals of the N register areas after being overlapped. After receiving the register address, determining a register area to be read and written according to the register address, and further setting the charging selection signal corresponding to the register area to be read and written to be effective. Therefore, the invention selects the charging selection signal by regions through the register address, the delay time in the period of the charging selection signal is far shorter than the routing delay, even if the Page capacity of the NAND Flash and the total delay time of the routing of the register selection signal of N register regions are very large, the time for reading and writing the register of the SRAM can be effectively reduced, the speed for reading and writing the register of the SRAM is greatly improved, the reading and writing frequency on a high-capacity NAND Flash interface is convenient to improve, and the realization is simple.
It should be noted that, for simplicity of description, the method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the illustrated order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments of the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Referring to fig. 5, a block diagram of an embodiment of an apparatus for increasing a read/write speed according to the present invention is shown, where the apparatus for increasing a read/write speed is applied to a NAND flash memory, the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charge selection signals in one-to-one correspondence with the N register areas, a cycle of the N charge selection signals includes a delay time, time delays exist between the N charge selection signals, and the sum of the delay times in the N charge selection signal cycles is equal to a total delay time of register selection signal routing of the N register areas. Wherein N is an integer greater than or equal to 2.
Optionally, in an embodiment of the present invention, the N register areas have the same size, and the delay time difference of the charging selection signals corresponding to two adjacent register areas is the total delay time/N of the routing of the register selection signal. The total delay time of the register selection signal routing is the register selection signal routing delay between the register with the nearest register selection signal routing in the N register areas and the register with the farthest register selection signal routing.
Referring to fig. 5, the apparatus for increasing the read/write speed may specifically include the following modules:
and the receiving module 1 is used for receiving the register address.
And the register area determining module 2 is used for determining the register area to be read and written according to the register address.
And the setting module 3 is used for setting the charging selection signal corresponding to the register area to be subjected to the read-write operation to be effective.
Alternatively, in another embodiment of the present invention, referring to fig. 6, the register area determination module 2 may include:
a register area determining unit 21, configured to determine, according to a high-K bit address of a register address, a register area to be subjected to a read-write operation; wherein N is 2K。
Optionally, in an embodiment of the present invention, a falling edge of the charging selection signal corresponding to the register area to be subjected to the read/write operation is after a falling edge of the register selection signal of the mth register in the register area to be subjected to the read/write operation; the Mth register is a register with the farthest routing of the register selection signal in the register area to be read and written.
Optionally, in an embodiment of the present invention, a rising edge of the charging selection signal corresponding to the register area to be subjected to the read/write operation is before a rising edge of the register selection signal of the first register in the register area to be subjected to the read/write operation; the first register is a register with the nearest routing of the register selection signal in the register area to be read and written.
The device for improving the reading and writing speed of the embodiment of the invention has the following advantages: the NAND flash memory comprises an SRAM, N register areas connected with the SRAM and N charging selection signals in one-to-one correspondence with the N register areas, the period of the N charging selection signals comprises delay time, time delay exists among the N charging selection signals, and the delay time in the N charging selection signal periods is equal to the total delay time of routing of the register selection signals of the N register areas after being overlapped. After receiving the register address, determining a register area to be read and written according to the register address, and further setting the charging selection signal corresponding to the register area to be read and written to be effective. Therefore, the invention selects the charging selection signal by regions through the register address, the delay time in the period of the charging selection signal is far shorter than the routing delay, even if the Page capacity of the NAND Flash and the total delay time of the routing of the register selection signal of N register regions are very large, the time for reading and writing the register of the SRAM can be effectively reduced, the speed for reading and writing the register of the SRAM is greatly improved, the reading and writing frequency on a high-capacity NAND Flash interface is convenient to improve, and the realization is simple.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
Referring to FIG. 7, a block diagram of a NAND flash memory embodiment of the present invention is shown. The NAND flash memory comprises an SRAM, N register areas (such as a first register area, … … and an Nth register area) connected with the SRAM, and N charging selection signals (such as first charging selection signals PREB1, … … and an Nth charging selection signal PREBN) corresponding to the N register areas in a one-to-one mode, wherein the cycle of the N charging selection signals comprises delay time, the N charging selection signals have time delay, and the sum of the delay time in the cycle of the N charging selection signals is equal to the total delay time of register selection signal routing of the N register areas. Wherein N is an integer greater than or equal to 2.
Specifically, when the SRAM reads and writes N register areas, the SRAM first receives a register address, then determines a register area to be subjected to a read/write operation according to the register address, and then sets the charging selection signal corresponding to the register area to be subjected to the read/write operation to be valid. Because the delay time in the charging selection signal period corresponding to the register area to be read and written is far shorter than the total routing delay time, the NAND flash memory provided by the embodiment of the invention can effectively reduce the time for reading and writing the register of the SRAM and greatly improve the speed for reading and writing the register of the SRAM.
Optionally, in an embodiment of the present invention, the NAND flash memory may determine, by the decoder, the register area to be subjected to the read/write operation according to the register address, where the decoder may determine the register area to be subjected to the read/write operation according to a high-K bit address of the register address. Alternatively, in one embodiment of the present invention, the NAND flash memory may delay the N charge selection signals by a delay circuit so that the N charge selection signals have a time delay from each other. Optionally, in an embodiment of the present invention, the NAND flash memory may select, by the selector, the charging selection signal corresponding to the register area to be subjected to the read-write operation, and set the charging selection signal corresponding to the register area to be subjected to the read-write operation to be valid.
Optionally, in an embodiment of the present invention, the N register areas have the same size, and the delay time difference of the charging selection signals corresponding to two adjacent register areas is the total delay time/N of the routing of the register selection signal. The total delay time of the register selection signal routing is the register selection signal routing delay between the register with the nearest register selection signal routing in the N register areas and the register with the farthest register selection signal routing.
Optionally, in an embodiment of the present invention, a falling edge of the charging selection signal is after a falling edge of the register selection signal of the mth register in the corresponding register area; the Mth register is a register with the farthest routing of the register selection signal in the register area.
Optionally, in an embodiment of the present invention, a rising edge of the charging selection signal precedes a rising edge of the register selection signal of the first register in the corresponding register area; the first register is a register with the nearest routing of the register selection signal in the register area.
In an embodiment of the present invention, a circuit structure of the SRAM in the NAND flash memory for reading data from the register may be as shown in fig. 8, where a PREB signal is a charge selection signal corresponding to a register area to be read and written among the N charge selection signals, and a SELC signal is a register selection signal corresponding to a register to be read and written. It is assumed that the NAND flash memory includes four register areas (a first register area, a second register area, a third register area, and a fourth register area), N charge select signals are PREB1, PREB2, PREB3, and PREB4, respectively, and the NAND flash memory includes W registers (a first register, … …, and a W-th register).
For example, the process of the SRAM in fig. 8 reading and writing the first register in the first register area is as follows:
the SRAM reads the first register: the charge select signal PREB1 is 0, and the power supply charges the bus nodes Q and QB between the SRAM and the first register to the voltage VDD. The selection signal SELC1 of the first register is 1, and if FLG is 0 and INV is 1, the bus node Q discharges FLG, and the bus node QB is maintained at VDD. The selection signal SELC1 of the first register is 0, and the SRAM amplifies the voltage difference (e.g., 100mv) of QB-Q to a full-swing signal "0" and outputs it through DOUT. The selection signal SELC of the first register is 1, and if FLG is 1 and INV is 0, the bus node Q is maintained at VDD, and the bus node QB discharges INV. The selection signal SELC1 of the first register is 0, and the SRAM amplifies the voltage difference of Q-QB to a full-swing signal "1" and outputs the full-swing signal "1" through DOUT.
The SRAM writes a first register: the charge select signal PREB1 is 0, and the power supply charges the bus nodes Q and QB between the SRAM and the first register to the voltage VDD. When the select signal SELC1 of the first register is equal to 1 and DIN is equal to 0, the SRAM discharges the voltage of the bus node Q to 0, the bus node QB is maintained at VDD, and thus 0 is input to the FLG, SELC1 is turned off, and writing "0" is completed.
SELC1 is turned on, and if DIN is 1, SRAM discharges QB to 0 and Q is maintained at VDD, thereby inputting 1 to FLG, SELC1 is turned off, completing writing "1".
As shown in fig. 9, the timing for reading and writing the first register by the SRAM is a period (trd) of the PREB1, which is a period for reading and writing the register by the SRAM, and is composed of a minimum high level time (th) of the SELC1, a minimum low level time (tl) of the PREB1, and a delay time (total trace delay time/4). The minimum high time of SELC1 is limited by the read accuracy of SRAM, e.g., if the read accuracy of SRAM is 100mV, the minimum high time (th) of SELC1 is the time for bus nodes Q and QB to discharge to 100mV differential. The minimum low time of PREB1 is limited by the time PREB1 recharges the bus node Q voltage and QB voltage back to voltage VDD. Since the delay time is only 1/4 of the total trace delay time, the period of PREB1 is effectively reduced, i.e. the speed of SRAM reading and writing the first register is effectively increased. In fig. 9, tdly is the total delay time of the trace.
The NAND flash memory of the embodiment of the present invention includes the following advantages: the NAND flash memory comprises an SRAM, N register areas connected with the SRAM and N charging selection signals in one-to-one correspondence with the N register areas, the period of the N charging selection signals comprises delay time, time delay exists among the N charging selection signals, and the delay time in the N charging selection signal periods is equal to the total delay time of routing of the register selection signals of the N register areas after being overlapped. After receiving the register address, determining a register area to be read and written according to the register address, and further setting the charging selection signal corresponding to the register area to be read and written to be effective. Therefore, the invention selects the charging selection signal by regions through the register address, the delay time in the period of the charging selection signal is far shorter than the routing delay, even if the Page capacity of the NAND Flash and the total delay time of the routing of the register selection signal of N register regions are very large, the time for reading and writing the register of the SRAM can be effectively reduced, the speed for reading and writing the register of the SRAM is greatly improved, the reading and writing frequency on a high-capacity NAND Flash interface is convenient to improve, and the realization is simple.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The method and the apparatus provided by the present invention are described in detail, and the principle and the embodiment of the present invention are explained by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
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| CN201910990385.3A CN112687316B (en) | 2019-10-17 | A method and device for improving read and write speed and NAND flash memory |
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| CN201910990385.3A CN112687316B (en) | 2019-10-17 | A method and device for improving read and write speed and NAND flash memory |
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