CN112684642A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN112684642A CN112684642A CN202011397686.4A CN202011397686A CN112684642A CN 112684642 A CN112684642 A CN 112684642A CN 202011397686 A CN202011397686 A CN 202011397686A CN 112684642 A CN112684642 A CN 112684642A
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Abstract
The application discloses display panel and display device, display panel includes: the chip-on-film transistor comprises a first substrate, a second substrate, a source electrode chip-on-film, a grid electrode chip-on-film, a printed circuit board, wiring and a conductive structure, wherein the second substrate is arranged opposite to the first substrate; the wires comprise a first wire and a second wire, and the first wire and the second wire are used for communicating the printed circuit board and the grid chip on film; the first routing is arranged on the first substrate; the second routing is arranged on the first substrate and the second substrate; the conductive structure conducts the part of the second routing wire on the first substrate with the part of the second routing wire on the second substrate; the problem of capacitive coupling of the wires is solved, and therefore the display effect is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
Liquid Crystal Displays (LCDs) have many advantages such as thin body, power saving, no radiation, and the like, and are widely used. Most of the existing liquid crystal display devices in the market are backlight liquid crystal display devices, which include a liquid crystal display panel and a backlight module (backlight module). Generally, a Liquid Crystal display panel includes a Color Filter (CF) substrate, a Thin Film Transistor (TFT) substrate, a Liquid Crystal (LC) sandwiched between the Color Filter substrate and the TFT substrate, and a Sealant.
The TFT substrate is provided with a bonding region for bonding a source Chip On Film (COF) and a gate Chip On Film (PCBA) to transmit a signal of a Printed Circuit Board (Printed Circuit Board Assembly, PCBA) to the display panel, wherein wires between the source Chip On Film and the gate Chip On Film interfere with each other, which affects a display effect.
Disclosure of Invention
The application aims at providing a display panel and a display device, which improve the capacitive coupling phenomenon of wiring, thereby improving the display effect.
The application discloses display panel includes: the chip-on-film transistor comprises a first substrate, a second substrate, a source electrode chip-on-film, a grid electrode chip-on-film, a printed circuit board, wiring and a conductive structure, wherein the second substrate is arranged opposite to the first substrate; the source electrode flip chip film is bound on one side of the first substrate; the grid flip chip film is bound on the other side of the first substrate; the printed circuit board is connected to one side of the first substrate through the source electrode chip on film, the wires comprise a first wire and a second wire, and the first wire and the second wire are used for communicating the printed circuit board and the grid electrode chip on film; the first wires are arranged on the source electrode chip on film and the first substrate; the second wires are arranged on the source electrode chip on film, the first substrate and the second substrate; the conductive structure connects the portion of the second trace on the first substrate with the portion of the second trace on the second substrate.
Optionally, the second trace includes a first trace segment, a second trace segment and a third trace segment that are sequentially connected, the first trace segment is disposed at a position of the first substrate close to the source electrode chip on film, the second trace segment is disposed on the second substrate, and the third trace segment is disposed at a position of the first substrate close to the gate electrode chip on film; the first routing section is communicated with the second routing section through the conductive structure, and the second routing section is communicated with the third routing section through the conductive structure.
Optionally, the first substrate is an array substrate, the second substrate is a color film substrate, a color filter and a common electrode layer are arranged on the color film substrate, and the second routing segment and the common electrode layer are formed through the same process and are insulated from each other.
Optionally, the second routing segment is disposed in the non-display area of the color film substrate.
Optionally, the vertical projection parts of the first running line segment and the second running line segment are overlapped to form a first overlapping part, and the vertical projection parts of the second running line segment and the third running line segment are overlapped to form a second overlapping part; the conductive structure comprises a first conductive gold ball and a second conductive gold ball, the first overlapping portion is provided with the first conductive gold ball to communicate the first running line segment with the second running line segment, and the second overlapping portion is also provided with the second conductive gold ball to communicate the second running line segment with the third running line segment.
Optionally, the vertical projection parts of the first running line segment and the second running line segment are overlapped to form a first overlapping part, and the vertical projection parts of the second running line segment and the third running line segment are overlapped to form a second overlapping part; the conductive structure comprises a first spacing unit and a second spacing unit, conductive layers are respectively arranged on the surfaces of the first spacing unit and the second spacing unit, the first overlapping portion is provided with the first spacing unit so as to communicate the first route segment with the second route segment, and the second overlapping portion is also provided with the second spacing unit so as to communicate the second route segment with the third route segment.
Optionally, the vertical projection parts of the first running line segment and the second running line segment are overlapped to form a first overlapping part, and the vertical projection parts of the second running line segment and the third running line segment are overlapped to form a second overlapping part; the conductive structure comprises a spacing unit and a conductive gold ball, and a conductive layer is arranged on the surface of the spacing unit; the first overlapping part is provided with the conductive gold ball to communicate the first route segment with the second route segment, and the second overlapping part is also provided with the spacing unit to communicate the second route segment with the third route segment.
Optionally, the first substrate is an array substrate, the second substrate is a color film substrate, the first trace is a control signal line for transmitting a control signal, and the second trace is a power signal line for transmitting a power signal.
The application also discloses a display panel, display panel is divided into display area and non-display area, display panel includes: the chip package structure comprises a first substrate, a second substrate, a source electrode chip on film, a grid electrode chip on film, a printed circuit board and wires, wherein the second substrate is arranged opposite to the first substrate; the source electrode flip chip film is bound on one side of the first substrate; the grid flip chip film is bound on the other side of the first substrate; the wiring is arranged in the non-display area, and the printed circuit board outputs a power supply signal and a control signal to the grid flip chip film through the wiring; the wires comprise a first wire and a second wire, and the first wire transmits a control signal to the grid flip chip film; the second wire transmits a power signal to the grid flip chip film; the first wires are sequentially arranged on the source electrode chip on film and the first substrate; the second routing comprises a first routing section, a second routing section and a third routing section which are sequentially communicated, the first routing section is arranged at the position, close to the source electrode chip on film, of the first substrate, the second routing section is arranged on the second substrate, and the third routing section is arranged at the position, close to the gate electrode chip on film, of the first substrate;
the first substrate is an array substrate, the second substrate is a color film substrate, a color filter and a common electrode layer are arranged on the color film substrate, and the second route section and the common electrode layer are formed through the same process and are mutually insulated; the vertical projection parts of the first running line segment and the second running line segment are overlapped to form a first overlapping part, and the vertical projection parts of the second running line segment and the third running line segment are overlapped to form a second overlapping part; the conductive structure comprises a conductive gold ball, the conductive gold ball is arranged on the first overlapping part to communicate the first route segment with the second route segment, and the conductive gold ball is also arranged on the second overlapping part to communicate the second route segment with the third route segment; the second wiring is a control signal line and is used for transmitting control signals, and the first wiring is a power signal line and is used for transmitting power signals.
The application also discloses a display device which comprises the display panel and a driving circuit for driving the display panel.
Compared with the scheme that the wires between the source electrode chip on film and the grid electrode chip on film are arranged on the same substrate, the wire arrangement between the source electrode chip on film and the grid electrode chip on film is improved, the first wires are arranged on the first substrate, and the second wires are arranged on the second substrate; because the box thickness with a certain thickness is formed between the first substrate and the second substrate, a certain distance exists between the first substrate and the second substrate, so that the distance between the first routing and the second routing is increased, and further, the coupling capacitance between the first routing and the second routing is reduced, and the mutual interference between the first routing and the second routing is weakened; the problem of parasitic capacitance is improved, and the mutual interference phenomenon between the first wiring and the second wiring is improved, so that the display effect of the display panel is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic diagram of a display panel according to an embodiment of the present application;
fig. 2 is a schematic diagram of traces of a display device according to an embodiment of the present application;
fig. 3 is a schematic diagram of a first trace and a second trace of an embodiment of the present application;
fig. 4 is a schematic diagram of a first trace and a second trace of another embodiment of the present application;
FIG. 5 is a schematic view of a conductive structure of an embodiment of the present application;
FIG. 6 is a schematic view of another conductive structure of an embodiment of the present application;
fig. 7 is a schematic view of an array substrate according to an embodiment of the present application.
Wherein, 1, a display panel; 10. a first substrate; 11. an array substrate; 12. a first metal layer; 13. a first insulating layer; 14. a second metal layer; 15. a second insulating layer; 16. a transparent conductive layer; 20. a second substrate; 21. a color film substrate; 22. a common electrode layer; 30. a source electrode flip chip film; 40. a gate chip on film; 50. a printed circuit board; 100. routing; 110. a first wire; 120. a second routing; 122. a first route segment; 122a, a first overlapping portion; 123. a second route segment; 123a, a second overlapping portion; 124. a third route segment; 130. a conductive structure; 131. a conductive gold ball; 131a, a first conductive gold ball; 131b, second conductive gold balls; 132. a spacing unit; 132a, a first spacing unit; 132b, a second spacing unit; 133. and a conductive layer.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
As shown in fig. 1 and fig. 2, which are schematic diagrams of an exemplary display panel and a trace in a display device according to the present application, the display panel includes: the flip chip package structure comprises a first substrate 10, a second substrate 20, a source electrode flip chip 30, a grid electrode flip chip 40 and a wire 100, wherein the second substrate 20 is arranged opposite to the first substrate 10; the source electrode flip-chip film 30 is bound on one side of the first substrate 10; the gate flip-chip film 40 is bound on the other side of the first substrate 10; the wire 100 connects the source chip on film 30 and the gate chip on film 40; the traces 100 include a first trace 110 and a second trace 120 disposed side by side on the first substrate 10.
The inventor has found that, when the first trace 110 and the second trace 120 are disposed side by side and have a large coupling phenomenon, taking the first trace 110 and the second trace 120 as a power signal line and a control signal line, respectively, as an example, when a power signal in the power signal line suddenly changes (e.g., is powered on), a control signal in the control signal line is coupled to form a pulse burst, so as to generate an erroneous control signal, which affects the gate flip-chip film 40 and causes an abnormal picture. The coupling degree is positively correlated with the coupling capacitance, namely the coupling degree is higher when the coupling capacitance is larger; the coupling capacitance between the two lines is inversely related to the distance between the two lines, and the smaller the distance is, the larger the coupling capacitance is, so that the higher the coupling degree is, the larger the mutual influence of the two types of signals is.
Thus, the inventor of the application improves the method, and the improvement is as follows:
as shown in fig. 3, a display device of the present application is disclosed, which includes a display panel and a driving circuit that drives the display panel, the display panel including: the display panel includes: the flip chip package comprises a first substrate 10, a second substrate 20, a source electrode flip chip 30, a grid electrode flip chip 40, a printed circuit board 50 and a wire 100, wherein the second substrate 20 is arranged opposite to the first substrate 10; the source electrode flip-chip film 30 is bound on one side of the first substrate 10; the gate flip-chip film 40 is bound on the other side of the first substrate 10; the traces 100 include a first trace 110 and a second trace 120, and the first trace 110 and the second trace 120 are used for communicating the printed circuit board 50 and the gate flip-chip film 40; the first trace 110 is disposed on the source electrode flip-chip film 30 and the first substrate 10; the second traces 120 are disposed on the source electrode flip-chip film 30, the first substrate 10 and the second substrate 20; the second trace 120 is conducted between the first substrate 10 and the second substrate 20 through a conductive structure 130.
According to the display panel, the first wire 110 is arranged on the first substrate 10, the second wire 120 is arranged on the second substrate 20, the box thickness with a certain thickness is formed between the first substrate 10 and the second substrate 20, and therefore the first substrate 10 and the second substrate 20 have a certain distance, and correspondingly, the distance between the first wire 110 and the second wire 120 is increased, the coupling capacitance between the first wire 110 and the second wire 120 is reduced, the mutual interference between the two wires 100 is avoided, and the display effect of the display panel is improved.
It should be noted that in this embodiment, the second traces 120 are control signal lines, the first traces 110 are power signal lines, the corresponding first substrate 10 is the array substrate 11, and the second substrate 20 is the color filter substrate 21, and the power signal lines are disposed on the array substrate 11 by disposing the control signal lines on the color filter substrate 21. In this way, firstly, the number of the traces 100 on the color film substrate 21 is small, so that the influence on the control signal line can be reduced; secondly, the distance between the control signal line and the power signal line is enlarged, the mutual interference degree is low, and the parasitic capacitance is reduced or prevented, namely the coupling phenomenon is reduced or prevented.
Fig. 4 is a schematic view of a first trace 110 and a second trace 120 according to the present application, where the second trace 120 includes a first trace segment 122, a second trace segment 123 and a third trace segment 124 that are sequentially connected, the first trace segment 122 is disposed on the first substrate 10 near the source chip on film 30, the second trace segment 123 is disposed on the second substrate 20, and the third trace segment 124 is disposed on the first substrate 10 near the gate chip on film 40; the first wire segment 122 and the second wire segment 123, and the second wire segment 123 and the third wire segment 124 are respectively connected through a conductive structure 130. By arranging the longest second trace segment 123 of the trace segments 100 on the color film substrate 21, the length of the adjacent arrangement between the first trace 110 and the second trace 120 can be greatly reduced, the distance between the first trace 110 and the second trace 120 is increased, and then the coupling capacitance between the first trace 110 and the second trace 120 is reduced.
In this embodiment, the first substrate 10 is an array substrate 11, the second substrate 20 is a color film substrate 21, the array substrate 11 is provided with a bonding area of a source electrode flip-chip film 30 and a gate electrode flip-chip film 40, the printed circuit board 50 is connected to the array substrate 11 through the source electrode flip-chip film 30 and provides a control signal and a power signal to the gate electrode flip-chip film 40 through the first wire 110 and the second wire 120, and the first wire 110 and the second wire 120 can be respectively arranged at two ends of the source electrode flip-chip film 30 at the source electrode flip-chip film 30, so that although the first wire 110 and the second wire 120 are arranged on the same layer, the space is enough to reduce the coupling capacitance between the first wire 110 and the second wire 120; the longest second trace segment 123 of the first trace 110 is disposed on the second substrate 20, so as to further reduce the coupling capacitance between the first trace 110 and the second trace 120. It should be noted that the first trace 110 and the second trace 120 may be directly connected to the source chip on the source chip-on-film 30, and the power is supplied to the gate chip through the source chip, or may be connected to the printed circuit board through the source chip-on-film 30, and directly supplied to the printed circuit board.
Fig. 5 shows a schematic diagram of a conductive structure 130 according to the present application, in which the first substrate 10 is an array substrate 11, the second substrate 20 is a color filter substrate 21, a color filter and a common electrode layer 22 are disposed on the color filter substrate 21, and the second routing segment 123 and the common electrode layer 22 are formed through the same process and are insulated from each other. In the present application, the second wire segment 123 and the common electrode are both made of Indium Tin Oxide (ITO), and for a display panel without the common electrode layer 22 on the color filter substrate 21, the second wire segment 123 may also be made of ITO, and is correspondingly exposed on the color filter substrate 21 and directly contacted with the conductive structure 130, and of course, the second wire segment 123 of a metal process may also be formed on the color filter substrate 21, and the area occupied by the general second wire segment 123 is relatively small compared with the whole display panel, so that the metal process is also available, and the influence on the whole structure on the color filter substrate 21 is very small.
Specifically, the second routing segment 123 is disposed in the non-display region of the color filter substrate 21, and generally, the non-display region of the color filter substrate 21 is correspondingly disposed with a black matrix, and the second routing segment 123 is correspondingly disposed on the black matrix and is in contact with the conductive structure 130, so as to shield the third routing 100.
As shown in fig. 5, the first line segment 122 overlaps the vertically projected part of the second line segment 123 to form a first overlapping part 122a, and the second line segment 123 overlaps the vertically projected part of the third line segment 124 to form a second overlapping part 123 a; the conductive structure 130 includes a first conductive gold ball 131a and a second conductive gold ball 131b, the first overlapping portion 122a is provided with the first conductive gold ball 131a to communicate the first wire segment 122 with the second wire segment 123, and the second overlapping portion 123a is also provided with the second conductive gold ball 131b to communicate the second wire segment 123 with the third wire segment 124.
In the present application, the conductive gold balls 131 are used to connect the first wire segment 122 on the first substrate 10 with the second wire segment 123 on the second substrate 20, so as to ensure the connection between the first wire segment 122 and the second wire segment 123, and thus the problems of poor contact and the like are not generated.
Specifically, the line widths of the first routing segment 122 and the second routing segment 123 at the first overlapping portion 122a may be set to be wider than those of the routing lines at other positions, and the first routing segment 122 and the second routing segment 123 may be fully contacted with the conductive structure 130, so as to avoid the occurrence of poor conduction, and of course, the second routing segment 123 and the third routing segment 124 at the second overlapping portion 123a may also be set to be wider than those of the routing lines at other positions.
As shown in fig. 6, unlike the previous embodiment, the first line segment 122 overlaps the perpendicular projection of the second line segment 123 to form a first overlapping portion 122a, and the second line segment 123 overlaps the perpendicular projection of the third line segment 124 to form a second overlapping portion 123 a; the conductive structure 130 includes a first spacing unit 132a and a second spacing unit 132b, the surfaces of the first spacing unit 132a and the second spacing unit 132b are respectively provided with a conductive layer 133, the first overlapping portion 122a is provided with the first spacing unit 132a to communicate the first routing segment 122 with the second routing segment 123, and the second overlapping portion 123a is provided with the second spacing unit 132b to communicate the second routing segment 123 with the third routing segment 124.
In the present application, the spacing unit 132 is provided, the conductive layer 133 is provided on the spacing unit 132 to connect the first routing segment 122 on the first substrate 10 and the second routing segment 123 on the second substrate 20, and the spacing unit has a function of supporting the first substrate 10 and the second substrate 20 to ensure the box thickness; moreover, the spacing unit 132 is required to be disposed, and the spacing unit 132 is used to communicate the first wire segment 122 and the second wire segment 123, so that no additional process is required.
Of course, the two embodiments of the conductive structure 130 may be combined as appropriate, that is, the first overlapping portion 122a is formed by overlapping the vertical projection of the first line segment 122 and the second line segment 123, and the second overlapping portion 123a is formed by overlapping the vertical projection of the second line segment 123 and the third line segment 124; the conductive structure 130 comprises a spacing unit 132 and a conductive gold ball 131, wherein a conductive layer 133 is arranged on the surface of the spacing unit 132; the first overlapping portion 122a is provided with the conductive gold ball 131 to communicate the first routing segment 122 with the second routing segment 123, and the second overlapping portion 123a is also provided with the spacing unit 132 to communicate the second routing segment 123 with the third routing segment 124; alternatively, the first overlapping portion 122a is provided with the spacing unit 132 to communicate the first routing segment 122 with the second routing segment 123, and the second overlapping portion 123a is provided with the conductive gold ball 131 to communicate the second routing segment 123 with the third routing segment 124, so that the structure is flexible and changeable.
As shown in fig. 7, in an embodiment, a first metal layer 12, a first insulating layer 13 and a transparent conductive layer 16 are sequentially stacked on the first substrate 10; the first wire segment 122 and the third wire segment 124 may be disposed on the first metal layer 12 or the second metal layer 14, or may be disposed on the transparent conductive layer 16, wherein the transparent conductive layer 16 is made of ITO; in contrast, taking the first wire segment 122 as an example, when the first wire segment 122 is made of the first metal layer 12, the first wire segment 122 needs to be connected to the conductive structure 130 correspondingly, and thus the first wire segment 122 needs to be connected to the conductive structure 130 through the transparent conductive layer 16, that is, the first wire segment 122 disposed on the first metal layer is connected to the transparent conductive layer 16 through a via, and is connected to the conductive structure 130 through the transparent conductive layer 16. The first wire segment 122 has relatively lower impedance and smaller signal loss by using a metal layer process, and when the first wire segment 122 is selected to use an ITO process, a via hole is not required to be formed, and the first wire segment can be directly connected with the conductive structure 130 in a contact manner, so that an additional via hole process is not required, the process change on the array substrate 11 is small, and the cost is not additionally increased.
With reference to fig. 2, 5 and 6; as another embodiment of the present application, the present application further discloses a display panel divided into a display area and a non-display area, the display panel including: the flip chip package comprises a first substrate 10, a second substrate 20, a source electrode flip chip 30, a grid electrode flip chip 40, a printed circuit board 50 and a wire 100, wherein the second substrate 20 is arranged opposite to the first substrate 10; the source electrode flip-chip film 30 is bound on one side of the first substrate 10; the gate flip-chip film 40 is bound on the other side of the first substrate 10; the trace 100 is disposed in the non-display region, and the printed circuit board 50 outputs a power signal and a control signal to the gate flip-chip film 40 through the trace 100; the traces 100 include a first trace 110 and a second trace 120, and the first trace 110 transmits a control signal to the gate flip-chip film 40; the second trace 120 transmits a power signal to the gate flip-chip film 40; the first wires 110 are sequentially disposed on the source electrode flip-chip film 30 and the first substrate 10; the second trace 120 includes a first trace segment 122, a second trace segment 123 and a third trace segment 124 that are sequentially connected, the first trace segment 122 is disposed at a position of the first substrate 10 close to the source chip on film 30, the second trace segment 123 is disposed on the second substrate 20, and the third trace segment 124 is disposed at a position of the first substrate 10 close to the gate chip on film 40;
the first substrate 10 is an array substrate 11, the second substrate 20 is a color film substrate 21, a color filter and a common electrode layer 22 are arranged on the color film substrate 21, and the second routing segment 123 and the common electrode layer 22 are formed through the same process and are insulated from each other; the vertical projection parts of the first line segment 122 and the second line segment 123 are overlapped to form a first overlapping part 122a, and the vertical projection parts of the second line segment 123 and the third line segment 124 are overlapped to form a second overlapping part 123 a; the conductive structure 130 includes a conductive gold ball 131, the first overlapping portion 122a is provided with the conductive gold ball 131 to communicate the first routing segment 122 with the second routing segment 123, and the second overlapping portion 123a is also provided with the conductive gold ball 131 to communicate the second routing segment 123 with the third routing segment 124; the second trace 120 is a control signal line for transmitting a control signal, and the first trace 110 is a power signal line for transmitting a power signal.
In the present application, the second trace 120 may also be a power signal line, the first trace 110 may be a control signal line, the control signal line is disposed on the array substrate 11, and the power signal line is disposed on the color film substrate 21; similarly, the coupling phenomenon is mainly caused by powering on and powering off a power signal in the power signal line, so that the power signal line is arranged on the color film substrate 21 with less traces 100, and the interference of the power signal line on other traces 100 is minimized as much as possible; the two different embodiments can be selected according to actual needs.
The technical solution of the present application can be widely applied to various display panels, such as a COA display panel, a TN (Twisted Nematic) display panel, an IPS (In-Plane Switching) display panel, a VA (Vertical Alignment) display panel, and an MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as an OLED (Organic Light-Emitting Diode) display panel, can also be applied to the above solutions.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A display panel, comprising:
a first substrate;
a second substrate disposed opposite to the first substrate;
the source electrode chip on film is bound on one side of the first substrate;
the grid chip on film is bound on the other side of the first substrate;
a printed circuit board connected to one side of the first substrate through the source chip on film,
the wires comprise a first wire and a second wire, and the first wire and the second wire are used for electrically communicating the printed circuit board and the grid chip on film; the first routing is arranged on the first substrate; the second routing is arranged on the first substrate and the second substrate; and
and the conductive structure conducts the part of the second routing wire, which is positioned on the first substrate, with the part of the second routing wire, which is positioned on the second substrate.
2. The display panel according to claim 1, wherein the second traces include a first trace segment, a second trace segment and a third trace segment that are sequentially connected, the first trace segment is disposed on the first substrate at a position close to the source COF, the second trace segment is disposed on the second substrate, and the third trace segment is disposed on the first substrate at a position close to the gate COF;
the first routing section is communicated with the second routing section through the conductive structure, and the second routing section is communicated with the third routing section through the conductive structure.
3. The display panel according to claim 2, wherein the first substrate is an array substrate, the second substrate is a color filter substrate, a common electrode layer is disposed on the color filter substrate, and the second routing segment and the common electrode layer are formed by the same process and are insulated from each other.
4. The display panel according to claim 3, wherein the second trace segment is disposed in the non-display region of the color filter substrate.
5. A display panel as claimed in claim 2, characterized in that the first track segment coincides with a perpendicular projection of a second track segment forming a first overlap, and the second track segment coincides with a perpendicular projection of a third track segment forming a second overlap;
the conductive structure comprises a first conductive gold ball and a second conductive gold ball, the first overlapping portion is provided with the first conductive gold ball to communicate the first route segment with the second route segment, and the second overlapping portion is provided with the second conductive gold ball to communicate the second route segment with the third route segment.
6. A display panel as claimed in claim 2, characterized in that the first track segment coincides with a perpendicular projection of a second track segment which coincides partly with a perpendicular projection of a third track segment to form a first overlap;
the conductive structure comprises a first spacing unit and a second spacing unit, and conductive layers are respectively arranged on the surfaces of the first spacing unit and the second spacing unit;
the first overlapping portion is provided with the first spacing unit to communicate the first route segment with the second route segment, and the second overlapping portion is also provided with the second spacing unit to communicate the second route segment with the third route segment.
7. A display panel as claimed in claim 2, characterized in that the first track segment coincides with a perpendicular projection of a second track segment which coincides partly with a perpendicular projection of a third track segment to form a first overlap;
the conductive structure comprises a spacing unit and a conductive gold ball, and a conductive layer is arranged on the surface of the spacing unit;
the first overlapping portion is provided with the conductive gold ball to communicate the first route segment with the second route segment, and the second overlapping portion is provided with the spacing unit to communicate the second route segment with the third route segment.
8. The display panel according to claim 1, wherein the first substrate is an array substrate, the second substrate is a color film substrate, and the first traces are control signal lines for transmitting control signals; the second routing wire is a power signal wire and used for transmitting a power signal.
9. A display panel divided into a display area and a non-display area, the display panel comprising:
a first substrate;
a second substrate disposed opposite to the first substrate;
the source electrode chip on film is bound on one side of the first substrate;
the grid chip on film is bound on the other side of the first substrate;
a wiring disposed in the non-display region, an
The printed circuit board outputs a power supply signal and a control signal to the grid flip chip film through the wiring;
the wires comprise a first wire and a second wire, and the first wire transmits a control signal to the grid flip chip film; the second wire transmits a power signal to the grid flip chip film;
the first wires are sequentially arranged on the source electrode chip on film and the first substrate;
the second routing comprises a first routing section, a second routing section and a third routing section which are sequentially communicated, the first routing section is arranged at the position, close to the source electrode chip on film, of the first substrate, the second routing section is arranged on the second substrate, and the third routing section is arranged at the position, close to the gate electrode chip on film, of the first substrate;
the first substrate is an array substrate, the second substrate is a color film substrate, a color filter and a common electrode layer are arranged on the color film substrate, and the second route section and the common electrode layer are formed through the same process and are mutually insulated;
the vertical projection parts of the first running line segment and the second running line segment are overlapped to form a first overlapping part, and the vertical projection parts of the second running line segment and the third running line segment are overlapped to form a second overlapping part;
the conductive structure comprises a conductive gold ball, the conductive gold ball is arranged on the first overlapping part to communicate the first route segment with the second route segment, and the conductive gold ball is also arranged on the second overlapping part to communicate the second route segment with the third route segment;
the second wiring is a control signal line and is used for transmitting control signals, and the first wiring is a power signal line and is used for transmitting power signals.
10. A display device comprising the display panel according to any one of claims 1 to 9 and a driving circuit for driving the display panel.
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| CN202011397686.4A CN112684642A (en) | 2020-12-04 | 2020-12-04 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011397686.4A CN112684642A (en) | 2020-12-04 | 2020-12-04 | Display panel and display device |
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| CN106932979A (en) * | 2015-12-31 | 2017-07-07 | 乐金显示有限公司 | Array base palte and the display device including it |
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Application publication date: 20210420 |