CN112671575A

CN112671575A - Working link switching method and device, storage medium and electronic device

Info

Publication number: CN112671575A
Application number: CN202011522185.4A
Authority: CN
Inventors: 王全刚; 周杰; 何志川
Original assignee: Centec Networks Suzhou Co Ltd
Current assignee: Centec Networks Suzhou Co Ltd
Priority date: 2020-12-21
Filing date: 2020-12-21
Publication date: 2021-04-16
Anticipated expiration: 2040-12-21
Also published as: CN112671575B

Abstract

The embodiment of the invention provides a method and a device for switching a working link, wherein the method comprises the following steps: under the condition that the first chip of the first device does not receive the BAS message within the preset time or the message received by the first chip is wrong, the embedded CPU of the second device receives the notification information of the first chip, and responds to the notification information to input the link state change information into the automatic protection switching APS state machine corresponding to the embedded CPU; the embedded CPU receives a target APS message sent by the first chip and sends the target APS message to the APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS message, and the problems that in the prior art, when the link fails, the external CPU is required to judge APS protection switching, the APS protection switching speed is probably influenced when the external CPU has multiple tasks, and the like are solved.

Description

Working link switching method and device, storage medium and electronic device

Technical Field

The present invention relates to the field of communications, and in particular, to a method and an apparatus for switching a working link, a storage medium, and an electronic apparatus.

Background

APS (Automatic Protection Switching) is a mechanism for automatically Switching to a backup link within 50 milliseconds when a main link is interrupted or a signal is degraded in order to ensure the reliability of a service.

In a FlexE (Flexible Ethernet) network, APS information is sent once per second during normal operation, when the operating state changes, three APS messages must be sent immediately at intervals of 16384 code blocks, a receiving end triggers corresponding protection switching operation according to the APS information, a chip reports to an external CPU after detecting a link failure, the external CPU performs APS state machine operation, and when the CPU has a large number of tasks, the speed of APS protection switching may be affected due to untimely scheduling, thereby affecting the quality of service.

As shown in fig. 1, assuming that service data currently works in a working link, as shown in fig. 2, when SPN OAM of a working link at a device 1 side detects that a signal failure or a signal degradation occurs in the current link, a chip of the device 1 reports a current state to a CPU, and the CPU implements protection switching through an IO control chip according to an APS state machine; meanwhile, the device 1 will rapidly send three APS messages to the device 2 through the protection link at a time interval of 16384 code blocks, the device 2 reports the APS messages received by the chip of the device 2 to the CPU, and the CPU triggers a corresponding protection switching operation through the IO control chip according to the APS state machine.

In the related art, an effective technical scheme is not provided for solving the problems that APS protection switching must be judged by an external CPU when a link fails, and the speed of APS protection switching is likely to be influenced when the external CPU has multiple tasks.

Disclosure of Invention

The embodiment of the invention provides a method and a device for switching a working link, a storage medium and an electronic device, which are used for at least solving the problems that in the related art, when a link fails, an external CPU is required to judge APS protection switching, and the speed of APS protection switching is possibly influenced when the external CPU has multiple tasks.

According to an embodiment of the present invention, there is provided a method for switching an active link, including: when a first chip of a first device does not receive a BAS message within a preset time or a message received by the first chip is incorrect, an embedded CPU of a second device receives notification information of the first chip, and responds to the notification information to input link state change information into an automatic protection switching APS state machine corresponding to the embedded CPU, wherein the notification information is used for indicating the following contents of the embedded CPU: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment; and the embedded CPU receives a target APS message sent by the first chip and sends the target APS message to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS message.

In an exemplary embodiment, after the embedded CPU receives a target APS packet sent by the first chip and sends the target APS packet to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS packet, the method further includes: and under the condition that the APS state machine determines to switch the working link according to the link state change information and the target APS message and determines the target state after the working link is switched, the embedded CPU synchronizes the target state stored in the embedded CPU to an external CPU in a memory sharing mode.

In an exemplary embodiment, the receiving, by the embedded CPU, the target APS packet sent by the first chip includes: and the embedded CPU receives target APS messages of target quantity sent by the first chip through a protection link according to a preset time interval, wherein the target APS messages are used for triggering the switching of the working link.

In an exemplary embodiment, after the embedded CPU receives a target APS packet sent by the first chip and sends the target APS packet to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS packet, the method further includes: and under the condition that an APS state machine determines to switch the working link according to the link state change information and the target APS message and determines the switching operation required by the switching of the working link, the embedded CPU writes the switching operation stored in the embedded CPU into a chip table entry address in a memory sharing mode so as to realize the switching of the working link.

In an exemplary embodiment, the embedded CPU of the second device receives the notification information of the first chip, and includes: and the embedded CPU of the second device receives the notification information which is simultaneously sent to the external CPU by the first chip.

In an exemplary embodiment, it is determined that a message received by a first chip of a first device is erroneous by: and under the condition that the first chip receives an Operation Administration and Maintenance (OAM) message of a Sliced Packet Network (SPN), determining that the message received by the first chip is wrong.

According to another embodiment of the present invention, there is also provided a device for switching an operating link, which is applied to an embedded CPU of a second device, and includes: a first processing module, configured to receive notification information of a first chip when a first chip of a first device does not receive a BAS packet within a preset time or the first chip receives a packet incorrectly, and respond to the notification information to input link state change information into an automatic protection switching APS state machine corresponding to an embedded CPU, where the notification information is used to indicate the following content of the embedded CPU: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment; and the second processing module is configured to receive the target APS packet sent by the first chip, and send the target APS packet to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS packet.

In one exemplary embodiment, the apparatus further comprises: and the synchronization module is used for synchronizing the target state stored in the embedded CPU to an external CPU in a memory sharing mode under the condition that an APS state machine determines to switch the working link according to the link state change information and the target APS message and determines the target state after the working link is switched.

According to a further embodiment of the present invention, there is also provided a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.

According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

By the invention, under the condition that a first chip of a first device does not receive a BAS message within a preset time or a message received by the first chip is wrong, an embedded CPU of a second device receives notification information of the first chip and responds to the notification information to input link state change information into an Automatic Protection Switching (APS) state machine corresponding to the embedded CPU, wherein the notification information is used for indicating the embedded CPU to have the following contents: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment; the embedded CPU receives a target APS message sent by the first chip and sends the target APS message to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS message, that is, the embedded CPU of each device and the APS state machine performs BAS message monitoring, notification information receiving, link state change information receiving, APS message receiving and other operations between the devices, thereby realizing APS data stream switching.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

FIG. 1 is a diagram illustrating a prior art service data located in a working link;

fig. 2 is a schematic diagram of a prior art service data located in a protection link;

fig. 3 is a block diagram of a hardware configuration of a computer terminal of a method for switching an operating link according to an embodiment of the present invention;

fig. 4 is a flowchart of a handover method of an active link according to an embodiment of the present invention;

fig. 5 is a flow chart of a handover method of an active link according to an embodiment of the present invention;

fig. 6 is a flow chart of a method for switching an active link according to an embodiment of the present invention (ii);

fig. 7 is an information transmission diagram of a handover method of an active link according to an embodiment of the present invention;

fig. 8 is a block diagram of an automatic protection switching system of a network according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram (one) of a switching device of an operating link according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram (two) of a switching apparatus of an operating link according to an embodiment of the present invention.

Detailed Description

The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

The method provided by the embodiment of the application can be executed in a computer terminal or a similar operation device. Taking the example of the operation on the computer terminal, fig. 3 is a hardware structure block diagram of the computer terminal of the method for switching the working link according to the embodiment of the present invention. As shown in fig. 3, the computer terminal may include one or more (only one shown in fig. 3) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, and in an exemplary embodiment, may further include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 3 is only an illustration and is not intended to limit the structure of the computer terminal. For example, the computer terminal may also include more or fewer components than shown in FIG. 3, or have a different configuration with equivalent functionality to that shown in FIG. 3 or more functionality than that shown in FIG. 3.

The memory 104 may be used to store a computer program, for example, a software program of an application software and a module, such as a computer program corresponding to the method for switching the working link in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, so as to implement the method described above. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to a computer terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal. In one example, the transmission device 106 includes a Network adapter (NIC), which can be connected to other Network devices through a base station so as to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.

In this embodiment, a method for switching an operating link is provided, which is applied to the computer terminal, and fig. 4 is a flowchart of a method for switching an operating link according to an embodiment of the present invention, where the flowchart includes the following steps:

step S202, when the first chip of the first device does not receive the BAS packet within a preset time or the packet received by the first chip is incorrect, the embedded CPU of the second device receives notification information of the first chip, and responds to the notification information to input link state change information into an automatic protection switching APS state machine corresponding to the embedded CPU, where the notification information is used to indicate the embedded CPU to: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment;

step S204, the embedded CPU receives the target APS message sent by the first chip and sends the target APS message to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS message.

Through the above steps, when the first chip of the first device does not receive the BAS packet within the preset time, or the packet received by the first chip is incorrect, the embedded CPU of the second device receives the notification information of the first chip, and responds to the notification information to input the link state change information into the automatic protection switching APS state machine corresponding to the embedded CPU, where the notification information is used to indicate the embedded CPU to: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment; the embedded CPU receives a target APS message sent by the first chip and sends the target APS message to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS message, the problems that in the prior art, when a link fails, the APS protection switching must be judged by an external CPU, the APS protection switching speed is likely to be influenced when the external CPU has multiple tasks, and the like are solved, the embedded CPU and an external main CPU work cooperatively, the characteristic of good real-time performance of the embedded CPU is exerted, the rapid switching of a data link in a Flexe network is realized, and the stability and the reliability of services are favorably improved.

The embedded CPU and the external CPU are relative to the chip, the embedded CPU may be understood as a CPU disposed inside the chip, and the external CPU may be understood as an additional CPU outside the chip. The BAS message is a basic code block of the SPN OAM, and is used for performing a basic OAM message transmitted in real time, including connectivity check, BIP check, RDI, REI, CS _ LF, and CS _ RF functions.

Fig. 5 is a flowchart illustrating a method for switching an active link according to an embodiment of the present invention (i), as shown in fig. 5, after step S204, the method further includes:

step S206, under the condition that the APS state machine determines to switch the working link according to the link state change information and the target APS message, and the APS state machine determines the target state after the working link is switched, the embedded CPU synchronizes the target state stored in the embedded CPU to an external CPU in a memory sharing mode.

In short, the APS state machine determines to switch the working link, and after the APS state machine determines the target state after the working link is switched, the embedded CPU synchronizes the target state to the external CPU in a memory sharing manner.

And the target state stored in the embedded CPU is sent to the embedded CPU by an APS state machine.

In the step S204, the embedded CPU may receive the target APS packets sent by the first chip through the protection link in multiple ways, and in an optional embodiment, the embedded CPU receives the target APS packets of the target amount sent by the first chip through the protection link according to a preset time interval, where the target APS packets are used to trigger the switching of the working link.

That is, the first chip sends target APS messages for triggering link switching in a target amount to the embedded CPU through the protection link at a predetermined time interval.

Fig. 6 is a flowchart illustrating a method for switching an active link according to an embodiment of the present invention (ii), as shown in fig. 6, after step S204, the method further includes:

step S402, under the condition that the APS state machine determines to switch the working link according to the link state change information and the target APS message, and the APS state machine determines the switching operation required by the switching of the working link, the embedded CPU writes the switching operation stored in the embedded CPU into the address of the chip table entry in a memory sharing mode, so as to realize the switching of the working link.

In short, the APS state machine determines to switch the working link, and after the APS state machine determines the target state after the working link is switched, the embedded CPU writes the target state into the chip table entry address in a memory sharing manner.

In an optional embodiment, the receiving, by the embedded CPU of the second device, the notification information of the first chip includes: and the embedded CPU of the second device receives the notification information which is simultaneously sent to the external CPU by the first chip.

In an alternative embodiment, it is determined that the message received by the first chip of the first device is incorrect by: and determining that the message received by the first chip is wrong when the first chip receives an operation, Administration, and Maintenance (OAM) message for SPN operation, Administration, and Maintenance.

Namely, the first chip determines the message error through the operation, administration and maintenance OAM message of the SPN.

Fig. 7 is a schematic information transmission diagram of a method for switching an active link according to an embodiment of the present invention, as shown in fig. 7, including the following steps:

step S1, the Switch Core generates APS message;

step S2, the Switch Core sends the APS message to the DMA (Direct Memory Access) of the embedded CPU;

step S3, the DMA sends the analytic data to the APS state machine;

step S4, the APS state machine sends data to the external CPU through the shared memory of the external CPU;

step S5, OAM sends data to APS state machine through external CPU shared memory;

step S6, the APS state machine sends data to the shared memory;

step S7, the shared memory delivers the data sent by the APS state machine to the Switch Core;

step S8, the Switch Core generates OAM Defect information;

step S9, sending the OAM Defect information to a DMA of an external CPU;

step S10, convergence is a signal failure or signal degradation and is sent to the APS state machine;

and step S11, the DMA of the external CPU sends the information to OAM to complete information reporting.

It should be noted that the execution order of the above steps may be exchanged or cyclically executed in some cases.

Through the steps, the following technical effects can be achieved: when the chip receives SPN OAM error message or detection time is overtime (the chip can not receive BAS message), the chip directly accesses the DMA memory to send two identical messages (informing OAM error message or detection time is overtime) to the external CPU and the embedded CPU, the external CPU informs users according to the DMA message, the embedded CPU converges various error messages into Signal Failure (SF) and Signal Degradation (SD), and the Signal Failure (SF) and the Signal Degradation (SD) are used as input sources to enter an APS state machine. And the local terminal sends information to the chip of the opposite terminal. The APS message received by the chip is sent to the embedded CPU through the DMA, and the APS message is analyzed and then enters the APS state machine as an input source. And calculating the switching action in a state machine maintained by the embedded CPU according to the input state, and quickly writing the result into the address of the chip table entry through the shared memory to realize the quick switching of the Flexe data stream. When the embedded CPU performs link switching operation on the chip, the embedded CPU reports a switching event through interruption, and synchronizes the state of an APS group in the embedded CPU to an external CPU through a shared memory, so that the switching event is visible to a user. The embedded CPU and the external main CPU work cooperatively, so that the characteristic of good real-time performance of the embedded CPU is exerted, the rapid switching of a data link in a Flexe network is realized, and the stability and the reliability of services are improved.

It should be noted that the execution order of the above steps may be exchanged or cyclically executed in some cases, which is not limited in the embodiment of the present invention.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

In this embodiment, a device for switching a working link is further provided, which is applied to an embedded CPU of a second device, and is used to implement the foregoing embodiments and preferred embodiments, and details are not described again after the description. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 8 is a block diagram of an automatic protection switching system of a network according to an embodiment of the present invention, as shown in fig. 8, including:

a first processing module 62, configured to receive notification information of a first chip when the first chip of a first device does not receive a BAS packet within a preset time or the first chip receives a packet incorrectly, and respond to the notification information to input link state change information into an automatic protection switching APS state machine corresponding to the embedded CPU, where the notification information is used to indicate the following content of the embedded CPU: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment;

a second processing module 64, configured to receive the target APS packet sent by the first chip, and send the target APS packet to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS packet.

Through the system, when a first chip of a first device does not receive a BAS message within a preset time or a message received by the first chip is incorrect, an embedded CPU of a second device receives notification information of the first chip, responds to the notification information and inputs link state change information into an Automatic Protection Switching (APS) state machine corresponding to the embedded CPU, wherein the notification information is used for indicating the embedded CPU to have the following contents: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment; the embedded CPU receives a target APS message sent by the first chip and sends the target APS message to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS message, and the problems of low APS data stream switching speed, complex logic of the APS state machine and excessive consumption of table resources in the prior art are solved.

Fig. 9 is a schematic structural diagram (a) of a device for switching an operating link according to an embodiment of the present invention, as shown in fig. 9, the device further includes:

and a synchronizing module 72, configured to synchronize, by means of a shared memory, the target state stored in the embedded CPU to an external CPU when an APS state machine determines to switch the working link according to the link state change information and the target APS packet, and determines the target state after the working link is switched.

In an optional embodiment, the second processing module 64 is further configured to receive the target APS packet sent by the first chip, and includes: and the embedded CPU receives target APS messages of target quantity sent by the first chip through a protection link according to a preset time interval, wherein the target APS messages are used for triggering the switching of the working link.

Fig. 10 is a schematic structural diagram (ii) of a device for switching an operating link according to an embodiment of the present invention, and as shown in fig. 10, the device further includes:

a write-in module 82, configured to write the switching operation stored in the embedded CPU into a chip table entry address in a manner of sharing a memory, so as to implement switching of the working link.

In an optional embodiment, the second processor 64 is further configured to receive the notification information sent by the first chip to an external CPU.

In an optional embodiment, the first processor 62 is further configured to determine that the message received by the first chip is an error when the message is a message for operation, administration and maintenance, OAM, of a packet slicing network SPN.

It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.

Embodiments of the present invention also provide a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the above method embodiments when executed.

In an exemplary embodiment, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:

s1, when the first chip of the first device does not receive the BAS packet within a preset time or the packet received by the first chip is incorrect, the embedded CPU of the second device receives notification information of the first chip, and responds to the notification information to input link state change information into an automatic protection switching APS state machine corresponding to the embedded CPU, where the notification information is used to indicate the embedded CPU: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment;

and S2, the embedded CPU receives the target APS message sent by the first chip and sends the target APS message to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS message.

In an exemplary embodiment, in the present embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

In an exemplary embodiment, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

In an exemplary embodiment, in the present embodiment, the processor may be configured to execute the following steps by a computer program:

In an exemplary embodiment, for specific examples in this embodiment, reference may be made to the examples described in the above embodiments and optional implementation manners, and details of this embodiment are not described herein again.

It will be apparent to those skilled in the art that the various modules or steps of the invention described above may be implemented using a general purpose computing device, which may be centralized on a single computing device or distributed across a network of computing devices, and in one exemplary embodiment may be implemented using program code executable by a computing device, such that the steps shown and described may be executed by a computing device stored in a memory device and, in some cases, executed in a sequence different from that shown and described herein, or separately fabricated into individual integrated circuit modules, or multiple ones of them fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for switching an active link, comprising:

when a first chip of a first device does not receive a BAS message within a preset time or a message received by the first chip is incorrect, an embedded CPU of a second device receives notification information of the first chip, and responds to the notification information to input link state change information into an automatic protection switching APS state machine corresponding to the embedded CPU, wherein the notification information is used for indicating the following contents of the embedded CPU: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment;

and the embedded CPU receives a target APS message sent by the first chip and sends the target APS message to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS message.

2. The method according to claim 1, wherein the embedded CPU receives a target APS packet sent by the first chip and sends the target APS packet to an APS state machine, so that after the APS state machine determines to switch the working link according to the link state change information and the target APS packet, the method further comprises:

and under the condition that the APS state machine determines to switch the working link according to the link state change information and the target APS message and determines the target state after the working link is switched, the embedded CPU synchronizes the target state stored in the embedded CPU to an external CPU in a memory sharing mode.

3. The method according to claim 1, wherein the receiving, by the embedded CPU, the target APS packet sent by the first chip comprises:

and the embedded CPU receives target APS messages of target quantity sent by the first chip through a protection link according to a preset time interval, wherein the target APS messages are used for triggering the switching of the working link.

4. The method according to claim 1, wherein the embedded CPU receives a target APS packet sent by the first chip and sends the target APS packet to an APS state machine, so that after the APS state machine determines to switch the working link according to the link state change information and the target APS packet, the method further comprises:

and under the condition that an APS state machine determines to switch the working link according to the link state change information and the target APS message and determines the switching operation required by the switching of the working link, the embedded CPU writes the switching operation stored in the embedded CPU into a chip table entry address in a memory sharing mode so as to realize the switching of the working link.

5. The method of claim 1, wherein receiving the notification information of the first chip by an embedded CPU of a second device comprises:

and the embedded CPU of the second device receives the notification information which is simultaneously sent to the external CPU by the first chip.

6. The method according to any of claims 1 to 5, wherein it is determined that the message received by the first chip of the first device is erroneous by:

and under the condition that the first chip receives an Operation Administration and Maintenance (OAM) message of a Sliced Packet Network (SPN), determining that the message received by the first chip is wrong.

7. An apparatus for switching working links, wherein an embedded CPU applied to a second device comprises:

a first processing module, configured to receive notification information of a first chip when a first chip of a first device does not receive a BAS packet within a preset time or the first chip receives a packet incorrectly, and respond to the notification information to input link state change information into an automatic protection switching APS state machine corresponding to an embedded CPU, where the notification information is used to indicate the following content of the embedded CPU: the first chip does not receive the BAS message within a preset time, or the first chip receives the message incorrectly, and the link state change information is at least used for indicating signal failure or signal degradation of a working link between the first equipment and the second equipment;

and the second processing module is configured to receive the target APS packet sent by the first chip, and send the target APS packet to an APS state machine, so that the APS state machine determines to switch the working link according to the link state change information and the target APS packet.

8. The apparatus of claim 7, further comprising:

and the synchronization module is used for synchronizing the target state stored in the embedded CPU to an external CPU in a memory sharing mode under the condition that an APS state machine determines to switch the working link according to the link state change information and the target APS message and determines the target state after the working link is switched.

9. A computer-readable storage medium, in which a computer program is stored, wherein the computer program is arranged to carry out the method of any one of claims 1 to 6 when executed.

10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 6.