CN112671358A - Design method of comprehensive signal generation processing system - Google Patents
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Abstract
The invention belongs to the technical field of signal generation processing, and particularly relates to a design method of a comprehensive signal generation processing system, which comprises the following steps: step 1, selecting an FPGA to establish a fixed signal generating device, generating a required waveform signal through the FPGA, and continuously displaying the generated waveform signal on a liquid crystal display screen; step 2, selecting a small signal amplifier to establish a power amplification device, amplifying the generated waveform signal through the small signal amplifier to form an excitation source meeting the test requirement, loading excitation and testing; and 3, selecting a DSP to establish a signal detection processing device, and detecting and processing the test generated signal through the DSP to realize basic noise reduction and harmonic wave removal processing of the test generated signal. The invention provides the design method of the comprehensive signal generation processing system, which is convenient to carry, has higher accuracy and better processing performance.
Description
Technical Field
The invention belongs to the technical field of signal generation processing, and particularly relates to a design method of a comprehensive signal generation processing system.
Background
At present, waveform generators are widely used in various fields such as communication, control, measurement, etc., and waveforms such as sawtooth, sine, square, etc. are commonly used for designing and debugging circuits. With the rapid development of electronic technology, digitization is gradually becoming the development trend of the electronic industry, and companies expand their products in the directions of digitization, integration, miniaturization, and the like. It is known that digital electronic products have irreplaceable advantages, such as small size, high integration level, strong anti-interference capability, and the like. However, digital circuits can only handle pulse waveforms well, i.e. only square waves formed by l and 0 are handled well, and not well for continuously varying signals. For a common signal generating device, the digitized signal is often stored in a data file for further processing by an internal algorithm, which results in the signal generating device not being portable.
Disclosure of Invention
The invention mainly aims to solve the problems in the prior art and provides a design method of a comprehensive signal generation processing system, which is convenient to carry, high in accuracy and good in processing performance.
The technical problem solved by the invention is realized by adopting the following technical scheme: a design method of an integrated signal generation processing system comprises the following steps:
step 1, selecting an FPGA to establish a fixed signal generating device, generating a required waveform signal through the FPGA, and continuously displaying the generated waveform signal on a liquid crystal display screen;
step 2, selecting a small signal amplifier to establish a power amplification device, amplifying the generated waveform signal through the small signal amplifier to form an excitation source meeting the test requirement, loading excitation and testing;
and 3, selecting a DSP to establish a signal detection processing device, and detecting and processing the test generated signal through the DSP to realize basic noise reduction and harmonic wave removal processing of the test generated signal.
Further, the small signal amplifier employs a class D power amplifier.
Further, the step 1 of generating the required waveform signal through the FPGA further comprises,
and the FPGA adopts a programmable digital algorithm to process the waveform signals of the channels in real time so as to generate the required waveform signals.
Further, step 3, selecting a DSP to establish a signal detection processing device, and performing detection processing on the test generated signal through the DSP to realize basic noise reduction and harmonic elimination processing on the test generated signal,
and an FIR digital filter in the DSP filters the harmonic waves of the signals generated by the test.
Further, step 3, selecting a DSP to establish a signal detection processing device, and performing detection processing on the test generated signal through the DSP to realize basic noise reduction and harmonic elimination processing on the test generated signal,
and the DSP performs basic noise reduction processing on the experimentally generated signal by adopting a frequency spectrum subtraction algorithm.
Further, the protection control device promptly cuts off the output of the small-sized signal amplifier when the small-sized signal amplifier malfunctions or when the input waveform signal is erroneous.
Furthermore, the protection control device controls the relay switch through the single chip microcomputer to control the output on-off of the small signal amplifier.
The invention has the beneficial effects that:
the FPGA generates the required waveform signal, thereby improving the problem that the digital signal is often stored in a data file so as to facilitate the further processing of an internal algorithm in the prior art, and further causing the signal generating device to have no portability, and leading the system to be convenient to carry; the small signal amplifier is a D-type power amplifier, and under the condition of the same load and power supply voltage, the power of the D-type PA is almost improved by five times, so that the system has higher accuracy; the DSP can generate a finite-length unit impulse response (FIR) filter which has strict linear phase-frequency characteristics while ensuring any amplitude-frequency characteristics, and the unit sampling response of the DSP is finite-length, so the filter is a stable system and the processing performance of the system is better.
Drawings
FIG. 1 is a flow chart of a design method of an integrated signal generating and processing system according to the present invention.
Fig. 2 is a flowchart of the procedure of the fixed signal generating device of the present invention.
Fig. 3 is a block diagram of a hardware configuration of the stationary signal generating apparatus of the present invention.
Fig. 4 is a circuit diagram of a power amplifying device of the present invention.
Fig. 5 is a flowchart of the protection control device according to the present invention.
Fig. 6 is a flow chart of the programming of the FIR digital filter of the present invention.
Fig. 7 is a block diagram of a hardware configuration of the stationary signal generating apparatus of the present invention.
Fig. 8 is a block diagram of a hardware configuration of the signal detection processing apparatus according to the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As shown in fig. 1 to 8, the design method of an integrated signal generating and processing system provided by the present invention includes the following steps:
step 1, selecting an FPGA to establish a fixed signal generating device, generating a required waveform signal through the FPGA, and continuously displaying the generated waveform signal on a liquid crystal display screen;
step 2, selecting a small signal amplifier to establish a power amplification device, amplifying the generated waveform signal through the small signal amplifier to form an excitation source meeting the test requirement, loading excitation and testing;
and 3, selecting a DSP to establish a signal detection processing device, and detecting and processing the test generated signal through the DSP to realize basic noise reduction and harmonic wave removal processing of the test generated signal.
The small signal amplifier adopts a D-type power amplifier.
The step 1, generating the required waveform signal through the FPGA, further comprising,
and the FPGA adopts a programmable digital algorithm to process the waveform signals of the channels in real time so as to generate the required waveform signals.
and an FIR digital filter in the DSP filters the harmonic waves of the signals generated by the test.
and the DSP performs basic noise reduction processing on the experimentally generated signal by adopting a frequency spectrum subtraction algorithm.
When the small signal amplifier has a fault or the input waveform signal is incorrect, the protection control device quickly cuts off the output of the small signal amplifier.
The protection control device controls the relay switch through the single chip microcomputer to control the output on-off of the small signal amplifier.
Examples
Step 1, selecting an FPGA to establish a fixed signal generating device, generating a required waveform signal through the FPGA, and continuously displaying the generated waveform signal on a liquid crystal display screen;
the step 1, generating the required waveform signal through the FPGA, further comprising,
and the FPGA adopts a programmable digital algorithm to process the waveform signals of the channels in real time so as to generate the required waveform signals.
As shown in fig. 2, when the system detects an input frequency value, the frequency value is converted to a shape, and the converted frequency value is input to the phase accumulator. The frequency control words can be accumulated through the phase accumulator, the accumulated data is output as a new address, the waveform is selected through the four waveform tables, and finally the waveform is displayed on an LCD through a digital tube.
As shown in fig. 7, the fixed signal generator takes FPGA as core, and generates the function signal by direct digital frequency synthesizer (DDS) technology. The waveform memory converts the phase information into amplitude information, then converts the amplitude information into a continuous analog signal through a D/A converter, and finally obtains an accurate and continuous required waveform after filtering through a low-pass filter.
Step 2, selecting a small signal amplifier to establish a power amplification device, amplifying the generated waveform signal through the small signal amplifier to form an excitation source meeting the test requirement, loading excitation and testing;
the small signal amplifier adopts a D-type power amplifier.
When the small signal amplifier has a fault or the input waveform signal is incorrect, the protection control device quickly cuts off the output of the small signal amplifier. The protection control device controls the relay switch through the single chip microcomputer to control the output on-off of the small signal amplifier.
As shown in fig. 5, when the small signal amplifier malfunctions or the input waveform signal is erroneous, the load may be damaged. In order to prevent this, it is necessary to cut off the output of the small signal amplifier quickly and reduce the loss. The protection control device controls the relay through the single chip microcomputer, and then controls the output on-off of the small signal amplifier, and the method is economical and reliable.
And 3, selecting a DSP to establish a signal detection processing device, and detecting and processing the test generated signal through the DSP to realize basic noise reduction and harmonic wave removal processing of the test generated signal.
As shown in fig. 8, in general, the voltage or current signal flowing through the device is an analog signal which is continuous in time and value, i.e., there is a definite function value u or i at any time t, and the magnitude of u or i is continuous. The signal detection processing device samples the signals through an A/D device, converts the signals into discrete pulse signals in time, quantizes and codes the pulse signals through a DSP, and converts the pulse signals into binary codes consisting of 0 and 1, namely digital signals commonly known in the field. The DSP can easily perform operations such as conversion, filtering, and the like on these digital signals, and can perform various complicated operations to achieve the intended purpose. The model of the DSP chip adopted by the system is TMS320F2821 PGFA.
and an FIR digital filter in the DSP filters the harmonic waves of the signals generated by the test.
The FIR digital filter is designed by adopting a Chebyshev equal-ripple approximation method, the filter designed by the method can obtain better pass band and stop band performances, and can accurately specify the edges of the pass band and the stop band, and because the errors of the filter in the stop band and the pass band are uniformly distributed, the frequency response of the filter shows equal-ripple performance in the stop band and the pass band, and the order can be lower. As shown in fig. 6, a suitable ideal frequency selective filter is chosen (which is always a non-causal, infinitely long impulse response), and its impulse response is truncated (or windowed) to obtain a linear phase and causal FIR filter.
and the DSP performs basic noise reduction processing on the experimentally generated signal by adopting a frequency spectrum subtraction algorithm.
Spectral subtraction algorithms provide an efficient computational method to enhance speech and reduce noise by subtracting the noise spectrum from the noisy speech spectrum. Noisy speech is segmented and windowed, an FFT is performed for each data window, and a magnitude spectrum is calculated. The VAD is used to detect the incoming speech signal. In the non-speech section, the noise spectrum is estimated and stored in the buffer, and the data in the buffer is attenuated through the algorithm, so that the noise is reduced. During periods of non-speech, there are two ways to produce output: the output is attenuated or set to 0 by a fixed factor. With some residual noise (comfort noise) during non-speech frames, a relatively high speech quality can be output because during speech frames the noise is locally masked by the speech and its amplitude will be balanced over the non-speech segments by the presence of the same amount of noise. Setting the output to 0 on speech segments has the effect of amplifying the noise, so during non-speech it is preferable to attenuate the noise by a fixed factor. A balance must be maintained between amplitude and the noise characteristics perceived over the speech segment, and the noise perceived over the noise segment, so that undesirable acoustic effects, such as buzzes, clicks, jitters, ambiguities in the speech signal, etc., are avoided.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. A design method of an integrated signal generation processing system is characterized in that: the method comprises the following steps:
step 1, selecting an FPGA to establish a fixed signal generating device, generating a required waveform signal through the FPGA, and continuously displaying the generated waveform signal on a liquid crystal display screen;
step 2, selecting a small signal amplifier to establish a power amplification device, amplifying the generated waveform signal through the small signal amplifier to form an excitation source meeting the test requirement, loading excitation and testing;
and 3, selecting a DSP to establish a signal detection processing device, and detecting and processing the test generated signal through the DSP to realize basic noise reduction and harmonic wave removal processing of the test generated signal.
2. The integrated signal generation processing system design method of claim 1, characterized in that: the small signal amplifier adopts a D-type power amplifier.
3. The integrated signal generation processing system design method of claim 1, characterized in that: the step 1, generating the required waveform signal through the FPGA, further comprising,
and the FPGA adopts a programmable digital algorithm to process the waveform signals of the channels in real time so as to generate the required waveform signals.
4. The integrated signal generation processing system design method of claim 1, characterized in that: step 3, selecting a DSP to establish a signal detection processing device, and detecting and processing the test generated signal through the DSP to realize the basic noise reduction and harmonic elimination processing of the test generated signal,
and an FIR digital filter in the DSP filters the harmonic waves of the signals generated by the test.
5. The integrated signal generation processing system design method of claim 1, characterized in that: step 3, selecting a DSP to establish a signal detection processing device, and detecting and processing the test generated signal through the DSP to realize the basic noise reduction and harmonic elimination processing of the test generated signal,
and the DSP performs basic noise reduction processing on the experimentally generated signal by adopting a frequency spectrum subtraction algorithm.
6. The integrated signal generation processing system design method of claim 1, characterized in that: when the small signal amplifier has a fault or the input waveform signal is incorrect, the protection control device quickly cuts off the output of the small signal amplifier.
7. The integrated signal generation processing system design method of claim 6, characterized in that: the protection control device controls the relay switch through the single chip microcomputer to control the output on-off of the small signal amplifier.
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| CN112651104A (en) * | 2020-11-27 | 2021-04-13 | 天津城建大学 | Design method of comprehensive signal detection processing simulation analysis platform |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354873A (en) * | 1999-04-12 | 2002-06-19 | 艾利森电话股份有限公司 | Signal noise reduction by time-domain spectral subtraction using fixed filters |
| CN201053983Y (en) * | 2006-12-29 | 2008-04-30 | 徐红启 | Portable general digital storage oscillograph |
| CN102945674A (en) * | 2012-12-03 | 2013-02-27 | 上海理工大学 | Method for realizing noise reduction processing on speech signal by using digital noise reduction algorithm |
| CN103684625A (en) * | 2012-09-07 | 2014-03-26 | 成都林海电子有限责任公司 | Testing method of Beidou based satellite mobile terminal digital down converter |
| CN105249925A (en) * | 2015-09-25 | 2016-01-20 | 刘垚 | Traditional Chinese medicine pulse manifestation acquisition apparatus, noise reduction system and noise reduction method |
-
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- 2020-11-27 CN CN202011361108.5A patent/CN112671358A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1354873A (en) * | 1999-04-12 | 2002-06-19 | 艾利森电话股份有限公司 | Signal noise reduction by time-domain spectral subtraction using fixed filters |
| CN201053983Y (en) * | 2006-12-29 | 2008-04-30 | 徐红启 | Portable general digital storage oscillograph |
| CN103684625A (en) * | 2012-09-07 | 2014-03-26 | 成都林海电子有限责任公司 | Testing method of Beidou based satellite mobile terminal digital down converter |
| CN102945674A (en) * | 2012-12-03 | 2013-02-27 | 上海理工大学 | Method for realizing noise reduction processing on speech signal by using digital noise reduction algorithm |
| CN105249925A (en) * | 2015-09-25 | 2016-01-20 | 刘垚 | Traditional Chinese medicine pulse manifestation acquisition apparatus, noise reduction system and noise reduction method |
Non-Patent Citations (1)
| Title |
|---|
| 谢标: "基于FGGA的任意波信号发生器的硬件设计与实现", 《中国优秀硕士学位论文全文数据库 工程科技II辑》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112651104A (en) * | 2020-11-27 | 2021-04-13 | 天津城建大学 | Design method of comprehensive signal detection processing simulation analysis platform |
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Application publication date: 20210416 |