CN112671351A - Analog front-end circuit applied to gigabit Ethernet receiver system - Google Patents
Analog front-end circuit applied to gigabit Ethernet receiver system Download PDFInfo
- Publication number
- CN112671351A CN112671351A CN202011501008.8A CN202011501008A CN112671351A CN 112671351 A CN112671351 A CN 112671351A CN 202011501008 A CN202011501008 A CN 202011501008A CN 112671351 A CN112671351 A CN 112671351A
- Authority
- CN
- China
- Prior art keywords
- circuit
- resistor
- signal
- resistors
- sampling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005070 sampling Methods 0.000 claims abstract description 62
- 238000000034 method Methods 0.000 claims abstract description 30
- 230000006978 adaptation Effects 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims description 9
- 230000005540 biological transmission Effects 0.000 claims description 6
- 230000005577 local transmission Effects 0.000 abstract description 13
- 238000010586 diagram Methods 0.000 description 19
- 238000013461 design Methods 0.000 description 9
- 230000003044 adaptive effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000008030 elimination Effects 0.000 description 2
- 238000003379 elimination reaction Methods 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000002592 echocardiography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
The application provides an analog front end circuit applied to a gigabit Ethernet receiver system, comprising: the receiving stage circuit is used for receiving a receiving signal input by the twisted pair; the DAC sampling circuit is used for sampling the local transmission signal; the echo cancellation circuit is electrically connected with the DAC sampling circuit and the receiving stage circuit and is used for canceling a local sending signal contained in a receiving signal; the automatic gain control circuit is electrically connected between the receiving stage circuit and the echo cancellation circuit; and the ECC self-adaptive circuit is electrically connected with the automatic gain control circuit and is used for sending the gain control word to the automatic gain control circuit. The method and the device solve the problem that the echo cancellation capability is reduced under different process angles and temperatures.
Description
Technical Field
The present invention relates to the field of analog front end technologies, and in particular, to an analog front end circuit for a gigabit ethernet receiver system.
Background
The AFE circuit, also called an analog front-end circuit, is mainly responsible for preprocessing a received signal and then delivering the preprocessed signal to the ADC for sampling. The analog front-end circuit generally comprises a baseline drift compensation circuit, an echo cancellation circuit and an automatic gain control circuit, wherein in the traditional analog front-end circuit, the echo cancellation circuit only cancels echoes in received signals, the echo cancellation effect is not considered too much, because resistance can generate deviation due to different process angles and temperatures, DAC sampling signals can also have deviation, the echo cancellation effect can be deteriorated, the automatic gain control circuit mainly carries out direct current compensation on the received signals, the received signals can not be subjected to gain control so as to be matched with the DAC sampling signals with the deviation, and the echo cancellation effect can not be improved.
Disclosure of Invention
The embodiment of the application provides an analog front-end circuit applied to a gigabit Ethernet receiver system, and solves the problem that echo cancellation capability is reduced under different process angles and temperatures.
In a first aspect, an analog front-end circuit applied to a gigabit ethernet receiver system is provided, including: the receiving stage circuit is used for receiving a receiving signal input by the twisted pair; the DAC sampling circuit is used for sampling the local transmitting signal to obtain a sampling signal with a phase difference of 180 degrees with the local transmitting signal; the echo cancellation circuit is electrically connected with the DAC sampling circuit and the receiving stage circuit and is used for cancelling a local sending signal contained in the receiving signal; the automatic gain control circuit is electrically connected between the receiving stage circuit and the echo cancellation circuit; and the ECC self-adaptive circuit is electrically connected with the automatic gain control circuit and is used for sending a control word to the automatic gain control circuit so as to control the gain change of the received signal.
According to the analog front-end circuit provided by the embodiment of the application, because a full-duplex working mode is used in a gigabit ethernet, a local transmission signal and a signal which is transmitted by the other party and needs to be received can pass through the same twisted pair, so that the received signal comprises a signal which is transmitted locally and also comprises a signal which is transmitted externally and needs to be received, an echo cancellation circuit is arranged to cancel the local transmission signal in the received signal, so that only a pure signal which needs to be received remains in the received signal, the principle of echo cancellation is to invert the phase of the local transmission signal by 180 degrees and then add the phase of the local transmission signal with the received signal, so that the local transmission signal with a normal phase in the received signal can be cancelled, but because the resistor used in the circuit for sampling the local transmission signal is a process resistor, the process resistor may have resistance deviation during manufacturing, therefore, the automatic gain control circuit and the ECC self-adaptive circuit are arranged to be matched with each other to eliminate the deviation caused by the process resistor, so that the process resistor with different deviations can be well adapted, the echo elimination capability is not affected, and the echo elimination effect is better.
The method and the device solve the problem that the echo cancellation capability is reduced under different process angles and temperatures, thereby reducing the processing difficulty of a post-stage circuit and enhancing the signal transmission performance of the Ethernet.
In a possible design, the DAC sampling circuit includes a plurality of DAC transmission units, a plurality of sampling resistors R and a DAC sampling unit, one end of the plurality of sampling resistors R is connected with the plurality of DAC transmission units in a one-to-one correspondence, and the other end of the plurality of sampling resistors R is connected with the DAC sampling unit.
In one possible design, the DAC sending unit includes a field effect transistor and a transmitting resistor Rsi, where the transmitting resistor Rsi is a process resistor;
one end of the emitting resistor Rsi is connected with the grid electrode of the field effect transistor, the other end of the emitting resistor Rsi is grounded, and the sampling resistor R is connected to a connecting line between the emitting resistor Rsi and the grid electrode of the field effect transistor.
In one possible design, the DAC sampling unit (302) includes a first operational amplifier and a third resistor, a positive input pin of the first operational amplifier is connected to the sampling resistor R, and two ends of the third resistor are respectively connected to the positive input pin and the output pin of the first operational amplifier.
In one possible design, the echo cancellation circuit is a summation circuit formed by operational amplifiers, and the echo cancellation circuit (40) comprises a second operational amplifier, a fourth resistor and a fifth resistor;
two ends of the fourth resistor are respectively connected with the output pin of the first operational amplifier and the positive input pin of the second operational amplifier, and two ends of the fifth resistor are respectively connected with the positive input pin and the output pin of the second operational amplifier.
In one possible design, the ECC adaptation circuit includes a unity gain op-amp, a reference voltage generation unit, a comparator, and a digital circuit;
the voltage output ends of the unit gain operational amplifier and the reference voltage generating unit are respectively connected with the positive input pin and the negative input pin of the comparator, the output pin of the comparator is connected with the digital circuit, and the digital circuit is used for controlling the output voltage value of the unit gain operational amplifier.
In one possible design, the unity gain operational amplifier comprises two second resistors, a variable resistor Rv and a unity gain amplifier;
the positive input pin of the unity gain amplifier is connected with the two first resistors which are connected in series, and the positive input pin of the unity gain amplifier is grounded;
the first end of the variable resistor Rv is connected with the negative input pin of the unity gain amplifier, the second end of the variable resistor Rv is connected with a connecting line between the two first resistors, the third end of the variable resistor Rv is connected with the digital circuit, and the digital circuit is used for sending control words to the variable resistor Rv to control the resistance value of the variable resistor Rv.
In one possible design, the automatic gain control circuit includes two sixth resistors, two seventh resistors, a gain control unit, and two signal shunting lines;
the receiving stage circuit comprises two differential output ends, the first ends of the two signal shunt lines are respectively connected with the two differential output ends in a one-to-one correspondence manner, and the second ends of the two signal shunt lines are respectively connected with a positive input pin of the second operational amplifier and the digital circuit;
the gain control unit is arranged between the two signal shunt lines, the two sixth resistors and the two seventh resistors are respectively arranged on the two signal shunt lines, the sixth resistors are positioned between the first ends of the signal shunt lines and the gain control unit, and the seventh resistors are positioned between the gain control unit and the second ends of the signal shunt lines;
the digital circuit is also used for sending a control word to the gain control unit to control the resistance value of the gain control unit.
In a possible design, the gain control unit includes five parallel paths, each path is provided with at least one first resistor and a switch, and the resistance values of at least one first resistor on the same path are equal, and the resistance values of the first resistors on different paths are not equal.
In one possible design, the analog front-end circuit further includes: a baseline drift compensation circuit electrically connected to the receive stage circuit;
the receiving stage circuit is a differential output circuit, the compensation voltage of the baseline wander compensation circuit for the baseline wander of the receiving signal is 2R1(I1-I2), R1 is the feedback resistance of the receiving stage circuit, and I1-I2 are the differential output currents of the receiving stage circuit.
Drawings
Fig. 1 is a schematic structural diagram of an analog front-end circuit applied to a gigabit ethernet receiver system according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of a receiving stage circuit provided in an embodiment of the present application.
Fig. 3 is a circuit diagram of a baseline drift compensation circuit provided by an embodiment of the present application.
Fig. 4 is a waveform comparison diagram of the baseline drift compensation circuit provided in the embodiment of the present application for compensating a signal with an offset of 0.75V.
Fig. 5 is a connection circuit diagram of a DAC sampling circuit, an echo cancellation circuit, and an automatic gain control circuit according to an embodiment of the present application.
Fig. 6 is a schematic block diagram of an echo cancellation circuit according to an embodiment of the present application.
Fig. 7 is a circuit diagram of an ECC adaptive circuit according to an embodiment of the present application.
Fig. 8 is a waveform diagram of a simulation of echo cancellation performed in an embodiment of the present application.
Reference numerals: 10. a receiving stage circuit;
20. a baseline drift compensation circuit;
30. a DAC sampling circuit; 301. a DAC transmitting unit; 302. a DAC sampling unit;
40. an echo cancellation circuit;
50. an automatic gain control circuit;
60. an ECC adaptation circuit; 601. a unity gain operational amplifier; 602. a reference voltage generating unit; 603. a comparator; 604. a digital circuit;
70. a low pass filter.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
It should be noted that the same reference numerals are used to denote the same components or parts in the embodiments of the present application, and for the same parts in the embodiments of the present application, only one of the parts or parts may be given the reference numeral, and it should be understood that the reference numerals are also applicable to the other same parts or parts.
The embodiment of the application provides an analog front-end circuit applied to a gigabit Ethernet receiver system, which has a large baseline drift compensation range and solves the problem of reduction of echo cancellation capability under different process angles and temperatures, so that the processing difficulty of a rear-stage circuit is reduced, and the signal transmission performance of Ethernet is enhanced.
Fig. 1 is a schematic structural diagram of an analog front-end circuit applied to a gigabit ethernet receiver system according to an embodiment of the present invention.
As shown in fig. 1, the analog front-end circuit applied to a gigabit ethernet receiver system provided in the embodiments of the present application includes a receiving stage circuit 10, a DAC sampling circuit 30, an echo cancellation circuit 40, an automatic gain control circuit 50, and an ECC adaptation circuit 60. Wherein,
the receiving stage circuit 10 is used for receiving a receiving signal of a twisted pair input. The DAC sampling circuit 30 is configured to sample the local transmit signal to obtain a sampling signal with a phase difference of 180 ° from the local transmit signal. The echo cancellation circuit 40 is electrically connected to the DAC sampling circuit 30 and the receiving stage circuit 10, and is configured to cancel a local transmit signal included in the received signal. The automatic gain control circuit 50 is electrically connected between the receiving stage circuit 10 and the echo cancellation circuit 40. The ECC adaptation circuit 60 is electrically connected to the agc circuit 50 and is configured to send a control word to the agc circuit 50 to control the gain variation of the received signal.
According to the analog front-end circuit provided by the embodiment of the application, because a full-duplex working mode is used in the gigabit ethernet, a local transmission signal and a signal which is transmitted by the other party and needs to be received can pass through the same twisted pair, so that the received signal includes both a signal which is transmitted locally and a signal which needs to be received and is transmitted externally, the echo cancellation circuit 40 is arranged to cancel the local transmission signal in the received signal, so that only a pure signal which needs to be received remains in the received signal, the principle of the echo cancellation is to invert the phase of the local transmission signal by 180 degrees and then add the phase of the local transmission signal to the received signal, so that the local transmission signal with a normal phase in the received signal can be cancelled, but because the resistor used in the DAC sampling circuit 30 which samples the local transmission signal is a process resistor, the resistance deviation may occur during manufacturing, this will result in the reduction of the echo cancellation capability, so the present application further sets the automatic gain control circuit 50 and the ECC adaptive circuit 60 to cooperate with each other to eliminate the deviation caused by the process resistance, so that the present application can adapt well to the process resistance with different deviations, and the echo cancellation capability will not be affected, so that the echo cancellation effect is better.
The method and the device solve the problem that the echo cancellation capability is reduced under different process angles and temperatures, thereby reducing the processing difficulty of a post-stage circuit and enhancing the signal transmission performance of the Ethernet.
Fig. 5 is a connection circuit diagram of the DAC sampling circuit 30, the echo cancellation circuit 40, and the automatic gain control circuit 50 according to the embodiment of the present application. Fig. 7 is a circuit diagram of an ECC adaptation circuit 60 provided in an embodiment of the present application.
The DAC sampling circuit 30 includes a plurality of DAC sending units 301, a plurality of sampling resistors R, and a DAC sampling unit 302, wherein one ends of the plurality of sampling resistors R are respectively connected to the plurality of DAC sending units 301 in a one-to-one correspondence, and the other ends of the plurality of sampling resistors R are connected to the DAC sampling unit 302. As shown in fig. 5, optionally, in the embodiment of the present application, the number of DAC sending units 301 is 9, and the number of sampling resistors R is 9, and fig. 5 shows a connection relationship diagram of only one of DAC sending units 301 and one of sampling resistors R.
As shown in fig. 5, the DAC sending unit 301 includes a field effect transistor and an emitting resistor Rsi, where the emitting resistor Rsi is a process resistor; one end of the emitting resistor Rsi is connected with the grid electrode of the field effect transistor, the other end of the emitting resistor Rsi is grounded, and the sampling resistor R is connected to a connecting line between the emitting resistor Rsi and the grid electrode of the field effect transistor.
The DAC sampling unit 302 includes a first operational amplifier and a third resistor, a positive input pin of the first operational amplifier is connected to the sampling resistor R, and two ends of the third resistor are respectively connected to the positive input pin and the output pin of the first operational amplifier.
As shown in fig. 5, the transmission resistance Rsi in the DAC transmission unit 301 is a process resistance, the resistance value of the process resistor at different process angles and temperatures has a deviation of +/-20%, once the transmitting resistor Rsi has a deviation, the sampling signal acquired by the DAC sampling unit 302 also has a deviation, the amplitude of the local transmit signal is constant because the amplitude of the local transmit signal is related only to the ratio of the resistances, and not to the absolute magnitude of the resistances, therefore, the amplitude of the signal coupled to the MDI line by the transmitting end, i.e. the local transmit signal contained in the received signal, remains the same, so that the amplitude of the sampled signal is different from the local transmit signal contained in the received signal, and the mismatch between the two signals will directly result in the degradation of the echo cancellation performance, therefore, the present application provides that the automatic gain control circuit 50 and the ECC adaptation circuit 60 cooperate with each other to eliminate the deviation caused by the process resistance.
As shown in fig. 5, the echo cancellation circuit 40 is a summation circuit formed by operational amplifiers, and the echo cancellation circuit 40 includes a second operational amplifier, a fourth resistor, and a fifth resistor; two ends of the fourth resistor are respectively connected with the output pin of the first operational amplifier and the positive input pin of the second operational amplifier, and two ends of the fifth resistor are respectively connected with the positive input pin and the output pin of the second operational amplifier.
Fig. 6 is a schematic block diagram of an echo cancellation circuit 40 according to an embodiment of the present application. As shown in fig. 6, the frequency and amplitude of the sampling signal collected by the DAC sampling unit 302 are equal to the local transmit signal, and the phase difference is 180 °, and the phase of the receive signal received by the receiving stage circuit 10 is the same as the phase of the local transmit signal, so that the principle of echo cancellation is to add the sampling signal and the receive signal, so as to cancel the positive and negative of the local transmit signal and the sampling signal included in the receive signal, thereby removing the local transmit signal included in the receive signal, and obtaining a pure receive signal.
As shown in fig. 5, the automatic gain control circuit 50 includes two sixth resistors, two seventh resistors, a gain control unit, and two signal shunting lines;
the receiving-stage circuit 10 includes two differential output terminals, first ends of the two signal shunting lines are respectively connected with the two differential output terminals in a one-to-one correspondence, and second ends are respectively connected with a positive input pin of the second operational amplifier and the digital circuit 604;
the gain control unit is arranged between the two signal shunt lines, the two sixth resistors and the two seventh resistors are respectively arranged on the two signal shunt lines, the sixth resistors are positioned between the first ends of the signal shunt lines and the gain control unit, and the seventh resistors are positioned between the gain control unit and the second ends of the signal shunt lines;
the digital circuit 604 is also arranged to send a control word to the gain control unit to control the resistance of the gain control unit.
The gain control unit comprises five parallel-connected paths, each path is provided with at least one first resistor and a switch, the resistance values of the at least one first resistor on the same path are equal, and the resistance values of the first resistors on different paths are unequal.
Optionally, when two or more first resistors are disposed on each via, the two or more first resistors are connected in series.
Through the above setting, which switch is closed, and which path is connected, which means that the automatic gain control circuit 50 selects the gain corresponding to the connected path to adjust the amplitude of the received signal, and at this time, the resistor on the line is the equivalent parallel resistor formed by the resistor on the connected path, the sixth resistor and the seventh resistor, and in order to enable the automatic gain control circuit 50 to well adjust the amplitude of the received signal to match the sampled signal when the sampled signal has any deviation within the deviation range from the minimum deviation to the maximum deviation, the resistance values of the first resistors set on the five paths in the automatic gain control circuit 50 of the present application are set according to the deviation value of the transmitting resistor Rsi, for example, two first resistors are respectively set on the five paths in the automatic gain control circuit 50 in fig. 5, and the set resistance values of the first resistors are R1, 16R1, 8R1, 2R1 and 4R 1.
As shown in fig. 5 and 7, the ECC adaptation circuit 60 includes a unity gain operational amplifier 601, a reference voltage generating unit 602, a comparator 603, and a digital circuit 604, wherein voltage output terminals of the unity gain operational amplifier 601 and the reference voltage generating unit 602 are respectively connected to positive and negative input pins of the comparator 603, an output pin of the comparator 603 is connected to the digital circuit 604, and the digital circuit 604 is used for controlling an output voltage value of the unity gain operational amplifier 601.
The unity gain operational amplifier 601 comprises two second resistors, a variable resistor Rv and a unity gain amplifier; the positive input pin of the unity gain amplifier is connected with the two first resistors which are connected in series, and the positive input pin of the unity gain amplifier is grounded; the first end of the variable resistor Rv is connected with the negative input pin of the unity gain amplifier, the second end of the variable resistor Rv is connected with a connecting line between the two first resistors, the third end of the variable resistor Rv is connected with the digital circuit 604, and the digital circuit 604 is used for sending a control word to the variable resistor Rv to control the resistance value of the variable resistor Rv.
In the present application, the amplitude of the received signal can be adjusted by controlling different gains through the automatic gain control circuit 50, but it is determined by the ECC adaptive circuit 60 that which channel is controlled to obtain the corresponding gain, the second resistors R1 and R2 in the ECC adaptive circuit 60 are process resistors, and the resistance values will have a deviation of ± 20% at different process angles and temperatures, so that the voltage value of V1 will be affected, and the values of V1 and V2 will not be equal, and further the output signal will have a voltage deviation, where the voltage deviation caused by the resistance deviation generated by the second resistors R1 and R2 can correspond to the deviation generated by the sampling signal, the ECC adaptive circuit 60 can obtain an accurate control word by adjusting its own voltage deviation, and further send the accurate control word to the automatic gain control circuit 50 to accurately control the gain change, specifically, the resistance value of the variable resistor Rv in the ECC adaptive circuit 60 can change, the value of V1 can be changed by changing the value of Rv, the values of V1 and V2 are not equal initially due to resistance deviation generated by the second resistors R1 and R2, the comparison result is output to the digital circuit 604 through the comparator 603, and the digital circuit 604 generates a control word according to the comparison result and sends the control word to Rv and the agc circuit 50 simultaneously, so as to control the change of the resistance of Rv, the change of the value of V1, further, the output result of the comparator 603 changes, the digital circuit 604 generates a new control word and sends the new control word to the Rv and the agc circuit 50, and the above process is repeated until the values of V1 and V2 are equal, at which time the voltage deviation caused by the resistance deviation is eliminated, and the control word generated by the digital circuit 604 when the values of V1 and V2 are equal controls the gain adjusted by the agc circuit 50 to adjust the amplitude of the received signal to match the sampled signal.
The principle of the digital circuit 604 of the ECC adaptation circuit 60 to generate the control word is: after the circuit is enabled, assuming that the resistance deviation generated by the second resistors R1 and R2 causes the value of V1 to be smaller than the value of V2, and the output of the comparator 603 is 0, assuming that the initial control word generated by the digital circuit 604 is 0, the digital counter in the digital circuit 604 starts counting up from 0 to 31, the resistance value of the corresponding Rv changes, so that the value of V1 increases, when the value of V1 increases to a certain value larger than V2, the output of the comparator 603 jumps from 0 to 1, and starts counting down from the current number, and the resistance value of the corresponding Rv changes, so that the value of V1 decreases, and when the value of V1 decreases to a certain value smaller than V2, the output of the comparator 603 jumps from 1 to 0, and starts counting up again from the current number, the value of V1 starts increasing, and the above process repeats, finally, the value of V1 is adjusted to be slightly different from the value of V2, and the control word counted by the digital counter will jump back and forth between two adjacent control words, in practical application, a timer is provided in the digital circuit 604, when the circuit is enabled, the timer starts to count time, the digital counter is turned off after the counting is finished, the control word is locked into one of two adjacent control words which jump back and forth, the locked control word eliminates the voltage deviation caused by the resistance deviation generated by the second resistors R1 and R2 in the ECC adaptive circuit 60, the control word is sent to the automatic gain control circuit 50 to control the automatic gain control circuit to select proper gain to adjust the amplitude of the received signal, therefore, when different deviations occur in the sampling signals, different control words can be determined by the method, so that the voltage deviation is counteracted, and the best effect of echo cancellation is ensured.
The information amount of the digital circuit 604 of the ECC adaptive circuit 60 is 5 bits, so that the count of the digital counter is from 0 to 31, for example, in a typical case, if there is no resistance deviation, the values of V1 and V2 are equal, the control word generated by the digital circuit 604 is 16, when there is a resistance deviation, the control word determined by the digital circuit 604 for eliminating the voltage deviation changes, and may be greater than 16 or less than 16, after the control word is sent to the automatic gain control circuit 50, the automatic gain control circuit 50 determines which path to close the switch according to the number of bits of the control word deviating from the control word 16 in the typical case, so that different control words can be generated for different deviations, and further, the automatic gain control circuit 50 is controlled to generate different gains to adjust the amplitude of the received signal to offset the voltage deviation caused by the resistance deviation, the received signal is matched with the sampling signal, and the echo cancellation effect is optimal.
Fig. 8 is a waveform diagram of a simulation of echo cancellation performed in an embodiment of the present application. Fig. 8 is a waveform diagram of the received signal, the local transmit signal, the signal obtained by superimposing the received signal and the local transmit signal, and the signal obtained by echo cancellation from top to bottom in sequence, and it can be seen that the signal obtained by echo cancellation has good integrity.
Fig. 2 is a circuit diagram of the receiving stage circuit 10 according to an embodiment of the present disclosure. Fig. 3 is a circuit diagram of the baseline wander compensation circuit 20 according to an embodiment of the present disclosure. Fig. 4 is a waveform comparison diagram of the baseline drift compensation circuit 20 provided in the embodiment of the present application for compensating the signal with an offset of 0.75V.
As shown in fig. 2-3, the analog front-end circuit further includes: a baseline wander compensation circuit 20, the baseline wander compensation circuit 20 being electrically connected to the receiving stage circuit 10; the receiving stage circuit 10 is a differential output circuit, the baseline wander compensation circuit 20 has a compensation voltage of 2R1(I1-I2) for the baseline wander of the received signal, R1 is the feedback resistance of the receiving stage circuit 10, and I1-I2 are the differential output currents of the receiving stage circuit 10.
In the above arrangement, the receiving stage circuit 10 is connected to the baseline wander compensation circuit 20, M1 and M2 in the baseline wander compensation circuit 20 are field effect transistors, the gate of M1 is connected to the control voltage Vcp generated by the charge pump, and the gate of M2 is connected to a reference voltage Vref having a fixed value. When there is no baseline wander, the common mode level MDI _ N of the twisted pair input signal of the receiving stage circuit 10 is MDI _ P, which means that the differential output signals Vx and Vy of the receiving stage circuit 10 are symmetrical, and at this time, the signal received by the subsequent stage circuit is normal, the controller in the receiver system does not send a compensation control signal to the baseline wander compensation circuit, the voltages of Vcp and Vref in the baseline wander compensation circuit 20 are the same, the currents flowing through M1 and M2 are the same, the voltages at the two ends of the resistor R are the same, and the baseline wander compensation circuit 20 does not adjust the input signal of the receiving stage circuit 10; when there is a baseline wander, the common mode level MDI _ N of the twisted pair input signal of the receiving stage circuit 10 is not equal to MDI _ P, which means that the differential output signals Vx and Vy of the receiving stage circuit 10 are asymmetric, and at this time, the controller in the receiver system will send a compensation control signal to the baseline wander compensation circuit 20, and the baseline wander compensation circuit 20 corrects the wander phenomenon, specifically, the correction process is as follows: the value of Vcp is changed to be different from the value of the reference voltage Vref through charge pump control, so that the currents flowing through M1 and M2 are different, and thus a current is generated on the resistor R, the change trends of I1 and I2 are changed differentially because the total current is constant, the differential output currents (I1-I2) and (I2-I1) of the receiving stage circuit 10 respectively flow through the feedback resistor R1 of the receiving stage circuit 10, the voltage drop generated by the differential output current of the feedback resistor R1 is a compensation voltage of baseline drift, and the size of the voltage capable of being compensated is 2R1 (I1-I2); if the received signal finally obtained by the receiver system still has drift after the baseline drift compensation is completed, the controller in the receiver system will continue to send the compensation control signal to the baseline drift compensation circuit 20, and then the baseline drift compensation circuit 20 again changes the value of Vcp to be different from the value of the reference voltage Vref by the charge pump control, and performs voltage compensation again, and the above compensation process continuously loops until the receiver system detects that the finally received signal is normal and has no drift.
Because the variable values of I1-I2 exist in the calculation formula of the compensation voltage of the baseline wander, the voltage compensation range of the baseline wander can be wide, so that the application can complete more kinds of compensation of the baseline wander phenomenon.
Fig. 4 is a waveform comparison diagram of the baseline shift compensation circuit 20 according to the embodiment of the present application, which compensates for the signal with the offset of 0.75V.
As shown in fig. 1, the analog front end circuit further includes a low pass filter 70, the low pass filter 70 being electrically connected to the echo cancellation circuit 40. With the above arrangement, the high-frequency noise in the echo-cancelled received signal can be filtered out by the low-pass filter 70.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An analog front-end circuit for a gigabit ethernet receiver system, comprising:
a receiving stage circuit (10) for receiving a receiving signal inputted by the twisted pair;
the DAC sampling circuit (30) is used for sampling the local transmitting signal to obtain a sampling signal with a phase difference of 180 degrees with the local transmitting signal;
an echo cancellation circuit (40) electrically connected to the DAC sampling circuit (30) and the receiving stage circuit (10) for cancelling a local transmit signal contained in the receive signal;
an automatic gain control circuit (50) electrically connected between the receiving stage circuit (10) and the echo cancellation circuit (40);
an ECC adaptation circuit (60) electrically connected to the automatic gain control circuit (50) for sending a control word to the automatic gain control circuit (50) to control a gain variation of the received signal.
2. The analog front-end circuit according to claim 1, wherein the DAC sampling circuit (30) comprises a plurality of DAC transmission units (301), a plurality of sampling resistors R, and a DAC sampling unit (302), wherein one ends of the plurality of sampling resistors R are respectively connected with the plurality of DAC transmission units (301) in a one-to-one correspondence, and the other ends of the plurality of sampling resistors R are connected with the DAC sampling unit (302).
3. The analog front-end circuit according to claim 2, wherein the DAC sending unit (301) comprises a fet and a sending resistor Rsi, the sending resistor Rsi being a process resistor;
one end of the emitting resistor Rsi is connected with the grid electrode of the field effect transistor, the other end of the emitting resistor Rsi is grounded, and the sampling resistor R is connected to a connecting line between the emitting resistor Rsi and the grid electrode of the field effect transistor.
4. The analog front-end circuit of claim 2, wherein the DAC sampling unit (302) comprises a first operational amplifier and a third resistor, wherein a positive input pin of the first operational amplifier is connected to the sampling resistor R, and two ends of the third resistor are respectively connected to the positive input pin and the output pin of the first operational amplifier.
5. The analog front-end circuit according to claim 4, wherein the echo cancellation circuit (40) is a summing circuit of operational amplifiers, the echo cancellation circuit (40) comprising a second operational amplifier, a fourth resistor and a fifth resistor;
two ends of the fourth resistor are respectively connected with the output pin of the first operational amplifier and the positive input pin of the second operational amplifier, and two ends of the fifth resistor are respectively connected with the positive input pin and the output pin of the second operational amplifier.
6. The analog front-end circuit according to claim 5, wherein the ECC adaptation circuit (60) comprises a unity gain operational amplifier (601), a reference voltage generation unit (602), a comparator (603), and a digital circuit (604);
the voltage output ends of the unit gain operational amplifier (601) and the reference voltage generating unit (602) are respectively connected with the positive input pin and the negative input pin of the comparator (603), the output pin of the comparator (603) is connected with the digital circuit (604), and the digital circuit (604) is used for controlling the output voltage value of the unit gain operational amplifier (601).
7. The analog front-end circuit according to claim 6, wherein the unity gain operational amplifier (601) comprises two second resistors, a variable resistor Rv, and a unity gain amplifier;
the positive input pin of the unity gain amplifier is connected with the two first resistors which are connected in series, and the positive input pin of the unity gain amplifier is grounded;
the first end of the variable resistor Rv is connected with the negative input pin of the unity gain amplifier, the second end of the variable resistor Rv is connected with a connecting line between the two first resistors, the third end of the variable resistor Rv is connected with the digital circuit (604), and the digital circuit (604) is used for sending a control word to the variable resistor Rv so as to control the resistance value of the variable resistor Rv.
8. The analog front-end circuit according to claim 6, characterized in that the automatic gain control circuit (50) comprises two sixth resistors, two seventh resistors, a gain control unit and two signal shunting lines;
the receiving stage circuit (10) comprises two differential output ends, first ends of the two signal shunt lines are respectively connected with the two differential output ends in a one-to-one correspondence manner, and second ends of the two signal shunt lines are respectively connected with a positive input pin of the second operational amplifier and the digital circuit (604);
the gain control unit is arranged between the two signal shunt lines, the two sixth resistors and the two seventh resistors are respectively arranged on the two signal shunt lines, the sixth resistors are positioned between the first ends of the signal shunt lines and the gain control unit, and the seventh resistors are positioned between the gain control unit and the second ends of the signal shunt lines;
the digital circuit (604) is further configured to send a control word to the gain control unit to control a resistance of the gain control unit.
9. The analog front-end circuit of claim 8, wherein the gain control unit comprises five parallel paths, each path has at least one first resistor and a switch, and at least one of the first resistors on a same path has an equal resistance, and the first resistors on different paths have unequal resistances.
10. The analog front-end circuit according to any one of claims 1 to 9, further comprising:
a baseline drift compensation circuit (20) electrically connected to the receive stage circuit (10);
the receiving stage circuit (10) is a differential output circuit, the compensation voltage of the baseline wander compensation circuit (20) for the baseline wander of the received signal is 2R1(I1-I2), R1 is the feedback resistance of the receiving stage circuit (10), and I1-I2 is the differential output current of the receiving stage circuit (10).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011501008.8A CN112671351B (en) | 2020-12-17 | 2020-12-17 | Analog front-end circuit applied to gigabit Ethernet receiver system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011501008.8A CN112671351B (en) | 2020-12-17 | 2020-12-17 | Analog front-end circuit applied to gigabit Ethernet receiver system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112671351A true CN112671351A (en) | 2021-04-16 |
| CN112671351B CN112671351B (en) | 2023-12-15 |
Family
ID=75406173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011501008.8A Active CN112671351B (en) | 2020-12-17 | 2020-12-17 | Analog front-end circuit applied to gigabit Ethernet receiver system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112671351B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3499999A (en) * | 1966-10-31 | 1970-03-10 | Bell Telephone Labor Inc | Closed loop adaptive echo canceller using generalized filter networks |
| CN1193424A (en) * | 1995-06-30 | 1998-09-16 | 艾利森电话股份有限公司 | Adaptive gain controller |
| CN1344478A (en) * | 1998-09-30 | 2002-04-10 | 印菲内奥技术股份有限公司 | Line terminator unit for subscriber line |
| CN1347204A (en) * | 2000-10-11 | 2002-05-01 | 印芬龙科技股份有限公司 | Programmable echo eliminating filter |
| CN1561010A (en) * | 2004-03-02 | 2005-01-05 | 复旦大学 | Echo cancel circuit for billion Ethernet receiver |
| CN1618180A (en) * | 2001-12-26 | 2005-05-18 | 格鲁斯番维拉塔公司 | Simple adaptive hybrid circuit |
| CN101425824A (en) * | 2007-09-17 | 2009-05-06 | 英飞凌科技股份公司 | Echo is eliminated |
| CN102195674A (en) * | 2010-03-15 | 2011-09-21 | 株式会社东芝 | Echo cancellation circuit |
| CN103457633A (en) * | 2012-08-03 | 2013-12-18 | 万高(杭州)科技有限公司 | Echo noise elimination full mixed line interface |
-
2020
- 2020-12-17 CN CN202011501008.8A patent/CN112671351B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3499999A (en) * | 1966-10-31 | 1970-03-10 | Bell Telephone Labor Inc | Closed loop adaptive echo canceller using generalized filter networks |
| CN1193424A (en) * | 1995-06-30 | 1998-09-16 | 艾利森电话股份有限公司 | Adaptive gain controller |
| CN1344478A (en) * | 1998-09-30 | 2002-04-10 | 印菲内奥技术股份有限公司 | Line terminator unit for subscriber line |
| CN1347204A (en) * | 2000-10-11 | 2002-05-01 | 印芬龙科技股份有限公司 | Programmable echo eliminating filter |
| CN1618180A (en) * | 2001-12-26 | 2005-05-18 | 格鲁斯番维拉塔公司 | Simple adaptive hybrid circuit |
| CN1561010A (en) * | 2004-03-02 | 2005-01-05 | 复旦大学 | Echo cancel circuit for billion Ethernet receiver |
| CN101425824A (en) * | 2007-09-17 | 2009-05-06 | 英飞凌科技股份公司 | Echo is eliminated |
| CN102195674A (en) * | 2010-03-15 | 2011-09-21 | 株式会社东芝 | Echo cancellation circuit |
| CN103457633A (en) * | 2012-08-03 | 2013-12-18 | 万高(杭州)科技有限公司 | Echo noise elimination full mixed line interface |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112671351B (en) | 2023-12-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7327995B1 (en) | Active resistance summer for a transformer hybrid | |
| US8045946B2 (en) | Active resistive summer for a transformer hybrid | |
| EP1566885B1 (en) | Adaptive equalizer with DC offset compensation | |
| TWI523439B (en) | Method and system for compensating mode conversion over a communications channel | |
| US7812747B2 (en) | System and method for common mode calibration in an analog to digital converter | |
| EP1566932A2 (en) | Adaptive equalizer with DC offset compensation | |
| CA2201834A1 (en) | Serial digital data communications receiver with improved automatic cable equalizer, agc system, and dc restorer | |
| DE102005007632A1 (en) | Amplifier arrangement and method for adjusting an offset | |
| CN105763491B (en) | A kind of DC maladjustment suppression circuit in wireless receiver | |
| US7795944B2 (en) | Low-offset input circuit including amplifier circuit to correct circuit characteristics to cancel offset of the input circuit | |
| US11658628B2 (en) | Semiconductor integrated circuit, receiving device, and DC offset cancellation method | |
| US20200014567A1 (en) | EHF Receiver Architecture with Dynamically Adjustable Discrimination Threshold | |
| US11546002B2 (en) | Transmitter, receiver and transceiver | |
| US20060280234A1 (en) | Single amplifier presample processing circuitry | |
| CN115811371A (en) | Threshold programmable loss of signal detection circuit with temperature and process compensation | |
| US11063628B2 (en) | Communication device capable of echo cancellation | |
| CN112671351A (en) | Analog front-end circuit applied to gigabit Ethernet receiver system | |
| US7254173B1 (en) | Digitally adjusted high speed analog equalizer | |
| US7209007B1 (en) | Combined analog signal gain controller and equalizer | |
| CN116232245A (en) | Variable gain amplifying circuit applied to Ethernet communication | |
| US20230050659A1 (en) | Offset circuitry and threshold reference circuitry for a capture flip-flop | |
| KR20230140255A (en) | Differential amplifier capable of offset compensation of differential output signal and adaptive continuous-time linear equalizer including the same | |
| KR101869887B1 (en) | Circuit for correcting the output mismatch in trans-impedance amplifier | |
| US11218232B1 (en) | DC offset calibration system and method | |
| US11152904B2 (en) | Programmable gain amplifier with programmable resistance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |