CN112670236A - NOR FLASH device isolation dielectric layer and preparation method thereof - Google Patents

NOR FLASH device isolation dielectric layer and preparation method thereof Download PDF

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Publication number
CN112670236A
CN112670236A CN202011540662.XA CN202011540662A CN112670236A CN 112670236 A CN112670236 A CN 112670236A CN 202011540662 A CN202011540662 A CN 202011540662A CN 112670236 A CN112670236 A CN 112670236A
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Prior art keywords
layer
flash device
depositing
oxide layer
isolation
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CN202011540662.XA
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Inventor
李雪健
李志林
张继亮
顾林
王虎
郭霞文
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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Abstract

The application relates to the field of semiconductor integrated circuit manufacturing, in particular to a NOR FLASH device isolation medium layer and a preparation method thereof. The method comprises the following steps: providing a NOR FLASH device, wherein a plurality of storage unit cells are formed on the NOR FLASH device, and an isolation gap is formed between every two adjacent storage unit cells; depositing a liner layer on the inner surface of the isolation gap; depositing and forming an HDP oxide layer with a first preset thickness by an HDP deposition process; the HDP oxide layer covers the isolation gap formed with the liner layer and the memory unit cell; and depositing and forming a HARP oxide layer with a second preset thickness on the surface of the device by a HARP deposition process according to the surface appearance of the device on which the HDP oxide layer is formed. The NOR FLASH device isolation dielectric layer can be manufactured and formed by the method. The application provides an isolation dielectric layer of a NOR FLASH device and a preparation method thereof, which can solve the problem that the GOI of a wafer is adversely affected when the isolation dielectric layer of the NOR FLASH device is manufactured by the related technology.

Description

NOR FLASH device isolation dielectric layer and preparation method thereof
Technical Field
The application relates to the field of semiconductor integrated circuit manufacturing, in particular to a NOR FLASH device isolation medium layer and a preparation method thereof.
Background
The NOR FLASH device is one type of nonvolatile FLASH memory and comprises a plurality of array-type parallel memory units, and isolation medium layers are arranged between every two memory units at intervals.
In the related art, the isolation dielectric layer is usually deposited by a High Density Plasma (HDP) process, but since the HDP process itself has High Plasma characteristics, the characteristics may adversely affect the Gate Oxide Integrity (GOI) of the wafer.
Disclosure of Invention
The application provides an isolation dielectric layer of a NOR FLASH device and a preparation method thereof, which can solve the problem that the GOI of a wafer is adversely affected when the isolation dielectric layer of the NOR FLASH device is manufactured by the related technology.
As a first aspect of the present application, a method for preparing an isolation dielectric layer of a NOR FLASH device is provided, where the method for preparing the isolation dielectric layer of the NNOR FLASH device includes the following steps:
providing a NOR FLASH device, wherein a plurality of storage unit cells are formed on the NOR FLASH device, and an isolation gap is formed between every two adjacent storage unit cells;
depositing a liner layer on the inner surface of the isolation gap;
depositing and forming an HDP oxide layer with a first preset thickness by an HDP deposition process; the HDP oxide layer covers the isolation gap formed with the liner layer and the memory unit cell;
and depositing and forming a HARP oxide layer with a second preset thickness on the surface of the device by a HARP deposition process according to the surface appearance of the device on which the HDP oxide layer is formed.
Optionally, the step of depositing a liner layer on the inner surface of the isolation gap includes:
depositing a silicon oxynitride layer on the inner surface of the isolation gap;
depositing a nitride layer on the silicon oxynitride layer; the stacked silicon oxynitride layer and the nitride layer form the pad layer.
Optionally, in the step of depositing and forming the HDP oxide layer with the first predetermined thickness by the HDP deposition process, the first predetermined thickness for forming the HDP oxide layer is 1000 angstroms to 2000 angstroms.
Optionally, in the step of depositing a HARP oxide layer with a second predetermined thickness on the surface of the device according to the surface topography of the device on which the HDP oxide layer is formed by the HARP deposition process, the second predetermined thickness for forming the HARP oxide layer is: 1000 angstroms to 2000 angstroms.
Optionally, after depositing the HARP oxide layer with the second predetermined thickness, further performing:
depositing a silicon dioxide layer on the HARP oxide layer.
Optionally, the thickness of the silicon dioxide layer is 200 to 800 angstroms.
Optionally, the liner layer has a thickness of 200 to 800 angstroms.
As a second aspect of the present application, there is provided a NOR FLASH device isolation dielectric layer manufactured by the method for manufacturing a NOR FLASH device isolation dielectric layer according to any one of claims 1 to 7.
The technical scheme at least comprises the following advantages: on one hand, the method can avoid the situation that high-density plasma exists for too long time, and prevent the GOI performance of the wafer from being adversely affected; on the other hand, the aspect ratio of the remaining portion of the isolation gap is reduced, and the filling of the isolation gap by the HARP deposition process does not cause the problem of void formation.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 illustrates a flow of a method for manufacturing an isolation dielectric layer of a NOR FLASH device according to an embodiment of the present application;
fig. 2a to 2b show schematic cross-sectional structures of the provided NOR FLASH device after the main steps have been completed;
fig. 2c is a schematic cross-sectional view of the device after step S2 is completed according to the present embodiment;
fig. 2d is a schematic cross-sectional structure diagram of the device after step S3 is completed in this embodiment;
fig. 2e is a schematic cross-sectional view of the device after step S4 is completed according to the present embodiment; .
Fig. 2f is a schematic cross-sectional view of the device after step S5 is completed according to the present embodiment;
FIG. 3 is a schematic diagram illustrating a cross-sectional structure of an isolation dielectric layer of a NOR FLASH device according to an embodiment of the present application;
FIG. 4 is a graph showing the breakdown voltage profile of the gate oxide of a NOR FLASH device fabricated by the method provided by the embodiments of the present application;
FIG. 5 is a graph showing the bit line bridge voltage distribution of a NOR FLASH device fabricated using the method provided by the embodiments of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 schematically shows a process of a method for preparing an isolation dielectric layer of a NOR FLASH device according to an embodiment of the present application, and referring to fig. 1, the method for preparing the isolation dielectric layer of the NOR FLASH device includes the following steps:
step S1: a NOR FLASH device is provided, wherein a plurality of storage unit cells are formed on the NOR FLASH device, and isolation gaps are formed between the adjacent storage unit cells.
Fig. 2a to 2b are schematic cross-sectional views illustrating the main steps of the provided NOR FLASH device after completion, and referring to fig. 2a, a gate dielectric layer 110, a floating gate polysilicon layer 120, a dielectric layer 130, a control gate polysilicon layer 140 and a mask layer 150 are sequentially formed on a semiconductor substrate. The dielectric layer 130 includes a first oxide film, a nitride film, and a second oxide film stacked in this order from bottom to top.
Then, the mask layer 150, the control gate polysilicon layer 140, the dielectric layer 130, the floating gate polysilicon layer 120 and the gate dielectric layer 110 are sequentially etched by a photolithography process to form a memory cell (cell) of the NOR FLASH device, referring to fig. 2b, which illustrates a cross-sectional structure of the NOR FLASH device including two adjacent memory cells, and an isolation gap 160 is formed between the adjacent memory cells.
Step S2: and depositing a liner layer on the inner surface of the isolation gap.
In this embodiment, a silicon oxynitride layer may be deposited on the inner surface of the isolation gap, and then a nitride layer may be deposited on the silicon oxynitride layer. The stacked silicon oxynitride layer and the nitride layer form the pad layer. Fig. 2c schematically shows the cross-sectional structure of the device after step S2 is completed, and referring to fig. 2c, a stacked silicon oxynitride layer and a nitride layer are sequentially deposited on the inner surface of the isolation gap 160, and the stacked silicon oxynitride layer and nitride layer serve as a liner layer 171 and function as a liner. Methods of forming the silicon oxynitride layer and the nitride layer include, but are not limited to: thermal oxidation, chemical vapor deposition, and physical vapor deposition. The thickness of the formed liner layer 171 may be: 200 angstroms to 800 angstroms.
Step S3: depositing and forming an HDP oxide layer with a first preset thickness by an HDP deposition process; the HDP oxide layer covers the isolation gap formed with the liner layer and the memory cell.
The HDP deposition process refers to a High Density Plasma (HDP) process, in which process gas is introduced under a low pressure condition, a radio frequency source is applied to generate a High Density Plasma, and after the High Density Plasma is generated, film deposition starts. In this embodiment, a silicon source gas, an oxygen source gas, and some inert gases are introduced under a low pressure condition of 2 mtorr to 10 mtorr, and the ion density of the generated high-density plasma can reach 1011cm-3To 1012cm-3。
In this embodiment, the first predetermined thickness of the HDP oxide layer deposited by the HDP deposition process in the isolation gap formed with the liner layer may be 1000 angstroms to 2000 angstroms.
Although the HDP Oxide layer formed by the HDP deposition process can achieve a good filling capability, at the same time, since the HDP deposition process generates a high density plasma, the high density plasma can adversely affect the Gate Oxide Integrity (GOI) of the wafer, and referring to fig. 2d, a schematic cross-sectional structure of the device after step S3 is completed in this embodiment, in which the HDP Oxide layer 172 with a first predetermined thickness is deposited to fill the lower portion of the isolation gap 160 and the memory cell. The remaining portion of the isolation gap 160 will be filled in a subsequent step.
Step S4: and depositing and forming a HARP oxide layer with a second preset thickness on the surface of the device by a HARP deposition process according to the surface appearance of the device on which the HDP oxide layer is formed.
The HARP deposition Process refers to a High Aspect Ratio (HARP) deposition Process. As the feature size of semiconductor devices continues to decrease, the aspect ratio of the isolation gap is made larger and larger, although the HARP deposition process does not involve the problem that high density plasma adversely affects the GOI performance of the wafer. However, due to the high conformality of the HARP deposition process, if the HARP oxide layer is deposited only on the isolation gap by the HARP deposition process, the isolation gap will have a large aspect ratio, resulting in filling the void.
Referring to fig. 2e, which shows a schematic cross-sectional structure of the device after step S4, in this embodiment, step S3 and the HDP deposition process are performed in advance to form a HDP oxide layer 172 with a first predetermined thickness in the isolation gap 160 with the liner layer formed thereon, and the HDP oxide layer 172 with the first predetermined thickness fills the lower portion of the isolation gap 160. On the basis, the aspect ratio of the remaining portion of the isolation gap 160 is reduced, so that in step S4, a HARP oxide layer 173 with a second predetermined thickness is deposited and formed on the surface of the device according to the surface topography of the device on which the HDP oxide layer 172 is formed by a HARP deposition process, so that the formed HARP oxide layer 173 with the second predetermined thickness is filled in the remaining portion of the isolation gap 160, on one hand, the existence of high-density plasma for a long time can be avoided, and the adverse effect on the GOI performance of the wafer can be prevented; on the other hand, the aspect ratio of the remaining portion of the isolation gap is reduced, and the filling of the isolation gap by the HARP deposition process does not cause the problem of void formation.
In this embodiment, in the step of depositing the HARP oxide layer with a second predetermined thickness on the surface of the device according to the surface topography of the device on which the HDP oxide layer is formed by the HARP deposition process, the second predetermined thickness of the HARP oxide layer may be selected from: 1000 angstroms to 2000 angstroms.
Step S5: depositing a silicon dioxide layer on the HARP oxide layer.
Optionally, the silicon dioxide layer is deposited on the HARP oxide layer by using tetraethoxysiloxane and ozone as reaction sources and by using a plasma enhanced chemical vapor deposition method. The silicon dioxide layer may be formed to a thickness of 2000 to 4000 angstroms.
Referring to fig. 2f, which shows a schematic cross-sectional structure of the device after step S5 is completed, the silicon dioxide layer 174 formed on the surface of the HARP oxide layer 173 in step S5 can fill the gap formed on the surface of the device after step S4 is completed, so that the surface of the device is smooth.
Step S6: and annealing the deposited isolation dielectric layer, and carrying out chemical mechanical polishing on the isolation dielectric layer after the annealing is finished so as to flatten the surface of the isolation dielectric layer.
From the foregoing, it can be seen that the present application provides a NOR FLASH device that includes an isolation gap; depositing a liner layer on the inner surface of the isolation gap; depositing an HDP oxide layer with a first preset thickness in the isolation gap with the formed liner layer by an HDP deposition process; depositing a HARP oxide layer with a second preset thickness on the surface of the device by a HARP deposition process according to the surface appearance of the device on which the HDP oxide layer is formed; on one hand, the situation that high-density plasma exists for too long time can be avoided, and adverse effects on GOI performance of the wafer are prevented; on the other hand, the aspect ratio of the remaining portion of the isolation gap is reduced, and the filling of the isolation gap by the HARP deposition process does not cause the problem of void formation.
The NOR FLASH device isolation dielectric layer shown in fig. 3 is manufactured according to the steps S1 to S5, and referring to fig. 3, a liner layer 171, an HDP oxide layer 172, a HARP oxide layer 173, and a silicon dioxide layer 174 are sequentially deposited in the isolation gap from bottom to top in the vertical direction.
FIG. 4 is a graph showing the breakdown voltage profile of the gate oxide of a NOR FLASH device fabricated by the method provided by the embodiments of the present application; FIG. 5 is a graph showing the bit line bridge voltage distribution of a NOR FLASH device fabricated using the method provided by the embodiments of the present application. As can be seen from fig. 4, the NOR FLASH device isolation dielectric layer preparation method provided in the embodiment of the present application has good oxide layer breakdown voltage distribution characteristics, and a region where the oxide layer breakdown voltage is close to 0 does not occur, that is, the problem of wafer GOI can be avoided by the NOR FLASH device isolation dielectric layer preparation method provided in the embodiment of the present application. As can be seen from fig. 5, the bit line bridge voltage is normal and has no adverse effect.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims (8)

1. A preparation method of an isolation dielectric layer of a NOR FLASH device is characterized in that the preparation method of the isolation dielectric layer of the NNOR FLASH device comprises the following steps:
providing a NOR FLASH device, wherein a plurality of storage unit cells are formed on the NOR FLASH device, and an isolation gap is formed between every two adjacent storage unit cells;
depositing a liner layer on the inner surface of the isolation gap;
depositing and forming an HDP oxide layer with a first preset thickness by an HDP deposition process; the HDP oxide layer covers the isolation gap formed with the liner layer and the memory unit cell;
and depositing and forming a HARP oxide layer with a second preset thickness on the surface of the device by a HARP deposition process according to the surface appearance of the device on which the HDP oxide layer is formed.
2. The method of fabricating an isolation dielectric layer for a NOR FLASH device of claim 1, wherein the step of depositing a liner layer on the inner surface of the isolation gap comprises:
depositing a silicon oxynitride layer on the inner surface of the isolation gap;
depositing a nitride layer on the silicon oxynitride layer; the stacked silicon oxynitride layer and the nitride layer form the pad layer.
3. The method of claim 1, wherein the step of depositing a HDP oxide layer of a first predetermined thickness by a HDP deposition process forms the HDP oxide layer of a first predetermined thickness of 1000 angstroms to 2000 angstroms.
4. The method of claim 1, wherein the step of depositing a HARP oxide layer of a second predetermined thickness on the surface of the device by a HARP deposition process according to the topography of the device surface on which the HDP oxide layer is formed, the second predetermined thickness of the HARP oxide layer being formed by: 1000 angstroms to 2000 angstroms.
5. The method of fabricating an isolation dielectric layer for a NOR FLASH device of claim 1, further comprising, after depositing a HARP oxide layer of a second predetermined thickness:
depositing a silicon dioxide layer on the HARP oxide layer.
6. The method of fabricating an isolation dielectric layer for a NOR FLASH device of claim 5, wherein the silicon dioxide layer has a thickness of 2000 angstroms to 4000 angstroms.
7. The method of fabricating an isolation dielectric layer for a NOR FLASH device of claim 1, wherein the liner layer has a thickness of 200 a to 800 a.
8. A NOR FLASH device isolation dielectric layer fabricated by the method of any of claims 1 to 7.
CN202011540662.XA 2020-12-23 2020-12-23 NOR FLASH device isolation dielectric layer and preparation method thereof Withdrawn CN112670236A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090127648A1 (en) * 2007-11-15 2009-05-21 Neng-Kuo Chen Hybrid Gap-fill Approach for STI Formation
CN111900124A (en) * 2020-08-18 2020-11-06 华虹半导体(无锡)有限公司 Method for forming isolation structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090127648A1 (en) * 2007-11-15 2009-05-21 Neng-Kuo Chen Hybrid Gap-fill Approach for STI Formation
CN111900124A (en) * 2020-08-18 2020-11-06 华虹半导体(无锡)有限公司 Method for forming isolation structure

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Application publication date: 20210416