CN112653451A - Clock data recovery device - Google Patents

Clock data recovery device Download PDF

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Publication number
CN112653451A
CN112653451A CN201910963028.8A CN201910963028A CN112653451A CN 112653451 A CN112653451 A CN 112653451A CN 201910963028 A CN201910963028 A CN 201910963028A CN 112653451 A CN112653451 A CN 112653451A
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Prior art keywords
phase
reference clock
clock signal
signal
data
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CN201910963028.8A
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CN112653451B (en
Inventor
刘曜嘉
陈柏羽
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Realtek Semiconductor Corp
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Realtek Semiconductor Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

The invention discloses a clock data recovery device, which comprises a phase detection circuit, a digital filter, a phase-locked loop, a phase interpolation circuit and an oscillator circuit. The phase detection circuit receives the data signal to sample according to the reference clock signals with different phases to generate a phase detection result. The digital filter accumulates the phase detection result to generate a phase modulation signal. The phase interpolation circuit performs phase adjustment on the source clock signal according to the phase modulation signal to generate an injection clock signal. The oscillator circuit generates a reference clock signal according to the injection clock signal, and the phase of the reference clock signal follows the phase of the injection clock signal.

Description

Clock data recovery device
Technical Field
The present invention relates to clock data recovery technologies, and in particular, to a clock data recovery apparatus.
Background
In high-speed transmission, since digital data is not transmitted simultaneously with a synchronous clock, noise and distortion of the digital data are often caused, and therefore, a clock data recovery circuit is usually required in a transceiver to regenerate a low jitter frequency and recover low-noise data.
The current clock data recovery circuit can be realized by an analog circuit or a digital circuit. However, analog circuits are prone to unlocking when the frequency is momentarily shifted, and noise accumulation is prone to occur in data patterns that have a particular duration without transitions; on the other hand, because the delay time of the digital circuit is long, the digital circuit has the limitations of capability and deteriorated bit error rate when locking frequency deviation, and the linearity and the power consumption are poor. Therefore, there is a drawback that is difficult to overcome in any circuit implementation.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a clock data recovery apparatus to improve the prior art.
An objective of the present invention is to provide a clock data recovery apparatus, which has the advantages of both digital and analog circuits, so as to recover clock data stably and accurately.
The present invention includes a clock data recovery apparatus, one embodiment of which includes: a phase detection circuit, a digital filter, a phase interpolation circuit, and an oscillator circuit. The phase detection circuit is configured to receive a data signal, perform sampling according to a plurality of reference clock signals with different phases, and generate a phase detection result according to the sampling. The digital filter is configured to continuously accumulate the number of times that the reference clock signal is phase-advanced and phase-delayed relative to the data signal in the phase detection result to generate the phase modulation signal. The phase interpolation circuit is configured to perform phase adjustment on the source clock signal according to the phase modulation signal to generate an injection clock signal. The oscillator circuit is configured to generate a reference clock signal from the injection clock signal, and a phase of the reference clock signal follows a phase of the injection clock signal.
The invention comprises a clock data recovery method, which is applied to a clock data recovery device, and one embodiment of the clock data recovery method comprises the following steps: enabling the phase detection circuit to receive a data signal, sampling according to a plurality of reference clock signals with different phases and generating a phase detection result according to the sampling; the digital filter continuously accumulates the times that the reference clock signal is phase lead and phase lag relative to the data signal in the phase detection result generated by the phase detection circuit so as to generate a phase modulation signal; enabling the phase interpolation circuit to perform phase adjustment on the source clock signal according to the phase modulation signal so as to generate an injection clock signal; and causing the oscillator circuit to generate a reference clock signal according to the injection clock signal, and a phase of the reference clock signal is a phase following the injection clock signal.
The features, practical operation and effects of the present invention will be described in detail with reference to the drawings.
Drawings
FIG. 1 is a block diagram of a clock data recovery apparatus according to an embodiment of the present invention;
FIG. 2A is a schematic diagram showing a plurality of data signals, a reference clock signal and sampling results thereof according to an embodiment of the present invention;
FIG. 2B is a block diagram of a phase detection circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram showing a plurality of data signals, a reference clock signal and sampling results thereof according to another embodiment of the present invention;
FIG. 4 is a circuit diagram of an oscillator circuit according to an embodiment of the present invention; and
fig. 5 is a flowchart illustrating a clock data recovery method according to an embodiment of the invention.
Detailed Description
An object of the present invention is to provide a clock data recovery apparatus, which has the advantages of both digital and analog circuits, and not only has the effect of making clock data recovery stable and accurate. In some embodiments, the clock data recovery apparatus of the present disclosure may also provide a mechanism for fast lock recovery.
Refer to fig. 1. Fig. 1 is a block diagram of a clock data recovery apparatus 100 according to an embodiment of the invention. The clock DATA recovery device 100 is configured to receive the DATA signal DATA and to reconstruct information of a clock associated with the DATA signal DATA from the DATA signal DATA.
The clock data recovery apparatus 100 includes a phase detection circuit 110, a digital filter 120, a phase locked loop 130, a phase interpolation circuit 140, and an oscillator circuit 150. Through the feedback mechanism of the above circuits, the clock DATA recovery apparatus 100 can continuously track the phase of the DATA signal DATA and reconstruct the clock carried by the DATA signal DATA.
The structure and operation of each circuit will be described in more detail below.
In one embodiment, the clock data recovery device 100 operates at full rate. In this case, the phase detection circuit 110 is configured to receive the DATA signal DATA, sample the DATA signal DATA by two reference clock signals CLKI, CLKI 'that are 180 degrees apart, and generate the phase detection result PD accordingly, wherein the two reference clock signals CLKI, CLKI' are clocked with the DATA signal DATA.
Refer to fig. 2A. FIG. 2A is a diagram of a plurality of DATA signals D1-D4, reference clock signals CLKI, CLKI' and sampling results SA 1-SA 3, and SB 1-SB 3 of the DATA signal DATA according to an embodiment of the invention.
In the full-rate mode, one period of each of the reference clock signals CLKI, CLKI' corresponds to a transmission time of one data. The sampling results SA 1-SA 3 of the reference clock signal CLKI will indicate the relationship between the positive edge phase and the corresponding data positive edge, such as the positive edges of the data D2, D4 and D6. Further, the sampling results SB 1-SB 3 of the reference clock signal CLKI' further confirm whether the positive edge phase of the reference clock signal CLKI is leading or lagging with respect to the corresponding data positive edge.
The phase detection circuit 110 may sample the DATA signal DATA according to two consecutive positive edges of the reference clock signal CLKI and a positive edge of the reference clock signal CLKI' between the two positive edges to generate three consecutive sampling results, and further generate the phase detection result PD according to a relationship between the three sampling results.
Taking the three consecutive sample results SA1, SB1, and SA2 in fig. 2A as an example, when the two previous sample results SA1, SB1 are the same, such as (001) or (110), it indicates that the positive edge of the data D2 is between the positive edge of the reference clock signal CLKI 'and the positive edge of the delayed reference clock signal CLKI, so that the reference clock signal CLKI' and the delayed reference clock signal CLKI are sampled to the same value. The phase detection result PD indicates that the reference clock signal CLKI is "phase-lagging" with respect to the DATA signal DATA.
When the last two sampling results SB1, SA2 are the same, such as (011) or (100), it indicates that the positive edge of the DATA signal DATA is between the positive edge of the reference clock signal CLKI and the positive edge of the reference clock signal CLKI ', so that the reference clock signal CLKI and the reference clock signal CLKI' are sampled to the same value. The phase detection result PD indicates that the reference clock signal CLKI is "phase advanced" with respect to the DATA signal DATA.
When the three sampling results SA1, SB1, SA2 are the same, such as (111) or (000), it indicates that the DATA signal DATA has not changed in transition state, and the phase relationship between the reference clock signal CLKI and the DATA signal DATA cannot be determined.
In practice, the phase detection circuit 110 may include a plurality of flip-flops and a plurality of logic gates. The flip-flop is used for sampling the DATA signal DATA according to the reference clock signals CLKI and CLKI' to generate a sampling result, and the logic operation gate is used for performing logic operation on the sampling result to generate a logic operation result which can identify phase lead or phase lag and is used as the phase detection result PD.
Fig. 2B is a block diagram of the phase detection circuit 110 according to an embodiment of the invention. The phase detection circuit 110 is adapted to implement the full-rate phase detection described above and includes three flip-flops FF 1-FF 3 and two exclusive-OR gates XOR1 and XOR 2.
The flip-flops FF 1-FF 3 sample according to the reference clock signals CLKI and CLKI', respectively, to generate sampling results, such as the aforementioned sampling results SA1, SB1 and SA 2. The exclusive or gate XOR1 performs a logical operation on the sampling results SA1 and SB1 to generate a logical operation result UP, and the exclusive or gate XOR2 performs a logical operation on the sampling results SB1 and SA2 to generate a logical operation result DN.
When the two sampling results SA1, SB1 are the same, such as (001) or (110), the logical operation result UP of the XOR gate XOR1 is 0, and the logical operation result DN of the XOR gate XOR2 is1, indicating "phase lag". When the last two sampling results SB1, SA2 are the same, e.g., (011) or (100), the logical operation result UP of the XOR gate XOR1 is1, and the logical operation result DN of the XOR gate XOR2 is 0, indicating "phase lead". When the three sampling results SA1, SB1, SA2 are the same, such as (111) or (000), the logical operation results UP and DN of the XOR gates XOR1 and XOR2 are both 1, indicating that they are not recognizable.
Therefore, in practical operation, the phase detection result PD of fig. 1 can be realized by including the logical operation results UP and DN in fig. 2B.
In another embodiment, the clock data recovery apparatus 100 operates at a half rate (half rate). In this case, the phase detection circuit 110 is configured to receive the DATA signal DATA, sample by four reference clock signals CLKI, CLKQ, CLKI ', CLKQ' having a half clock of the DATA signal DATA and sequentially differing by 90 degrees, and generate the phase detection result PD according to the sampling result.
Please refer to fig. 3. FIG. 3 is a diagram of a plurality of DATA signals D1-D8, reference clock signals CLKI, CLKQ, CLKI ', CLKQ' and their sampling results SC 1-SC 6, SD 1-SD 8 of the DATA signal DATA according to another embodiment of the present invention.
In the half-rate mode, one cycle of each of the reference clock signals CLKI, CLKQ, CLKI ', CLKQ' corresponds to a transmission time of two data. The sampling results SC1 to SC6 of the reference clock signals CLKQ and CLKQ' indicate the relationship of the positive edge phase with the corresponding data positive edge. For example, the sampling results SC1 SC3 of the reference clock signal CLKQ will sample the positive edges of the data D2, D4, D6. The sampling results SC4 SC6 of the reference clock signal CLKQ' will sample the positive edges of the data D3, D5, D7.
Furthermore, the sampling results SD 1-SD 8 of the reference clock signals CLKI and CLKI 'further confirm that the positive edge phases of the reference clock signals CLKQ and CLKQ' are ahead or behind with respect to the corresponding positive data edges. For example, the sampling results SD1 SD4 of the reference clock signal CLKI correspond to the data D1, D3, D5 and D7, and the sampling results SD5 SD8 of the reference clock signal CLKI' correspond to the data D2, D4, D6 and D8.
When the result SC1 of the positive edge of the data D2 sampled by the reference clock signal CLKQ coincides with the result SD1 of the positive edge of the reference clock signal CLKI, it indicates that the phase of the positive edge of the reference clock signal CLKQ is "phase-advanced" with respect to the positive edge of the data D2. When the result SC1 of the positive edge of the data D2 sampled by the reference clock signal CLKQ coincides with the result SD5 of the positive edge of the reference clock signal CLKI', it indicates that the phase of the reference clock signal CLKQ is "phase-lagging" with respect to the positive edge of the data D2.
The sampling and detecting method of the four-phase reference clock signal can also be realized by a structure similar to that shown in fig. 2B, which includes a plurality of flip-flops for sampling and logic operation gates for performing state judgment, so as to generate a phase detection result PD represented by a logic operation result. And will not be described in detail herein.
The digital filter 120 is configured to continuously accumulate the phase detection result PD generated by the phase detection circuit 110 to generate the phase modulation signal PA.
In one embodiment, the digital filter 120 may include an integrator to accumulate the number of phase leads and phase lags. Taking the above-mentioned architecture of fig. 2B as an example, the digital filter 120 may accumulate the times of the logic operation results UP and DN being 1 according to the continuous operation of the phase detection circuit 110.
For example, the digital filter 120 may accumulate a specific value when the logic operation result UP is1 and decrement the specific value when the logic operation result DN is1 by setting internal parameters, such as, but not limited to, the gain constant Kp and the integration constant Ki (not shown), so as to output the accumulated result as the phase modulation signal PA.
The phase-locked loop 130 is configured to generate a source clock signal CLKS. In various embodiments, the phase-locked loop 130 may output the source clock signal CLKS having a particular clock according to various clock and phase synchronization techniques implemented using feedback control principles. The phase locked loop 130 of the present invention is not limited to a particular architecture.
The phase interpolation circuit 140 is configured to phase adjust the source clock signal CLKS according to the phase modulation signal PA to generate the injection clock signal CLKJ. Since the phase modulation signal PA is generated according to the phase detection result PD, the phase interpolation circuit 140 actually adjusts the phase of the source clock signal CLKS according to the phase detection result PD.
When the phase detection result PD indicates "phase lag", the phase modulation signal PA controls the phase interpolation circuit 140 to adjust the phase of the source clock signal CLKS forward to generate the injection clock signal CLKJ. When the phase detection result PD indicates "phase lead", the phase modulation signal PA controls the phase interpolation circuit 140 to adjust the phase of the source clock signal CLKS backward to generate the injection clock signal CLKJ.
In one embodiment, the source clock signal CLKS generated by the PLL 130 is a single phase, and the phase modulation signal PA is used to interpolate an injection clock signal CLKJ having four phases sequentially shifted by 90 degrees, wherein the four phases are simultaneously adjusted according to the phase modulation signal PA.
The oscillator circuit 150 is configured to generate a reference clock signal, such as reference clock signals CLKI, CLKI ', CLKQ', based on the injection clock signal CLKJ.
Reference is also made to fig. 4. Fig. 4 is a circuit diagram of an oscillator circuit 150 according to an embodiment of the invention.
In one embodiment, the oscillator circuit 150 includes an injection stage STJ, an oscillation stage SRI, and a bridge stage SCR that bridges the injection stage STJ and the oscillation stage SRI. The injection stage STJ includes a differential pair DP1, DP2, the bridge stage includes a differential pair DP3, DP4, and the oscillator stage SRI includes a differential pair DP5, DP 6.
The input terminal I11 of the differential pair DP1, the input terminal I21 of the differential pair DP2, the input terminal I12 of the differential pair DP1, and the input terminal I22 of the differential pair DP2 of the injection stage STJ receive four-phase injection clock signals CLKJ (respectively denoted by 0, 90, 180, 270 in fig. 3) sequentially different by 90 degrees.
Further, the output O11 of the differential pair DP1, the output O21 of the differential pair DP2, the output O12 of the differential pair DP1 and the output O22 of the differential pair DP2 of the injection circuit stage STJ are electrically coupled to the oscillation circuit stage SRI and the cross-over circuit stage SCR, so as to sequentially generate four reference clock signals CLKI, CLKQ, CLKI ', CLKQ' that differ by 90 degrees and are stable and not easily interfered by oscillation. Wherein the phase of the reference clock signals CLKI, CLKQ, CLKI ', CLKQ' follows the phase of the injection clock signal CLKJ.
The oscillator circuit 150 can selectively provide the reference clock signals CLKI, CLKI ' to the phase detection circuit 110 for sampling in the manner of fig. 2A in the full-rate mode, or provide the reference clock signals CLKI, CLKQ, CLKI ', CLKQ ' to the phase detection circuit 110 for sampling in the manner of fig. 3 in the half-rate mode.
In one embodiment, the oscillator stage SRI of the oscillator circuit 150 may operate according to three current sources IS1, IS2, IS 3. The current source IS1 IS operated continuously, and the current sources IS2 and IS3 are operated according to the control of the phase detection result PD, so as to provide a mechanism for rapidly adjusting the phase of the reference clock signal.
For example, the current source IS2 IS turned off only when the phase detection result PD indicates "phase lead" to lower the frequency of the reference clock signal, thereby phase-shifting, and remaining on otherwise. The current source IS3 IS turned on only when the phase detection result PD indicates "phase lag", so as to increase the frequency of the reference clock signal, thereby advancing the phase, and remaining turned off in other situations. In the mechanism for adjusting the phase of the reference clock signal, the information corresponding to the phase detection result PD does not need to be transferred through the digital filter 120 and the phase interpolation circuit 140, so that the response delay of the clock data recovery apparatus 100 can be greatly reduced, and the frequency deviation can be rapidly reduced when the frequency deviation is large.
Such a design provides a fast adjustment mechanism when the DATA signal DATA is transmitted by a spread spectrum technique through a carrier wave such as a triangular wave, and has a fast state change.
Therefore, the clock data recovery device of the invention not only can save area and increase controllability through the digital filter, but also can generate a source clock signal through the phase-locked loop to avoid the unlocking of analog switching or the noise accumulation caused when the input data type is not transited. Furthermore, by injecting the phase of the phase interpolation circuit to the oscillator circuit, the oscillator circuit can approximate the analog continuous change modulation phase, the error code is not generated when the frequency is locked due to the quality influence of the phase interpolation circuit design, and the optimal linearity and power consumption performance can be maintained.
It should be noted that the architecture of each circuit described above is merely an example. In other embodiments, circuits with other architectures may be used to achieve the same effect, so as to achieve the purpose of providing stable and accurate clock data recovery.
Refer to fig. 5. Fig. 5 is a flowchart of a clock data recovery method 500 according to an embodiment of the invention.
In addition to the aforementioned devices, the present invention also discloses a clock data recovery method 500, which is applied in, for example, but not limited to, the clock data recovery device 100 of fig. 1. One embodiment of a clock data recovery method 500 is shown in FIG. 5, comprising the following steps:
s510: the phase detection circuit 110 is enabled to receive the DATA signal DATA, perform sampling according to a plurality of reference clock signals with different phases, and generate a phase detection result PD accordingly.
S520: the digital filter 120 continuously accumulates the phase leading and phase lagging times of the reference clock signal with respect to the DATA signal DATA in the phase detection result PD generated by the phase detection circuit 110 to generate the phase modulation signal PA.
S530: the phase interpolation circuit 140 performs phase adjustment on the source clock signal CLKS according to the phase modulation signal PA to generate the injection clock signal CLKJ.
S540: the oscillator circuit 150 is caused to generate a reference clock signal based on the injection clock signal CLKJ, and the phase of the reference clock signal follows the phase of the injection clock signal CLKJ.
S550: the oscillator circuit 150 is caused to adjust the phase of the reference clock signal directly according to the phase detection result PD. The oscillator circuit 150 will adjust the phase of the reference clock signal back when the phase detection result PD indicates that the phase of the reference clock signal is leading relative to the DATA signal DATA, and adjust the phase of the reference clock signal front when the phase detection result PD indicates that the phase of the reference clock signal is lagging relative to the DATA signal DATA
In summary, the clock data recovery apparatus and method of the present invention can have the advantages of both digital and analog circuits, not only achieve the effect of stable and accurate clock data recovery, but also provide a mechanism for fast lock recovery.
Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.
[ notation ] to show
100 clock data recovery device
110 phase detection circuit
120 digital filter
130 phase locked loop
140 phase interpolation circuit
150 oscillator circuit
500 clock data recovery method
S510 to S550
CLKI, CLKQ, CLKI ', CLKQ' reference clock signals
CLKJ injection clock signal
CLKS Source clock Signal
D1-D8 data
DATA DATA signal
DN, UP logical operation result
DP 1-DP 6 differential pair
I11, I12, I21 and I22 input terminals
Output ends of O11, O12, O21 and O22
FF 1-FF 3 flip-flop
PA phase modulation signal
PD phase detection result
SA 1-SA 3, SB 1-SB 3, SC 1-SC 6 and SD 1-SD 8 sampling results
SCR cross-over circuit stage
SRI oscillating circuit stage
STJ injection circuit stage
XOR1, XOR2 exclusive or gate.

Claims (10)

1. A clock data recovery apparatus, comprising:
a phase detection circuit configured to receive a data signal, perform sampling according to a plurality of reference clock signals of different phases, and accordingly generate a phase detection result;
a digital filter configured to accumulate the phase leading and phase lagging times of the reference clock signals relative to the data signal in the phase detection result to generate a phase modulation signal;
a phase interpolation circuit configured to perform phase adjustment on a source clock signal according to the phase modulation signal to generate an injection clock signal; and
an oscillator circuit configured to generate the reference clock signals according to the injection clock signal, and the phases of the reference clock signals follow the phase of the injection clock signal.
2. The clock data recovery apparatus of claim 1, wherein the oscillator circuit is further configured to adjust the phases of the reference clock signals directly according to the phase detection result, to adjust the phases of the reference clock signals back when the phase detection result indicates that the reference clock signals are phase-advanced with respect to the data signal, and to adjust the phases of the reference clock signals front when the phase detection result indicates that the reference clock signals are phase-retarded with respect to the data signal.
3. The clock data recovery apparatus of claim 1, wherein the phase detection circuit comprises a plurality of flip-flops and a plurality of logic operation gates, the flip-flops sample the data signal according to the reference clock signals to generate a plurality of sampling results, and the logic operation gates perform logic operation according to the sampling results to generate the phase detection result.
4. The clock data recovery apparatus of claim 1, further comprising a phase locked loop configured to generate the source clock signal;
wherein the phase locked loop is configured to generate the source clock signal clocked in common with the data signal, and the oscillator circuit is configured to generate the two reference clock signals 180 degrees apart from each other according to the injected clock signal.
5. The clock data recovery apparatus of claim 4, wherein the reference clock signals comprise a first reference clock signal and a second reference clock signal that are sequentially 180 degrees apart, such that the phase detection circuit generates three sampling results by sequentially sampling the data signal according to the first reference clock signal and the second reference clock signal;
when the first two sampling results in the three sampling results are the same, displaying that the first reference clock signal is behind the phase of the data signal;
and when the last two sampling results in the three sampling results are the same, displaying that the first reference clock signal leads the phase of the data signal.
6. The clock data recovery apparatus of claim 1, further comprising a phase locked loop configured to generate the source clock signal;
wherein the phase locked loop is configured to generate the source clock signal having one-half the clock of the data signal, and the oscillator circuit is configured to generate four reference clock signals sequentially 90 degrees apart according to the injected clock signal.
7. The clock data recovery apparatus of claim 6, wherein the four reference clock signals comprise a first reference clock signal, a second reference clock signal, a third reference clock signal and a fourth reference clock signal sequentially shifted by 90 degrees, such that the phase detection circuit samples the data signal to generate a first sampling result, a second sampling result, a third sampling result and a fourth sampling result;
when the first sampling result is the same as the fourth sampling result or the third sampling result is the same as the second sampling result, displaying that the first reference clock signal or the third reference clock signal is phase-advanced relative to the data signal;
and when the first sampling result is the same as the second sampling result or the third sampling result is the same as the fourth sampling result, displaying that the first reference clock signal or the third reference clock signal is phase-lagging relative to the data signal.
8. The clock data recovery apparatus of claim 1, wherein the oscillator circuit comprises an injection circuit stage, an oscillation circuit stage, and a bridge circuit stage for bridging the injection circuit stage and the oscillation circuit stage, the injection circuit stage configured to receive the injection clock signal, to oscillate to the oscillation circuit stage through the bridge circuit stage, and to further output the reference clock signals from the injection circuit stage.
9. The clock data recovery apparatus of claim 1, wherein the oscillator circuit operates according to a first current source, a second current source and a third current source, wherein the first current source is continuously operated, the second current source is turned off only when the phase detection result indicates that the reference clock signals are phase-advanced with respect to the data signal, and the third current source is turned on only when the phase detection result indicates that the reference clock signals are phase-delayed with respect to the data signal.
10. A clock data recovery method is applied to a clock data recovery device and comprises the following steps:
enabling a phase detection circuit to receive a data signal, sampling according to a plurality of reference clock signals with different phases, and generating a phase detection result;
a digital filter continuously accumulates the times of leading and lagging phases of the reference clock signals relative to the data signal in the phase detection result generated by the phase detection circuit so as to generate a phase modulation signal;
enabling a phase interpolation circuit to perform phase adjustment on a source clock signal according to the phase modulation signal so as to generate an injection clock signal; and
an oscillator circuit generates the reference clock signals according to the injection clock signal, and the phase of the reference clock signals follows the phase of the injection clock signal.
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