CN112653434B - Time sequence controlled low-power consumption common mode feedback pre-amplification circuit and comparator - Google Patents
Time sequence controlled low-power consumption common mode feedback pre-amplification circuit and comparator Download PDFInfo
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Abstract
The application discloses a time sequence control low-power consumption common mode feedback pre-amplification circuit and a comparator, and belongs to the technical field of integrated circuits. The method mainly comprises the following steps: the application provides a simple common mode feedback circuit with a time sequence, which effectively reduces common mode gain.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a time sequence controlled low-power consumption common mode feedback pre-amplification circuit and a comparator.
Background
In integrated circuits, a combined structure of pre-amplification circuits and latches is often used in ADC (digital to analog conversion) comparator structures.
In the prior art, the pre-amplification circuit of an integrated circuit is a pseudo-differential amplifier formed with two CMOS inverters. In the pseudo-differential amplifier, when the common mode voltage input by the inverting input terminal and the non-inverting input terminal of the pseudo-differential amplifier is close to the jump voltage, the NMOS transistor and the PMOS transistor have the same amplifying performance. The pseudo-differential amplifier operates at its voltage trip point when the inverting input is shorted to the non-inverting input. However, since the pseudo-differential amplifier generates a very high common mode gain, the high common mode gain has a certain effect on the value of the signal to noise ratio in the comparator.
Disclosure of Invention
Aiming at the problem that the high common mode gain generated by a preamplifier in a pre-amplifying circuit of a comparator structure in the prior art can have a certain influence on the value of the signal to noise ratio in the comparator, the application mainly provides a time sequence controlled low-power consumption common mode feedback pre-amplifying circuit and a comparator.
In order to achieve the above purpose, the application adopts a technical scheme that: provided is a timing control low power consumption common mode feedback pre-amplification circuit, comprising: the common mode feedback unit comprises a first transistor, a second transistor and a capacitor, the clock control unit comprises a first clock control switch, a second clock control switch, a third clock control switch, a fourth clock control switch, a fifth clock control switch, a sixth clock control switch, a seventh clock control switch, an eighth clock control switch and a ninth clock control switch, wherein the inverting input end of the preamplifier is interconnected with the in-phase output end of the preamplifier through the first clock control switch, the in-phase output end of the preamplifier is interconnected with the common mode voltage output end of the common mode feedback unit through the second clock control switch, the common mode voltage output end of the common mode feedback unit is interconnected with the inverting output end of the preamplifier through the fourth clock control switch, the common mode voltage output end of the common mode feedback unit is interconnected with the capacitor through the third clock control switch, the in-phase input end of the preamplifier is interconnected with the inverting output end of the preamplifier through the fifth clock control switch, the output end of the common mode feedback unit is interconnected with the common mode voltage output end of the common mode feedback unit through the seventh clock control switch and the output end of the preamplifier through the second clock control switch, and the common mode voltage feedback unit is interconnected with the output end of the common mode voltage of the output of the common mode feedback unit through the fourth clock control transistor.
The application adopts another technical scheme that: provided is a comparator of a low power consumption common mode feedback pre-amplifying circuit based on time sequence control, comprising: the low-power consumption common mode feedback pre-amplification circuit based on the time sequence control of the pre-amplifier, the clock control unit and the common mode feedback unit in the scheme I, and the latch, wherein the non-inverting output end of the pre-amplifier in the time sequence control low-power consumption common mode feedback pre-amplification circuit is connected with the non-inverting input end of the latch, and the inverting output end of the pre-amplifier in the time sequence control low-power consumption common mode feedback pre-amplification circuit is connected with the inverting input end of the latch.
The technical scheme of the application has the following beneficial effects: the application designs a time sequence controlled low-power consumption common mode feedback pre-amplification circuit and a comparator. By providing a simple common mode feedback circuit with timing, the common mode gain is effectively reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of one embodiment of a time-series controlled low power consumption common mode feedback pre-amplifier circuit of the present application;
FIG. 2 is a schematic diagram of a pseudo-differential amplifier in one embodiment of a time-series controlled low power consumption common mode feedback pre-amplification circuit of the present application;
FIG. 3 is a schematic diagram of a preamplifier in one embodiment of a time-series controlled low power consumption common mode feedback preamplifier circuit of the application;
FIG. 4 is a schematic diagram of a preamplifier-based clock control unit in one embodiment of a time-series controlled low power consumption common mode feedback pre-amplifier circuit according to the present application;
FIG. 5 is an overall schematic diagram of a pre-amplifier circuit in one embodiment of a time-series controlled low power consumption common mode feedback pre-amplifier circuit of the present application;
FIG. 6 is a schematic diagram of the variation of clock signals at each stage of operation in the time-series controlled low power consumption common mode feedback pre-amplification circuit of the present application;
FIG. 7 is a schematic diagram of a timing-controlled low-power consumption common-mode feedback pre-amplifier circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a comparator of a low power consumption common mode feedback pre-amp circuit based on timing control of the present application;
The reference numerals in the drawings are as follows: m1-first transistor, M2-second transistor, M3-third transistor, M4-fourth transistor, M5-fifth transistor, M6-sixth transistor, C1-first clock control switch, C2-second clock control switch, C3-third clock control switch, C4-fourth clock control switch, C5-fifth clock control switch, C6-sixth clock control switch, C7-seventh clock control switch, C8-eighth clock control switch, C9-ninth clock control switch, vin, non-inverting input of the p 1-pseudo-differential amplifier, vout, inverting output of the n 1-pseudo-differential amplifier, vin, inverting input of the n 1-pseudo-differential amplifier, vout, p 1-pseudo-differential amplifier's in-phase output, vin, p-preamplifier's in-phase input, vout, n-preamplifier's inverting output, vin, n-is preamplifier's inverting input, vout, p-preamplifier's in-phase output, vout, cm-common mode feedback unit's common mode output voltage, D1-first clock signal to control first clock control switch, D2-second clock signal to control second clock control switch, D3-third clock signal to control sixth clock control switch, CLK-input Latch's clock signal, D4-short reset signal to control reset switch, latch-Latch.
Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.
Detailed Description
The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings so that the advantages and features of the present application can be more easily understood by those skilled in the art, thereby making clear and defining the scope of the present application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In integrated circuits, a combined structure of pre-amplification circuits and latches is often used in ADC (digital to analog conversion) comparator structures. In the prior art, the pre-amplification circuit of an integrated circuit is a pseudo-differential amplifier formed with two CMOS inverters. In the pseudo-differential amplifier, when the common mode voltage input by the inverting input terminal and the non-inverting input terminal of the pseudo-differential amplifier is close to the jump voltage, the crystals have the same amplifying performance. The pseudo-differential amplifier operates at its voltage trip point when the inverting input is shorted to the non-inverting input. However, since the pseudo-differential amplifier generates a very high common mode gain, the high common mode gain has a certain effect on the value of the signal to noise ratio in the comparator.
The application is characterized in that: a simple common mode feedback circuit with time sequence is provided, and the common mode gain is effectively reduced.
The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram illustrating one embodiment of a time-series controlled low power consumption common mode feedback pre-amp circuit of the present application.
In a specific embodiment of the application, the low-power consumption common-mode feedback pre-amplifying circuit with time sequence control comprises a pre-amplifier, a clock control unit and a common-mode feedback unit, wherein the common-mode feedback unit comprises a first resistor and a second resistor, the pre-amplifier comprises a third transistor, a fourth transistor and a fifth transistor, an inverting input end of the pre-amplifier is respectively connected with a grid electrode of the third transistor and a grid electrode of the fifth transistor, an in-phase output end of the pre-amplifier is respectively connected with a drain electrode of the third transistor and a drain electrode of the fifth transistor, a drain electrode of the third transistor is respectively connected with a common-mode voltage output end of the common-mode feedback unit through the first resistor, a drain electrode of the fourth transistor is respectively connected with a drain electrode of the fourth transistor and a drain electrode of the sixth transistor through a common-mode voltage output end of the second resistor, an inverting output end of the pre-amplifier is respectively connected with a grid electrode of the fourth transistor and a grid electrode of the sixth transistor, an in-phase input end of the pre-amplifier is respectively connected with a common-mode voltage output end of the fourth transistor, a drain electrode of the fourth transistor is respectively connected with a drain electrode of the fourth transistor, a common-mode voltage output end of the fourth transistor is respectively connected with a drain electrode of the common-mode voltage output end of the fourth transistor is connected with a drain electrode of the common-mode feedback unit, and a common-mode voltage of the common-mode output unit is respectively.
In one embodiment of the present application, it is preferable to use PMOS transistors for the first transistors and NMOS transistors of a complementary type to the first transistors for the second transistors. The specific structure of the pseudo-differential amplifier formed by two inverters is shown in fig. 2, wherein Vin, p1 in the figure is the non-inverting input end of the pseudo-differential amplifier, vout, n1 is the inverting output end of the pseudo-differential amplifier, vin, n1 is the inverting input end of the pseudo-differential amplifier, vout, p1 is the non-inverting output end, M3 is the third transistor, M4 is the fourth transistor, M5 is the fifth transistor, and M6 is the sixth transistor. The low-power consumption common mode feedback pre-amplification circuit controlled by the time sequence is based on the pseudo-differential amplifier structure, and related circuit components are added, so that the pre-amplifier is realized.
Adding a common mode feedback unit based on a pseudo-differential amplifier structure to form a pre-amplifier, comprising: the first transistor, the second transistor, the first resistor, the second resistor and the capacitor. The added two resistors can detect common-mode voltage, the common-mode voltage is used as bias voltage of the first transistor and the second transistor and is input from grid electrodes of the first transistor and the second transistor respectively, the common-mode voltage controls the magnitude of current generated by the first transistor and the second transistor, and the generated current controls the amplification factor of the inverter. The first transistor and the second transistor are sized to operate in a linear region such that the drive voltage in the input transistor is minimized and the amount of suppression of the common mode voltage is moderate.
The specific structure diagram of the preamplifier in the time sequence controlled low power consumption common mode feedback pre-amplifying circuit is shown in fig. 3, wherein Vin, p is the non-inverting input end of the preamplifier, vout, n is the inverting output end of the preamplifier, vin, n is the inverting input end of the preamplifier, vout, p is the non-inverting output end of the preamplifier, vout, cm is the common mode output voltage of the common mode feedback unit, M1 is the first transistor, M2 is the second transistor, M3 is the third transistor, M4 is the fourth transistor, M5 is the fifth transistor, M6 is the sixth transistor, PMOS transistors are used for the first transistor, the third transistor and the fifth transistor, and NMOS transistors of the complementary type with the first transistor are used for the second transistor, the fourth transistor and the sixth transistor. Since the complexity and power consumption of the circuit are increased if the common mode feedback circuit is directly used, the common mode feedback unit is added in the preamplifier to realize the effect of common mode feedback. When the common-mode output voltage in the front-end amplifier is increased, the amplifying capability of the PMOS tube is weakened, and the common-mode voltage is also reduced; therefore, a common mode feedback unit is added on the basis of the pseudo-differential amplifier to form a pre-amplifying unit in the low-power consumption common mode feedback pre-amplifying circuit controlled by the time sequence, so that moderate voltage gain reduction is realized.
In a specific embodiment of the application, in the time sequence controlled low-power consumption common mode feedback pre-amplification circuit, the common mode feedback unit further comprises a first transistor, a second transistor and a capacitor, the clock control unit comprises a first clock control switch, a second clock control switch, a third clock control switch, a fourth clock control switch, a fifth clock control switch, a sixth clock control switch, a seventh clock control switch, an eighth clock control switch and a ninth clock control switch, wherein an inverting input end of the preamplifier is connected with an in-phase output end of the preamplifier through the first clock control switch, an in-phase output end of the preamplifier is connected with a common mode voltage output end of the common mode feedback unit through the second clock control switch, the common mode voltage output end of the common mode feedback unit is connected with an inverting output end of the preamplifier through the fourth clock control switch, the in-phase input end of the preamplifier is connected with an inverting output end of the preamplifier through the fifth clock control switch, and the common mode voltage output end of the common mode feedback unit is connected with the output end of the preamplifier through the fourth clock control switch, and the common mode voltage output end of the common mode feedback unit is connected with the output end of the common mode voltage feedback unit through the eighth clock control transistor through the fourth clock control switch, and the common mode voltage feedback unit is connected with the output end of the common mode voltage of the common mode feedback unit through the eighth transistor.
In a specific example of the present application, preferably, based on the foregoing pre-amplifier, the low power consumption common mode feedback pre-amplifying circuit of the present application adds a relevant clock control switch in the pre-amplifying unit, where the specific adding position is as shown in fig. 4, where M1 is a first transistor, M2 is a second transistor, M3 is a third transistor, M4 is a fourth transistor, M5 is a fifth transistor, M6 is a sixth transistor, PMOS transistors are used for the first transistor, the third transistor and the fifth transistor, and NMOS transistors of a complementary type to the first transistor are used for the second transistor, the fourth transistor and the sixth transistor; c1 is a first clock control switch, C2 is a second clock control switch, C3 is a third clock control switch, C4 is a fourth clock control switch, C5 is a fifth clock control switch, C6 is a sixth clock control switch, C7 is a seventh clock control switch, C8 is an eighth clock control switch, C9 is a ninth clock control switch, vin, p is a non-inverting input of the preamplifier, vout, n is an inverting output of the preamplifier, vin, n is an inverting input of the preamplifier, vout, p is a non-inverting output of the preamplifier. The related clock control switch added in the pre-amplifier of the time sequence controlled low-power consumption common mode feedback pre-amplification circuit effectively reduces the common mode gain of the pre-amplification circuit.
In a specific embodiment of the present application, the timing controlled low power consumption common mode feedback pre-amplification circuit of the present application further comprises: the first clock signal controls the opening and closing of the first clock control switch, the third clock control switch and the fifth clock control switch; the second clock signal controls the opening and closing of the second clock control switch and the fourth clock control switch; the third clock signal controls the opening and closing of the sixth clock control switch and the eighth clock control switch; the fourth clock signal controls the opening and closing of the seventh clock control switch and the ninth clock control switch.
In a specific embodiment of the present application, the timing controlled low power consumption common mode feedback pre-amplification circuit of the present application further comprises: the fourth clock signal is an inverted clock signal of the third clock signal.
In this embodiment, in the time sequence controlled low power consumption common mode feedback pre-amplifying circuit of the present application, the clock control switches added in the pre-amplifying unit are controlled by different clock signals respectively. The switching of the first clock control switch, the third clock control switch and the fifth clock control switch is controlled by a first clock signal, the switching of the second clock control switch and the fourth clock control switch is controlled by a second clock signal, the switching of the sixth clock control switch and the eighth clock control switch is controlled by a third clock signal, and the switching of the seventh clock control switch and the ninth clock control switch is controlled by a fourth clock signal; and the fourth clock signal is an inverted clock signal of the third clock signal. For each clock control switch, the operation stage of the low-power consumption common mode feedback pre-amplification circuit controlled by the time sequence is started in different stages respectively, so that the power consumption of the pre-amplification circuit is reduced and/or the common mode gain of the pre-amplification circuit is reduced.
In a specific embodiment of the present application, the timing controlled low power consumption common mode feedback pre-amplification circuit of the present application further comprises: if the seventh clock control switch and the ninth clock control switch controlled by the fourth clock signal are both closed, the working states of the first transistor and the second transistor are switched to be closed.
In one embodiment of the present invention, preferably, when the fourth clock signal is turned on at a high level, the seventh clock control switch and the ninth clock control switch controlled by the fourth clock signal are turned on, the gate of the first transistor is connected to an external power source, that is, the gate of the first transistor is connected to a high potential, and the gate of the second transistor is grounded; at this time, the working states of the first transistor and the second transistor are switched to be closed, that is, the pre-amplification circuit does not work, so that the power consumption of the pre-amplification circuit is reduced.
In a specific embodiment of the present application, the timing controlled low power consumption common mode feedback pre-amplification circuit of the present application further comprises: the in-phase output end of the preamplifier is connected with the anti-phase output end of the preamplifier through a reset switch, wherein the on-off of the reset switch is controlled through a short reset pulse signal.
In a specific embodiment of the present application, preferably, the non-inverting output terminal of the preamplifier of the time-sequence controlled low-power consumption common mode feedback pre-amplifying circuit of the present application is connected to the inverting output terminal of the preamplifier through a reset switch. The connection between the preamplifier and the latch is shown in fig. 5, wherein M1 is a first transistor, M2 is a second transistor, M3 is a third transistor, M4 is a fourth transistor, M5 is a fifth transistor, M6 is a sixth transistor, PMOS transistors are used for the first transistor, the third transistor and the fifth transistor, and NMOS transistors of the complementary type to the first transistor are used for the second transistor, the fourth transistor and the sixth transistor; c1 is a first clock control switch, C2 is a second clock control switch, C3 is a third clock control switch, C4 is a fourth clock control switch, C5 is a fifth clock control switch, C6 is a sixth clock control switch, C7 is a seventh clock control switch, C8 is an eighth clock control switch, C9 is a ninth clock control switch, C10 is a reset switch, vin, p is a non-inverting input of the preamplifier, vout, n is an inverting output of the preamplifier, vin, n is an inverting input of the preamplifier, vout, p is a non-inverting output of the preamplifier.
In a specific embodiment of the present application, the timing controlled low power consumption common mode feedback pre-amplification circuit of the present application further comprises: and if a reset switch controlled by the short reset pulse signal is closed, setting and clearing the signal at the in-phase output end of the preamplifier and the signal at the anti-phase output end of the preamplifier.
In one embodiment of the present application, preferably, the time-series controlled low-power consumption common mode feedback pre-amplifying circuit of the present application has three operation stages of a pre-amplifying stage, a low noise comparing stage and a set zero clearing stage, and fig. 6 shows a variation of each clock signal of each operation stage of the time-series controlled low-power consumption common mode feedback pre-amplifying circuit of the present application, where D1 is a first clock signal controlling a first clock control switch, D2 is a second clock signal controlling a second clock control switch, D3 is a third clock signal controlling a sixth clock control switch, D4 is a short reset signal controlling a reset switch, and CLK is a clock signal of an input latch. As shown in fig. 6, after each pre-amplification stage, a short reset pulse signal is then generated, resetting the signal at the non-inverting output of the pre-amplifier with the signal at the inverting output, which allows the differential signal to start near 0 and accelerates the establishment of an over-0.
In a specific embodiment of the present application, the timing controlled low power consumption common mode feedback pre-amplification circuit of the present application further comprises: and if the working state of the time sequence controlled low-power consumption common mode feedback pre-amplification circuit is a reset state, closing a first clock control switch, a third clock control switch and a fifth clock control switch controlled by a first clock signal and a second clock control switch and a fourth clock control switch controlled by a second clock signal.
In one embodiment of the present invention, preferably, in the set zero stage shown in fig. 6, the first clock signal and the second clock signal are both turned on at high potential, and the first clock control switch, the third clock control switch and the fifth clock control switch controlled by the first clock signal and the second clock control switch and the fourth clock control switch controlled by the second clock signal are all turned on; at this time, the inverting input end of the pre-amplifier is short-circuited with the non-inverting output end of the pre-amplifier, the inverting output end of the pre-amplifier is short-circuited with the non-inverting input end of the pre-amplifier, and the inverting output end of the pre-amplifier is short-circuited with the non-inverting output end of the pre-amplifier, so that the bias voltage is at the jump point, and the time sequence controlled low-power consumption common mode feedback pre-amplifier circuit obtains the maximum common mode gain. This trip point voltage, like a capacitor, can be used as a common mode input voltage in the next comparison stage, so that the common mode point of the time-controlled low-power consumption common mode feedback pre-amplification circuit is clamped to the trip point.
FIG. 7 is a schematic diagram illustrating one embodiment of a comparator of the time-controlled low power consumption common mode feedback pre-amp circuit of the present application.
In one embodiment of the present application, the low-power consumption common-mode feedback pre-amplification circuit based on the timing control of the present application is preferably connected to a latch, so as to realize a comparator structure of the low-power consumption common-mode feedback pre-amplification circuit with the timing control. The connection mode between the low-power consumption common mode feedback pre-amplification circuit controlled by the time sequence and the latch is shown in fig. 8, wherein the non-inverting output end of the pre-amplifier in the low-power consumption common mode feedback pre-amplification circuit controlled by the time sequence is connected with the non-inverting input end of the latch, and the inverting output end of the pre-amplifier is connected with the inverting input end of the latch. In the pre-amplification circuit of the comparator shown in fig. 8, M1 is a first transistor, M2 is a second transistor, M3 is a third transistor, M4 is a fourth transistor, M5 is a fifth transistor, M6 is a sixth transistor, PMOS transistors are used for the first transistor, the third transistor, and the fifth transistor, and NMOS transistors of a complementary type to the first transistor are used for the second transistor, the fourth transistor, and the sixth transistor; c1 is a first clock control switch, C2 is a second clock control switch, C3 is a third clock control switch, C4 is a fourth clock control switch, C5 is a fifth clock control switch, C6 is a sixth clock control switch, C7 is a seventh clock control switch, C8 is an eighth clock control switch, C9 is a ninth clock control switch, C10 is a reset switch, vin, p is a non-inverting input of the preamplifier, vout, n is an inverting output of the preamplifier, vin, n is an inverting input of the preamplifier, vout, p is a non-inverting output of the preamplifier. In the latch of the comparator shown in fig. 8, CLK is a clock signal input to the latch, and the operation state of each operation stage of the low-power consumption common mode feedback pre-amplification circuit of the timing control is as shown in fig. 6, and is turned on at a high potential in the low noise comparison stage.
The application designs a time sequence controlled low-power consumption common mode feedback pre-amplification circuit and a comparator. By providing a simple common mode feedback circuit with timing, the common mode gain is effectively reduced and the power consumption is reduced.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The foregoing description is only illustrative of the present application and is not intended to limit the scope of the application, and all equivalent structural changes made by the present application and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present application.
Claims (10)
1. The utility model provides a low-power consumption common mode feedback pre-amplification circuit of time sequence control which characterized in that includes: the preamplifier, the clock control unit and the common mode feedback unit, the common mode feedback unit comprises a first transistor, a second transistor and a capacitor, the clock control unit comprises a first clock control switch, a second clock control switch, a third clock control switch, a fourth clock control switch, a fifth clock control switch, a sixth clock control switch, a seventh clock control switch, an eighth clock control switch, a ninth clock control switch,
The inverting input end of the preamplifier is interconnected with the inverting output end of the preamplifier through the first clock control switch, the inverting output end of the preamplifier is interconnected with the common-mode voltage output end of the common-mode feedback unit through the second clock control switch, the common-mode voltage output end of the common-mode feedback unit is interconnected with the inverting output end of the preamplifier through the fourth clock control switch, the common-mode voltage output end of the common-mode feedback unit is interconnected with the capacitor through the third clock control switch, the non-inverting input end of the preamplifier is interconnected with the inverting output end of the preamplifier through the fifth clock control switch, the common-mode voltage output end of the common-mode feedback unit is interconnected with the grid electrode of the first transistor through the sixth clock control switch, the common-mode voltage output end of the common-mode feedback unit is interconnected with the grid electrode of the second transistor through the eighth clock control switch, and the grid electrode of the common-mode feedback unit is interconnected with the grid electrode of the second transistor through the ninth clock control switch.
2. The timing controlled low power consumption common mode feedback pre-amplifier circuit of claim 1, wherein a first clock signal controls the opening and closing of the first, third and fifth clock control switches;
A second clock signal controls the opening and closing of the second clock control switch and the fourth clock control switch;
a third clock signal controls the opening and closing of the sixth clock control switch and the eighth clock control switch;
and the fourth clock signal controls the opening and closing of the seventh clock control switch and the ninth clock control switch.
3. The timing controlled low power consumption common mode feedback pre-amp circuit as set forth in claim 2, wherein said fourth clock signal is an inverted clock signal of said third clock signal.
4. The timing controlled low power consumption common mode feedback pre-amplifier circuit as set out in claim 1, wherein said common mode feedback unit further comprises a first resistor and a second resistor, said pre-amplifier comprising a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, wherein,
The inverting input terminal of the preamplifier is respectively connected with the grid electrode of the third transistor and the grid electrode of the fifth transistor, the non-inverting output terminal of the preamplifier is respectively connected with the drain electrode of the third transistor and the drain electrode of the fifth transistor, the drain electrode of the third transistor and the drain electrode of the fifth transistor are respectively connected with the common-mode voltage output terminal of the common-mode feedback unit through a first resistor, the drain electrode of the fourth transistor and the drain electrode of the sixth transistor are respectively connected with the common-mode voltage output terminal of the common-mode feedback unit through a second resistor, the inverting output terminal of the preamplifier is respectively connected with the drain electrode of the fourth transistor and the drain electrode of the sixth transistor, the non-inverting input terminal of the preamplifier is respectively connected with the grid electrode of the fourth transistor and the grid electrode of the sixth transistor, the source electrode of the first transistor is connected with an external power supply, the drain electrode of the first transistor is respectively connected with the source electrode of the fourth transistor and the common-mode voltage output terminal of the fourth transistor, the drain electrode of the common-mode voltage output terminal of the fourth transistor is connected with the drain electrode of the common-mode voltage output unit is connected with the drain electrode of the common-mode voltage unit is connected with the common-mode voltage output terminal of the fifth transistor.
5. The timing controlled low power consumption common mode feedback pre-amplifier circuit of claim 4, wherein the first transistor, the third transistor and the fifth transistor are the same type of transistor, the second transistor, the fourth transistor and the sixth transistor are the same type of transistor, wherein the first transistor and the second transistor are complementary type transistors.
6. The timing controlled low power consumption common mode feedback pre-amplifier circuit according to claim 1 or 2, wherein if the seventh clock control switch and the ninth clock control switch controlled by the fourth clock signal are both closed, the operation states of the first transistor and the second transistor are switched to be closed.
7. The timing controlled low power consumption common mode feedback pre-amplification circuit of claim 1, wherein the in-phase output of the pre-amplifier is connected to the inverting output of the pre-amplifier through a reset switch, wherein the reset switch is controlled to open and close by a short reset pulse signal.
8. The timing controlled low power consumption common mode feedback pre-amplification circuit of claim 7, wherein if said reset switch controlled by said short reset pulse signal is closed, a signal at said in-phase output of said preamplifier and a signal at said out-of-phase output of said preamplifier are set clear.
9. The timing controlled low power consumption common mode feedback pre-amplification circuit of claim 1, wherein if the operation state of the timing controlled low power consumption common mode feedback pre-amplification circuit is a reset state, the first clock control switch, the third clock control switch, the fifth clock control switch, and the second clock control switch and the fourth clock control switch controlled by the second clock signal are turned off.
10. A comparator comprising the timing controlled low power consumption common mode feedback pre-amp circuit and latch of claim 1, wherein
The non-inverting output end of the pre-amplifier is connected with the non-inverting input end of the latch, and the inverting input end of the pre-amplifier is connected with the inverting input end of the latch.
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| US6127958A (en) * | 1997-09-11 | 2000-10-03 | Hyundai Electronics Industries Co., Ltd. | Analog/digital converting circuit |
| KR20030094463A (en) * | 2002-06-04 | 2003-12-12 | 주식회사 티엘아이 | Common mode feedback circuit controlled by clock signal |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
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| US6617899B2 (en) * | 2001-05-25 | 2003-09-09 | Infineon Technologies Ag | Ultra high speed clocked analog latch |
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| US6127958A (en) * | 1997-09-11 | 2000-10-03 | Hyundai Electronics Industries Co., Ltd. | Analog/digital converting circuit |
| KR20030094463A (en) * | 2002-06-04 | 2003-12-12 | 주식회사 티엘아이 | Common mode feedback circuit controlled by clock signal |
| CN108832916A (en) * | 2018-06-22 | 2018-11-16 | 安徽传矽微电子有限公司 | A kind of high-speed low-power-consumption comparator circuit of low dynamic imbalance |
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