CN112652347B - Control method of deep well voltage of semiconductor device - Google Patents
Control method of deep well voltage of semiconductor device Download PDFInfo
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- CN112652347B CN112652347B CN202011517688.2A CN202011517688A CN112652347B CN 112652347 B CN112652347 B CN 112652347B CN 202011517688 A CN202011517688 A CN 202011517688A CN 112652347 B CN112652347 B CN 112652347B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
Abstract
The invention provides a control method of deep well voltage of a semiconductor device, wherein the semiconductor device comprises a first substrate, a first well arranged on the first substrate and a second well arranged on the first well, and the control method comprises the following steps: when a negative voltage is applied to the second well, the voltage of the first well is lowered. The invention has the advantages that the parasitic capacitance between the second well and the first well of the semiconductor device is reduced by reducing the voltage of the first well, so that the current consumed by the parasitic capacitance is reduced, and the circuit performance is improved.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a control method of deep well voltage of a semiconductor device.
Background
In 3D NAND memories, it is necessary in some cases to apply a negative voltage to the P-well of the NMOS transistor, and therefore, a Deep N-well (DNW, Deep NWell) is typically employed to isolate the NMOS transistor. Specifically, a deep N-well is formed over a P-substrate, a P-well is formed over the deep N-well, and the drain and source of the NMOS transistor are formed in an N-type region in the P-well, which isolates the P-substrate from the P-well.
One problem with using deep N-wells to isolate the P-substrate from the P-well is that parasitic capacitances can form at the boundary between the P-well and the deep N-well and at the boundary between the deep N-well and the P-substrate. In general, a plurality of NMOS transistors may be formed on one P substrate, and when there are too many NMOS transistors, parasitic capacitance may be large. When a negative voltage is applied to the P-well, the parasitic capacitance will consume a large current, having a negative impact on circuit performance.
Therefore, how to reduce the current consumed by the parasitic capacitor is a problem that needs to be solved at present.
Disclosure of Invention
The invention aims to provide a control method of deep well voltage of a semiconductor device, which can reduce the current consumed by parasitic capacitance.
In order to solve the above problems, the present invention provides a method of controlling a deep well voltage of a semiconductor device including a first substrate, a first well disposed on the first substrate, and a second well disposed on the first well, the method comprising: when a negative voltage is applied to the second well, the voltage of the first well is lowered.
Further, the type of the first substrate is the same as the type of the second well, and is opposite to the type of the first well.
Further, the first substrate is a P-substrate, the first well is a deep N-well, and the second well is a P-well.
Further, the voltage of the first well is reduced by applying a preset voltage to the first well to reduce the voltage of the first well from an initial voltage to the preset voltage.
Further, the initial voltage is a power supply voltage.
Further, the second well has an initial voltage, and the ramp time for the initial voltage of the first well to decrease to the preset voltage is the same as the ramp time for the initial voltage of the second well to decrease to the negative voltage.
Further, when the application of the negative voltage to the second trap is stopped, the voltage of the first trap is restored to the initial voltage from the preset voltage.
Further, the voltage of the first well is lowered by stopping the application of the voltage to the first well and determining the present voltage of the first well by the negative voltage applied to the second well.
Further, the current voltage satisfies the following formula:
Vdnw＝Vdd-|Vneg|*Cj1/(Cj1+Cj2)
where Vdnw is a current voltage of the first well, Vdd is an initial voltage of the first well, Vneg is a negative voltage applied to the second well, Cj1 is a parasitic capacitance formed at a boundary between the second well and the first well, and Cj2 is a parasitic capacitance formed at a boundary between the first well and the first substrate.
Further, the control method further includes: and monitoring the voltage of the first trap after stopping applying the voltage to the first trap, and applying the set voltage to the first trap as the current voltage of the first trap if the voltage of the first trap is less than a set voltage.
Further, if the first well voltage is greater than or equal to the set voltage, the current voltage of the first well is maintained.
Further, the voltage application to the first well is stopped by electrically disconnecting the first well from a power supply.
The invention has the advantages that the parasitic capacitance between the second well and the first well of the semiconductor device is reduced by reducing the voltage of the first well, so that the current consumed by the parasitic capacitance is reduced, and the circuit performance is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor device;
FIG. 2 is a schematic diagram showing the voltage variation of a P well and a deep N well before and after applying a negative voltage to the P well in the prior art;
FIG. 3 is a schematic diagram showing the voltage variations of the P-well and the deep N-well before and after applying a negative voltage to the P-well according to the first embodiment of the present invention;
FIG. 4 is a schematic diagram showing the voltage variations of the P-well and the deep N-well before and after applying a negative voltage to the P-well according to the second embodiment of the present invention;
FIG. 5 is a schematic diagram showing the voltage changes of the P-well and the deep N-well before and after applying a negative voltage to the P-well according to the third embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a method for controlling a deep well voltage of a semiconductor device according to the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic cross-sectional view of a semiconductor device. Referring to fig. 1, a deep N-well 110 is formed on a P-substrate 100, a P-well 120 is formed on the deep N-well 110, a drain D and a source S of an NMOS transistor are formed in an N-type region in the P-well 120, and the deep N-well 110 isolates the P-substrate 100 from the P-well 120. Here, a parasitic capacitance Cj1 may be formed at the boundary between the P-well 120 and the deep N-well 110, and a parasitic capacitance Cj2 may be formed at the boundary between the deep N-well 110 and the P-substrate 100. In general, a plurality of NMOS transistors may be formed on one P substrate, and when the number of NMOS transistors is too large, parasitic capacitances Cj1 and Cj2 become large. When P-well 120 applies a negative voltage, parasitic capacitance Cj1 will consume a large current, having a negative impact on circuit performance.
Therefore, the present invention provides a method for controlling a deep well voltage of a semiconductor device, which can reduce a parasitic capacitance between a first well and a second well of the semiconductor device, thereby reducing a current consumed by the parasitic capacitance and improving circuit performance.
The semiconductor device includes a first substrate, a first well disposed on the first substrate, and a second well disposed on the first well. Wherein the first substrate is of the same type as the second well and of the opposite type to the first well. For example, in this embodiment, referring to fig. 1, the first substrate is a P-substrate 100, the first well is a deep N-well 110, and the second well is a P-well 120. In other embodiments of the present invention, the first substrate may also be an N-substrate, the first well is a deep P-well, and the second well is an N-well.
The control method comprises the following steps: when a negative voltage is applied to the second well, the voltage of the first well is lowered. Specifically, in the present embodiment, the control method includes: when a negative voltage is applied to the P-well 120 and the voltage of the deep N-well 110 is lowered, the voltage difference at the boundary between the P-well 120 and the deep N-well 110 is reduced, so that the parasitic capacitance formed at the boundary between the P-well 120 and the deep N-well 110 is reduced, thereby reducing the current consumed by the parasitic capacitance.
Fig. 2 is a schematic diagram showing voltage changes of the P-well 120 and the deep N-well 110 before and after applying a negative voltage to the P-well in the prior art, and fig. 3 is a schematic diagram showing voltage changes of the P-well 120 and the deep N-well 110 before and after applying a negative voltage to the P-well in the first embodiment of the present invention. In the first embodiment, the voltage of the deep N-well 110 is reduced by applying a predetermined voltage to the deep N-well 110 to reduce the voltage of the deep N-well 110 from an initial voltage to the predetermined voltage.
Referring to fig. 1 and 2, in the prior art, before the enabling negative voltage Vneg _ en is applied to the P-well 120 of the semiconductor device, the voltage of the P-well 120 is Vss and the voltage of the deep N-well 110 is Vdd, after the enabling negative voltage Vneg _ en is applied to the P-well 120, the voltage of the P-well 120 changes from the initial voltage Vss to Vneg, the voltage of the deep N-well 110 does not change, and is still Vdd, and the voltage difference at the boundary between the P-well 120 and the deep N-well 110 is Vdd-Vneg.
Referring to fig. 1 and 3, in the control method of the present invention, before applying the enabling negative voltage Vneg _ en to the P-well 120 of the semiconductor device, the voltage of the P-well 120 is Vss, the voltage of the deep N-well 110 is the initial voltage Vdd, the enabling negative voltage Vneg _ en is applied to the P-well 120, and the voltage of the P-well 120 is changed from the initial voltage Vss to Vneg; meanwhile, a preset voltage Vdnw is applied to the deep N-well 110, and the voltage of the deep N-well 110 is reduced to the preset voltage Vdnw. The voltage difference at the boundary between the p-well 120 and the deep N-well 110 is Vdnw-Vneg, and the preset voltage Vdnw is smaller than the initial voltage Vdd, the voltage difference at the boundary between the p-well 120 and the deep N-well 110 is reduced compared to the voltage difference in the prior art, so that the parasitic capacitance Cj1 formed at the boundary between the p-well 120 and the deep N-well 110 is reduced, and the current consumed by the parasitic capacitance Cj1 is reduced, thereby reducing the influence on the circuit performance.
Further, in the present embodiment, the preset voltage Vdnw may be applied to the deep N-well 110 by a control circuit of a semiconductor device. Wherein the preset voltage Vdnw is less than the initial voltage Vdd for the purpose of reducing the voltage difference at the boundary between the p-well 120 and the deep N-well 110. Further, the initial voltage Vdd may be a power supply voltage.
Further, in the present embodiment, referring to fig. 3, when the application of the negative voltage to the P-well 120 is stopped, the voltage of the deep N-well 110 is restored from the predetermined voltage Vdnw to the initial voltage Vdd, so as to avoid the performance of the semiconductor device being affected by the too low voltage of the deep N-well 110 when the negative voltage is not applied to the P-well.
Further, when the enable negative voltage Vneg _ en is applied to the P-well 120 of the semiconductor device, the ramp time t1 for the initial voltage Vdd of the deep N-well 110 to decrease to the preset voltage Vdnw is the same as the ramp time t2 for the initial voltage Vss of the P-well 120 to decrease to the negative voltage Vneg, so that the voltage variation of the deep N-well 110 is synchronized with the voltage variation of the P-well, thereby more effectively reducing the parasitic capacitance and further reducing the current consumption.
In the first embodiment of the present invention, a preset voltage is applied to the deep N-well 110 to reduce the voltage of the deep N-well 110 from the initial voltage Vdd to the preset voltage Vdnw. In other embodiments of the present invention, other methods may be used to lower the voltage of the deep N-well 110. For example, in the second embodiment of the present invention, the voltage of the deep N-well is lowered by stopping the application of the voltage to the deep N-well and determining the present voltage of the deep N-well by the negative voltage applied to the P-well.
Specifically, fig. 4 is a schematic diagram illustrating voltage changes of the P-well 120 and the deep N-well 110 before and after applying a negative voltage to the P-well according to the second embodiment of the present invention, referring to fig. 1 and 4, in the present embodiment, when an enable negative voltage Vneg _ en is applied to the P-well 120, the voltage application to the deep N-well 110 is stopped. I.e., the enable negative voltage Vneg en is applied to the P-well 120, the controller does not apply a voltage to the deep N-well 110. The deep N-well 110 is electrically disconnected from the power supply, so that no voltage is applied to the deep N-well 110.
In the second embodiment, before applying the enabling negative voltage Vneg _ en to the P-well 120 of the semiconductor device, the voltage of the P-well 120 is Vss, the voltage of the deep N-well 110 is the initial voltage Vdd, the enabling negative voltage Vneg _ en is applied to the P-well 120, and the voltage of the P-well 120 is changed from the initial voltage Vss to Vneg; at the same time, the application of voltage to the deep N-well 110 is stopped, and the voltage of the deep N-well 110 is lowered, the present voltage of the deep N-well being determined by the negative voltage Vneg applied by the P-well 120. Since no voltage is applied to the deep N-well 110, a change in the voltage of the deep N-well 110 is illustrated with a dotted line in fig. 4.
Specifically, the current voltage satisfies the following formula:
Vdnw＝Vdd-|Vneg|*Cj1/(Cj1+Cj2)
wherein Vdnw is a current voltage of the deep N-well, Vdd is an initial voltage of the deep N-well, Vneg is a negative voltage applied to the P-well, Cj1 is a parasitic capacitance formed at a boundary between the P-well and the deep N-well, and Cj2 is a parasitic capacitance formed at a boundary between the deep N-well and the P-substrate.
In the second embodiment, although the preset voltage is not applied to the deep N-well, since the initial voltage is the power supply voltage, after the application of the voltage to the deep N-well 110 is stopped, the current voltage thereof inevitably decreases with respect to the power supply voltage, thereby achieving the purpose of reducing the voltage difference at the boundary between the p-well 120 and the deep N-well 110.
Further, in the present embodiment, referring to fig. 4, when the application of the negative voltage to the P-well 120 is stopped, the initial voltage Vdd is reapplied to the deep N-well, so that the deep N-well recovers the initial voltage, and the performance of the semiconductor device is prevented from being affected due to the too low voltage of the deep N-well 110 when the negative voltage is not applied to the P-well.
The inventors have found that when the enable negative voltage Vneg _ en is applied to the P-well 120 of the semiconductor device, the voltage of the deep N-well 110 is lowered too much, which also has a large impact on the performance of the semiconductor device. In the second embodiment, since the voltage application to the deep N-well 110 is stopped, the current voltage of the deep N-well is determined by the initial voltage Vdd of the deep N-well, the negative voltage Vneg applied by the P-well 120, the parasitic capacitance Cj1 formed at the boundary between the P-well and the deep N-well, and the parasitic capacitance Cj2 formed at the boundary between the deep N-well and the P-substrate, which may cause the current voltage of the deep N-well to be too low. To solve this problem, the present invention also provides a third embodiment. Fig. 5 is a schematic diagram illustrating voltage variations of the P-well 120 and the deep N-well 110 before and after applying a negative voltage to the P-well according to a third embodiment of the present invention, referring to fig. 5, in the third embodiment of the present invention, a limitation on the voltage variations of the deep N-well 110 is added.
Specifically, a set voltage Vclamp is set as shown by a solid line in the figure. After the voltage application to the deep N-well 110 is stopped, the current voltage of the deep N-well 110 is monitored, and at this time, the current voltage of the deep N-well 110 is the same as that described in the second embodiment. If the current voltage Vdnw of the deep N-well 110 is less than the set voltage Vclamp, the set voltage is applied to the deep N-well 110 as the current voltage of the deep N-well 110, so as to avoid an excessive voltage drop of the deep N-well 110. If the present voltage Vdnw of the deep N-well 110 is greater than or equal to the set voltage Vclamp, the present voltage of the deep N-well 110 is maintained, i.e., the set voltage Vclamp is not applied to the deep N-well 110. The setting voltage Vclamp can be selected according to the time requirement of the semiconductor device.
In the third embodiment of the present invention, the voltage of the deep N-well 110 is limited by setting the set voltage Vclamp, so as to avoid the degradation that affects the performance of the semiconductor device.
The control method of the deep N well voltage of the semiconductor device can reduce the parasitic capacitance between the p well and the deep N well of the semiconductor device, further reduce the current consumed by the parasitic capacitance and improve the circuit performance. The inventor finds that the current consumption can be saved by about 0.5% by adopting the control method of the invention in a reading device of a 3D NAND memory, and the performance of the memory is greatly improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (7)
1. A method of controlling a deep well voltage of a semiconductor device, the semiconductor device including a first substrate, a first well disposed on the first substrate, and a second well disposed on the first well, the method comprising: and reducing the voltage of the first well when a negative voltage is applied to the second well by stopping the application of the voltage to the first well and determining a current voltage of the first well by the negative voltage applied to the second well, the current voltage satisfying the following formula: vdnw | Vneg | × Cj1/(Cj1+ Cj2), where Vdnw is a current voltage of the first well, Vdd is an initial voltage of the first well, Vneg is a negative voltage applied to the second well, Cj1 is a parasitic capacitance formed at a boundary between the second well and the first well, and Cj2 is a parasitic capacitance formed at a boundary between the first well and the first substrate.
2. The method of claim 1, wherein the first substrate is of the same type as the second well and is of the opposite type to the first well.
3. The method according to claim 1, wherein the first substrate is a P-substrate, the first well is a deep N-well, and the second well is a P-well.
4. The method of claim 1, wherein the voltage of the first well is restored to the initial voltage when the application of the negative voltage to the second well is stopped.
5. The method of claim 1, further comprising: and monitoring the voltage of the first trap after stopping applying the voltage to the first trap, and applying the set voltage to the first trap as the current voltage of the first trap if the voltage of the first trap is less than a set voltage.
6. The method of claim 5, wherein if the first well voltage is greater than or equal to the set voltage, the current voltage of the first well is maintained.
7. The method for controlling the deep well voltage of the semiconductor device according to claim 1, wherein the first well is electrically disconnected from a power source by stopping the application of the voltage to the first well.
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| CN202210249399.1A CN114822657A (en) | 2020-12-21 | 2020-12-21 | Control method of deep well voltage of semiconductor device |
| CN202011517688.2A CN112652347B (en) | 2020-12-21 | 2020-12-21 | Control method of deep well voltage of semiconductor device |
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| CN102084489A (en) * | 2008-07-02 | 2011-06-01 | 美国亚德诺半导体公司 | Dynamically-driven deep N-well circuit |
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| KR20130104270A (en) * | 2012-03-13 | 2013-09-25 | 삼성전자주식회사 | Split gate type nonvolatile memory device and semiconductor device with embedded split gate type nonvolatile memory device |
| US9041089B2 (en) * | 2013-06-07 | 2015-05-26 | Ememory Technology Inc. | Nonvolatile memory structure |
| US9361995B1 (en) * | 2015-01-21 | 2016-06-07 | Silicon Storage Technology, Inc. | Flash memory system using complementary voltage supplies |
| JP6889441B2 (en) * | 2017-03-10 | 2021-06-18 | 三菱重工業株式会社 | Semiconductor device |
| US10290740B2 (en) * | 2017-03-31 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device with reduced parasitic capacitance |
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| CN102084489A (en) * | 2008-07-02 | 2011-06-01 | 美国亚德诺半导体公司 | Dynamically-driven deep N-well circuit |
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