CN112649667B

CN112649667B - Chip frequency sweeping device and method and electronic equipment

Info

Publication number: CN112649667B
Application number: CN201910960398.6A
Authority: CN
Inventors: 严献平; 杨鑫
Original assignee: Bitmain Technologies Inc
Current assignee: Bitmain Technologies Inc
Priority date: 2019-10-10
Filing date: 2019-10-10
Publication date: 2024-02-06
Anticipated expiration: 2039-10-10
Also published as: CN112649667A

Abstract

The embodiment of the application discloses a sweep device, a method and electronic equipment of a chip, which can improve the working frequency and calculation force of the chip while guaranteeing the balance work of multiple chips. The sweep device of this chip includes: the N groups of chips are arranged on M voltage domains of the circuit board, wherein each group of chips in the N groups of chips comprises at least one chip, and M, N is a positive integer greater than 1; and the controller is connected with the N groups of chips and is used for carrying out sweep frequency test on the N groups of chips so as to determine the highest frequency of each chip in the N groups of chips, and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips in at least two voltage domains in the M voltage domains is the same.

Description

Chip frequency sweeping device and method and electronic equipment

Technical Field

The present disclosure relates to the field of chip technologies, and in particular, to a device and method for scanning a chip, and an electronic device.

Background

With the development of information technology, in the fields of artificial intelligence (Artificial Intelligence, AI), digital credential processing and the like, the computational power requirements on chips for performing data operation processing are continuously and rapidly increased.

Currently, in some data processing-dedicated devices, a processor employs multiple chips for computation to increase the speed of data processing. In general, a plurality of chips are swept to determine a uniform operating frequency. If one of the chips has poor performance, the barrel effect can cause the lower working frequency of the other chips to influence the calculation power of the other chips, thereby influencing the system performance of the device.

Therefore, how to solve the problem of barrel effect caused by the chip with poor performance in the frequency sweeping process, improve the working frequency and calculation force of a plurality of chips, and ensure the working balance of the plurality of chips is a problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a chip frequency sweeping device, a chip frequency sweeping method and electronic equipment, which can improve the working frequency and the computing power of a chip while guaranteeing the balance work of multiple chips.

In a first aspect, a device for sweeping a chip is provided, including: the N groups of chips are arranged on M voltage domains of the circuit board, wherein each group of chips in the N groups of chips comprises at least one chip, and M, N is a positive integer greater than 1; and the controller is connected with the N groups of chips and is used for carrying out sweep frequency test on the N groups of chips so as to determine the highest frequency of each chip in the N groups of chips, and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips in at least two voltage domains in the M voltage domains is the same.

According to the technical scheme, the highest frequency of each chip in the N groups of chips is obtained through sweep frequency testing, the operating frequency of each chip is determined by considering the running balance of the chips among different voltage domains on the basis of the highest frequency of each chip, and the sum of the operating frequencies of the chips on at least two voltage domains is equal, so that the operating frequency of the whole N groups of chips is improved on the basis of ensuring the balance of the system, and the computing power and the performance of the whole N groups of chips are improved.

In one possible implementation, the controller is configured to: sequencing the highest frequencies of the plurality of chips on each of the M voltage domains according to the highest frequency of each of the N groups of chips;

and determining the highest frequency of the target chip as the working frequency of a plurality of chips with the same serial number, wherein the highest frequency of the target chip is the smallest among the highest frequencies of the plurality of chips with the same serial number.

In one possible implementation, N chips are disposed on each of the M voltage domains, and the controller is configured to: ordering the highest frequencies of the N chips on each of the M voltage domains;

and determining the highest frequency of the target chip as the working frequency of M chips with the same serial number, wherein the highest frequency of the target chip is the smallest among the highest frequencies of the M chips with the same serial number.

In one possible implementation, the controller is configured to: the highest frequencies of the N chips in each of the M voltage domains are ranked from 1 to N according to the size, wherein the chips with the same size of the highest frequencies are ranked according to the position sequence.

In one possible implementation, each of the N groups of chips includes M chips that are located in the M voltage domains, respectively.

In the implementation mode, the N chips on each voltage domain respectively belong to N groups, when the N groups of chips are subjected to frequency sweep test in sequence, the chips on the same voltage domain are not subjected to frequency sweep test at the same time, namely the chips on the same voltage domain cannot interfere with each other during frequency sweep, so that each highest frequency obtained by determination is more accurate.

In one possible implementation, the N sets of chips are arranged in N columns on the circuit board and the chips on the M voltage domains are arranged in M rows on the circuit board.

In one possible implementation, the sum of the operating frequencies of the chips of each of the M voltage domains is the same.

In one possible implementation, the controller is configured to: and sequentially carrying out sweep frequency test on the N groups of chips, and determining the highest frequency of each chip in the N groups of chips.

In the implementation mode, the N groups of chips are subjected to the frequency sweep test in sequence, the highest frequency of each chip in each group of chips is determined by taking the group as a unit, and compared with the frequency sweep test of each chip in the N groups of chips in sequence, the frequency sweep test can improve the test efficiency and reduce the test time.

In one possible implementation, the chips located in the same voltage domain among the M voltage domains are not subjected to the sweep test at the same time.

In one possible implementation, the controller is configured to: and starting from the a-th group of chips in the N groups of chips, carrying out sweep frequency test on the N groups of chips in sequence according to the position sequence, wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

In one possible implementation, the controller is configured to: for the kth group of chips in the N groups of chips, wherein k is larger than or equal to 1 and smaller than or equal to N, k is a positive integer, the test frequency of the kth group of chips is set to be the ith test frequency in X test frequencies, and test data are sent to the kth group of chips, wherein the X test frequencies are sequentially increased, X is a positive integer larger than 1, i is larger than or equal to 2 and smaller than or equal to X, and i is a positive integer;

and acquiring and judging whether the number of random numbers of W chips in the kth group of chips is in a first threshold range or not so as to determine the highest frequency of the W chips in the kth group of chips, wherein W is a positive integer, the W chips are chips with undetermined highest frequency in the kth group of chips, and the random numbers are data generated after the W chips receive test data.

In one possible implementation, the controller is configured to: when the number of random numbers of the W chips is judged to be in a first threshold range and i+1 is less than or equal to X, the ith+1th test frequency in the X test frequencies is adopted to carry out sweep frequency test on the kth group of chips;

judging that the number of random numbers of the W chips is in a first threshold range, and determining that the highest frequency of the W chips is the X test frequency in the X test frequencies when i+1 is more than X;

and when the number of the random numbers of the first chip in the W chips is judged to be out of a first threshold range, determining that the highest frequency of the first chip is the ith-1 th test frequency in the X test frequencies, and carrying out sweep frequency test on the kth group of chips by adopting the ith+1 th test frequency in the X test frequencies.

In one possible implementation, the controller is further configured to: the test frequency of the other groups of chips except the kth group of chips in the N groups of chips is set as the first test frequency in the X test frequencies.

In one possible implementation, the controller is configured to:

for the kth group of chips in the N groups of chips, wherein k is equal to or less than 1 and is equal to or less than N, k is a positive integer, the test frequency of the kth group of chips is set to be the jth test frequency in Y test frequencies, and test data are sent to the kth group of chips, wherein the Y test frequencies are sequentially decreased, Y is a positive integer greater than 1, j is equal to or less than 2 and is equal to or less than Y, and j is a positive integer;

In one possible implementation, the controller is configured to: when the number of random numbers of the W chips is judged to be out of a first threshold range and j+1 is less than Y, adopting the j+1th test frequency in the Y test frequencies to carry out sweep frequency test on the kth group of chips;

when the number of the random numbers of the W chips is judged to be out of a first threshold range and j+1=Y, determining the working frequency of the W chips as the Y-th test frequency in the Y test frequencies;

when the number of the random numbers of the first chip in the W chips is judged to be in a first threshold range, the working frequency of the first chip is determined to be the j-th test frequency in the Y test frequencies, and the j+1th test frequency in the Y test frequencies is adopted to carry out sweep frequency test on the k-th group of chips.

In one possible implementation, the controller is further configured to: the test frequency of the other groups of chips except the kth group of chips in the N groups of chips is set as the Y-th test frequency in the Y test frequencies.

In one possible implementation, the frequency sweep apparatus further includes: and the memory is used for storing the working frequency of each chip in the N groups of chips.

In one possible implementation, the data lines of the N sets of chips are connected in series.

In a second aspect, a method for scanning a chip is provided, including: testing N groups of chips to determine the highest frequency of each chip in the N groups of chips, wherein the N groups of chips are arranged on M voltage domains of a circuit board, each group of chips in the N groups of chips comprises at least one chip, and M, N is a positive integer greater than 1;

and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips in at least two voltage domains in the M voltage domains is the same.

In one possible implementation, the determining the operating frequency of each of the N sets of chips according to the highest frequency of each of the N sets of chips includes:

sorting the highest frequencies of the plurality of chips on each of the M voltage domains according to the highest frequency of each of the N groups of chips;

In one possible implementation, the M voltage domains each have N chips disposed thereon, and the sorting the highest frequencies of the plurality of chips in each of the M voltage domains includes:

ordering the highest frequencies of the N chips of each of the M voltage domains;

the determining the highest frequency of the target chip as the working frequencies of the plurality of chips with the same serial number comprises the following steps:

In one possible implementation, the ordering the highest frequencies of the N chips on each of the M voltage domains includes:

the highest frequencies of the N chips in each of the M voltage domains are ranked from 1 to N according to the size, wherein the chips with the same size of the highest frequencies are ranked according to the position sequence.

In one possible implementation, the performing a frequency sweep test on the N groups of chips to determine a highest frequency of each chip in the N groups of chips includes:

and sequentially carrying out sweep frequency test on the N groups of chips, and determining the highest frequency of each chip in the N groups of chips.

In one possible implementation, the sequentially performing the frequency sweep test on the N groups of chips includes:

and starting from the a-th group of chips in the N groups of chips, carrying out sweep frequency test on the N groups of chips in sequence according to the position sequence, wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

In one possible implementation, the sequentially performing the frequency sweep test on the N groups of chips and determining the highest frequency of each chip in the N groups of chips includes:

for the kth group of chips in the N groups of chips, wherein k is equal to or less than 1 and is equal to or less than N, k is a positive integer, the test frequency of the kth group of chips is set to be the ith test frequency in the X test frequencies, and test data are sent to the kth group of chips, wherein the X test frequencies are sequentially increased, X is a positive integer greater than 1, i is equal to or less than 2 and is equal to or less than X, and i is a positive integer;

In one possible implementation manner, the acquiring and determining whether the number of random numbers of the W chips in the kth group of chips is within the first threshold range to determine the highest frequency of the W chips in the kth group of chips includes:

when the number of random numbers of the W chips is judged to be in a first threshold range and i+1 is less than or equal to X, the ith+1th test frequency in the X test frequencies is adopted to carry out sweep frequency test on the kth group of chips;

In one possible implementation, the sequentially performing the frequency sweep test on the N groups of chips and determining the highest frequency of each chip in the N groups of chips further includes: the test frequency of the other groups of chips except the kth group of chips in the N groups of chips is set as the first test frequency in the X test frequencies.

when the number of random numbers of the W chips is judged to be out of a first threshold range and j+1 is less than Y, adopting the j+1th test frequency in the Y test frequencies to carry out sweep frequency test on the kth group of chips;

determining the working frequency of the W chips as the Y-th test frequency in the Y test frequencies when the number of random numbers of at least one chip in the W chips is out of a first threshold range and j+1=Y;

In one possible implementation, the sequentially performing the frequency sweep test on the N groups of chips and determining the highest frequency of each chip in the N groups of chips further includes: the test frequency of the other groups of chips except the kth group of chips in the N groups of chips is set as the Y-th test frequency in the Y test frequencies.

In one possible implementation, the frequency sweep method further includes: the operating frequency of each of the N sets of chips is stored.

In a third aspect, there is provided an electronic device comprising: a frequency sweep apparatus as in the first aspect or any possible implementation of the first aspect.

In a fourth aspect, a frequency sweep apparatus for a chip is provided, comprising a processor and a memory for storing program code for invoking the program code to perform the frequency sweep method of the second aspect or any of the possible implementations of the second aspect.

In a fifth aspect, a computer storage medium is provided for storing program code for performing the method of frequency sweeping of the second aspect or any one of the possible implementations of the second aspect.

Drawings

FIG. 1 is a schematic block diagram of an electronic device to which the present application may be applied;

FIG. 2 is a schematic block diagram of a chip sweep apparatus according to an embodiment of the present application;

FIG. 3 is a schematic flow chart of a chip sweep method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of the operating frequencies of multiple chips on a computing board according to an embodiment of the present application;

FIG. 5 is a schematic block diagram of a chip sweep apparatus according to an embodiment of the present application;

FIG. 6 is a schematic block diagram of another chip sweep apparatus according to an embodiment of the present application;

FIG. 7 is a schematic block diagram of another chip sweep apparatus according to an embodiment of the present application;

FIG. 8 is a schematic block diagram of another chip sweep apparatus according to an embodiment of the present application;

FIG. 9 is a schematic flow chart of a chip sweep method according to an embodiment of the present application;

FIG. 10 is a schematic flow chart of another chip sweep method according to an embodiment of the present application;

FIG. 11 is a top frequency schematic of an N-set of chips according to an embodiment of the present application;

FIG. 12 is a schematic diagram of ordering of N sets of chips according to an embodiment of the present application;

FIG. 13 is a schematic diagram of the operating frequencies of N sets of chips according to an embodiment of the present application;

FIG. 14 is a schematic flow chart diagram of a chip sweep method according to an embodiment of the present application;

FIG. 15 is a schematic flow chart of another chip sweep method according to an embodiment of the present application;

FIG. 16 is a schematic flow chart of another chip sweep method according to an embodiment of the present application;

FIG. 17 is a schematic flow chart of another chip sweep method according to an embodiment of the present application;

FIG. 18 is a schematic flow chart of another chip sweep method according to an embodiment of the present application;

fig. 19 is a schematic block diagram of another chip sweep apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

It should be understood that the specific examples herein are intended only to facilitate a better understanding of the embodiments of the present application by those skilled in the art and are not intended to limit the scope of the embodiments of the present application.

It should also be understood that, in various embodiments of the present application, the size of the sequence number of each process does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

It should also be understood that the various embodiments described in this specification may be implemented alone or in combination, and that the examples herein are not limited in this regard.

Unless defined otherwise, all technical and scientific terms used in the examples of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

First, a logical structure diagram of an electronic device capable of executing the embodiment of the present application will be described. The electronic device may be a processing device for digital credentials, or may be other electronic devices for performing operation processing for dedicated services, such as a computing server, a communication device, a high-performance personal computer, and so on, which is not limited in the embodiments of the present application.

As shown in fig. 1, the electronic device 10 may include a power module 110, a processing module 120, a control module 130, a storage module 140, an interface module 150, and a heat dissipation module 160. It should be understood that the components of the electronic device 10 may have fewer or more components than illustrated, or have a different configuration of components. The various components shown in fig. 1 may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.

The power module 110 is used for providing power to other modules in the electronic device 10, and may include an ac-dc converter (AC to DC converter), a dc-dc converter (DC to DC converter), and a low dropout linear regulator (Low Dropout Regulator, LDO) for outputting different dc voltages to meet the voltage requirements of different chips and circuits.

The processing module 120 is a calculation processing module for dedicated calculation, which may include a plurality of chips for running the calculation. When the electronic module 10 is a digital certificate processing device, the processing module 120 may include one or more computing boards (also referred to as computing boards), and a plurality of chips (chips), also referred to as integrated circuits (integrated circuit, ICs), are arranged in an array on the one or more computing boards for performing a hash (hash) operation to solve the hash value, thereby obtaining the digital certificate.

In the processing module 120, the data lines of the plurality of chips are connected in series, and the data obtained by the operation of the plurality of chips is transmitted to the control module 130 through the data lines, in other words, the data obtained by the operation of the plurality of chips is transmitted to the control module 130 through one data transmission interface, the operation data of the plurality of chips is sequentially transmitted to the control module 130 through the one data transmission interface, and not the data lines of each chip are connected with the control module 130 and are synchronously transmitted to the control module 130.

Further, in the processing module 120, a plurality of chips are distributed over a plurality of voltage domains, which are connected in parallel, instead of being distributed over the same voltage domain. By adopting the design mode of the voltage domains, chips on different voltage domains are not mutually influenced, and the working stability and reliability of the chips are improved.

Alternatively, the chip on the computing board may be any one of an application specific integrated circuit (Application Specific Integrated Circuit, ASIC) chip, a graphics processor (Graphics Processing Unit, GPU) chip, a central processing unit (Central Processing Unit, CPU) chip, and a field programmable gate array (Field Programmable Gate Array, FPGA) chip, which is not limited in this embodiment of the present application.

The control module 130 may be a System on a Chip (SOC) for connecting with other modules in the control electronic device 10 to ensure orderly performance and data communication between the modules. The control module 130 may include a microcontroller (Microcontroller Unit, MCU), microprocessor (Microprocessor), digital signal processor (Digital Signal Processor, DSP), analog-to-digital converter (ADC), digital-to-Analog converter (Digital to Analog converter, DAC), and oscillator (Electronic Oscillator) and phase-locked loop circuit (Phase Locked Loops, PLL) to provide time pulse signals, among others.

The control module 130 may generate different clock signals through a phase-locked loop and the like, so as to control the plurality of chips in the processing module 120 to operate at different operating frequencies. In addition, the control module 130 may also generate test data through circuits such as a microcontroller and a microprocessor, transmit the test data to a plurality of chips in the processing module 120, and receive and process random data generated by the plurality of chips. In other words, the control module 130 may be used to control the operation of the plurality of chips in the processing module 120 and to receive data for processing the plurality of chips.

In addition, the control module 130 may be connected to an external network through a network port, and the control module 130 is set through the network, so as to control the operation of the electronic device 10.

The memory module 140 may include one or more Double Data Rate synchronous dynamic random access memory (DDR SDRAM), flash memory (flash) and other memory units for storing Data in operation, software programs, and the like. Wherein the software program is used to control the operation of hardware modules in the electronic device 10.

In particular, the software programs in the storage module 140 include an Operating System (OS) for controlling and managing conventional System tasks such as memory management, storage control, and power management, among others, as well as various software components and/or drivers that facilitate communication between various software and hardware. The operating system includes, but is not limited to: linux, unix, windows, vxworks, etc. The communication instruction set includes software components for processing data received via the interface module 150 to facilitate communication with other devices via the interface module.

The interface module 150 may include different wired interfaces, such as universal serial bus (Universal Serial Bus, USB), ethernet (ETH), universal asynchronous transfer (Universal Asynchronous Receiver/Transmitter, UATR), and serial peripheral interface (Serial Peripheral Interface Bus, SPI), etc., for connecting to a variety of different external devices directly or via a network.

In addition, the electronic device 10 further includes a heat dissipation module 160, where the heat dissipation module 160 may be a Fan (Fan), a water cooling system, or other device for dissipating heat from the electronic device 10. The power module 110 is used for supplying power to the heat dissipation module 160, and the control module 130 is used for controlling the heat dissipation module 160 to work.

In the electronic device 10, the processing speed and processing power for the computing tasks depend on the processing module 120. In particular, in a digital certificate processing device, the system performance of the device depends in large part on the computing power of the computing power board, i.e. the speed at which the computing power board computes the hash function output. The computing power of the computing power board is determined by the computing power of a plurality of chips on the computing power board, and the computing power of each chip on the computing power board can influence the overall system performance of the equipment. In addition, the calculation power of the chip is closely related to the operation frequency, and the higher the operation frequency is, the more times per second are calculated, and the higher the calculation power of the chip is.

Typically, the operating frequencies of multiple chips on a single computing pad can be obtained through frequency sweep testing. Due to different factors such as manufacturers and manufacturing processes of the chips, the performances of different chips also have different differences, namely, the highest working frequencies of different chips are different, and when the chips work at frequencies exceeding the highest working frequencies, the chips may be abnormal. In the prior art, a unified sweep test is performed on all chips on a computing board, and all chips work at the same working frequency.

Fig. 2 shows a prior art chip sweep apparatus, as shown in fig. 2, chip sweep apparatus 200 includes a controller 210, a force plate 220, and a power supply 230. The power board 220 is provided with a plurality of chip ICs, and the power board 220 may be one example of the processing module 120, or may be another electrical component that carries a plurality of chips and provides electrical connection for the plurality of chips. The controller 210 may be an example of the control module 130, a system chip of the frequency sweeping device 200, or other electrical components with control functions, and may control the operations of a plurality of chips on the computing board 220. The power supply 230 is used to supply power to the electrical devices on the chip sweep apparatus 200, and may be specifically one example of the power supply module described above.

As shown in fig. 2, a plurality of chips are arranged in an X-row Y-column array on a power board 220. Optionally, in one embodiment, each row of Y chips is located on one voltage domain, and the X voltage domains are distributed on the power board 220 in X rows, where X, Y is typically a positive integer greater than 1.

Specifically, the Y chips on one voltage domain are powered in parallel by one voltage domain, and the chips on different voltage domains are powered by different voltage domains, in other words, the chip voltages on different voltage domains do not affect each other, but the chip voltages on the same voltage domain affect each other.

Optionally, the voltages of the X voltage domains may be the same or different, and controlling the multiple chips by different voltage domains can improve the stability of the power board 220, so that the power voltage of the whole power board is uniform.

In addition, the data lines of Y chips on one voltage domain are connected in series for transmitting data signals. And the head chip and the tail chip on one voltage domain are respectively connected with the chips on the adjacent voltage domains to transmit data signals. For example, as shown in FIG. 2, the first chip IC of the second row _2,1 With the first chip of the next row, i.e. IC _3,1 The last chip IC of the second row is connected to _2,Y With the last chip of the last row, i.e. IC _1,Y And (5) connection.

When Y chips in one voltage domain are connected in parallel to use the same voltage source to supply power, if one of the chips has poor performance, resulting in a lower highest operating frequency, if the controller 210 makes the chip operate at a frequency higher than the highest operating frequency, the chip will generate an abnormality, and the power supply voltage of the whole voltage domain may be lowered, so that all other chips in the voltage domain cannot normally operate.

For the chip frequency sweep apparatus 200, the embodiment of the present application provides a chip frequency sweep method 20, and the frequency sweep obtains the working frequencies of the plurality of chips on the force calculating plate 220. Alternatively, the main implementation body of the frequency sweeping method 20 may be the controller 210.

Fig. 3 shows a schematic flow chart of the chip sweep method 20.

S210: setting the frequency of a plurality of chips on the computing board as an ith test frequency F _i 。

Specifically, the controller sets the test operating frequency of the plurality of chips on the computing board to the ith test frequency F _i The ith test frequency F _i For W test frequencies F ₁ ～F _w The ith test frequency of the test frequency is sequentially increased from small to large, W is a positive integer greater than 1, i is greater than or equal to 1 and less than or equal to W, and i is a positive integer.

S220: test data (pattern) is sent to multiple chips.

Specifically, the controller sends one or more test data to the plurality of chips, each of the plurality of chips receives the same one or more test data and performs an operation on the one or more test data, in which the plurality of chips send an operation result to the controller 210, wherein the operation result may be a random number (nonce) generated by the chip on the one or more test data or an operation data such as a hash value, and the random number is a random number of a random number in the hash operation, and the range is 0-2 ³² In between, or in other numerical ranges, the embodiments of the present application are not limited in this regard. Performing hash operation for the test data for multiple times to obtain multiple random numbers, wherein the larger the number of the random numbers generated in unit time is, the stronger the computing capability of the chip is, I.e. the higher the computing power of the computing power board.

S230: and receiving and judging whether the number of random numbers generated by the chips is within a threshold range.

Specifically, when the chip works normally, the number of random numbers generated in the chip working process is relatively large in unit time, and when the chip works abnormally, the number of random numbers generated in the chip working process is relatively small in unit time. Therefore, a threshold range can be set for the whole of the plurality of chips, and when the number of random numbers generated by the plurality of chips is within the threshold range, the calculation power of the plurality of chips satisfies the demand. Alternatively, a threshold range may be set for each of the plurality of chips, and it may be determined whether the number of random numbers generated by each chip is within the threshold range, and if the number is within the threshold range, it is determined that the chip is operating normally, and if the number is outside the threshold range, it is determined that the chip is operating abnormally.

In addition, the random numbers generated by the plurality of chips are transmitted to the controller through the data lines connected in series, the controller receives the random number output by each of the plurality of chips, and can judge whether the random number of the whole plurality of chips is in the threshold range or not, and can judge whether the random number output by each of the plurality of chips is in the threshold range or not.

S241: if the number of random numbers is within the threshold value, adding 1 to i, and using the (i+1) th test frequency F _i+1 And carrying out sweep frequency test on the plurality of chips on the force calculating plate.

Specifically, when the number of random numbers output by each of the plurality of chips is within the threshold range, each of the plurality of chips works normally, or when the number of random numbers output by the plurality of chips as a whole is within the threshold range, the power calculation of the power calculation board satisfies the requirement, and at this time, the controller sets the test operating frequency of the plurality of chips on the power calculation board to the i+1th test frequency F _i+1 The (i+1) th test frequency F _i+1 ＞F _i Using the i+1th test frequency F _i+1 The sweep test is performed on the plurality of chips on the computing board, and the process can refer to the steps S210 to S230.

S242: if the plurality of randomIf the number is out of the threshold range, determining the working frequency of the chips as the i-1 test frequency F _i-1 。

Specifically, when the number of random numbers output by any one of the plurality of chips is out of a threshold range or the number of random numbers output by the whole of the plurality of chips is out of the threshold range, the sweep test is ended, and the working frequency of the plurality of chips on the computing board is determined as the i-1 th test frequency F _i-1 . That is, after the sweep test is finished, the working frequency of the chips on the power board is F in the normal working process of the chips _i-1 。

It should be understood that, for the arrangement of the voltage domains on the force plate 220 in fig. 2, in another embodiment, X chips in each column may be located on one voltage domain, and Y voltage domains are distributed on the force plate 220 in a total longitudinal direction. The frequency sweep method 20 described above is equally applicable to the power board in this embodiment, and will not be described here again.

Because a plurality of chips on the same voltage domain on the power calculating plate are connected in parallel to use one voltage source, if only one chip is abnormal on the same voltage domain, the abnormal operation of all the chips on the voltage domain can be caused, and the larger influence is caused. Therefore, in the frequency sweeping process, if the test frequency F _i If the highest frequency of a certain chip is exceeded, all chips on a voltage domain where the abnormal chip is located may generate abnormality, the number of random numbers generated by the chips on the voltage domain is reduced, and at the moment, the random numbers of the whole chips may not reach a threshold range; alternatively, only one chip is at the test frequency F during the sweep _i Abnormal operation, the random number is not in the threshold value range, the working frequency of all chips on the power board is smaller than the test frequency F _i 。

Fig. 4 shows a schematic diagram of the operating frequencies of a multichip on a computing force board.

As shown in FIG. 4, the power board has 6 rows and 10 columns of chips distributed therein, wherein the chips IC of the 2 nd row and 3 rd column _2,3 For the chip with poor performance on the force calculating plate, when the multi-chip on the force calculating plate is subjected to sweep test, the IC _2,3 Measurement at over 250MHzThe test frequency is abnormal, and at this time, the working frequencies of 60 chips on the power board are all 250MHz according to the sweep frequency method 20.

In summary, when the controller 210 performs the sweep test on the plurality of chips on the power board 220 by using the sweep method 20, the unified operating frequency of the plurality of chips is determined to be the normal operating frequency of the chip with the worst performance among the plurality of chips, and the other chips do not reach the highest operating frequency of the chips, i.e. do not reach the optimal operating state. In other words, a chip with poor performance may form a barrel effect, which results in that the frequency sweep method 20 cannot be used to determine the highest working frequency of each chip on the power board, so that the power board reaches an optimal working state, thereby affecting the performance of the whole system.

Based on this, the embodiment of the application provides a sweep method and a sweep device for chips, which are used for determining the highest frequency of the chips by respectively carrying out sweep test on a plurality of chips, so that the influence of the chips with poor performance on other chips is reduced, the chips are prevented from generating a wooden barrel effect, and the working frequency is determined according to the highest frequency of the chips on the basis of ensuring the working balance of the chips, thereby improving the computing power and the system performance of the chips.

Fig. 5 shows a schematic diagram of a chip sweep apparatus according to an embodiment of the present application.

As shown in fig. 5, the chip sweep apparatus 300 includes:

n groups of chips 320 arranged on M voltage domains of the circuit board, wherein each group of chips in the N groups of chips 320 comprises at least one chip, and M, N is a positive integer greater than 1;

the controller 310 is connected to the N groups of chips 320, and is configured to perform a sweep test on the N groups of chips 320 to determine a highest frequency of each of the N groups of chips 320, and determine an operating frequency of each of the N groups of chips 320 according to the highest frequency of each of the N groups of chips 320, where a sum of the operating frequencies of the chips in at least two of the M voltage domains is the same.

Optionally, in the embodiment of the present application, the chips in the N groups of chips 320 may be the same as the chips in the processing module 120 in fig. 1, and may be any one of an ASIC chip, a GPU chip, a CPU chip, or an FPGA chip, for performing data operations to implement multiple types of task data processing, such as multiple different types of data processing of audio, video, image, signal, digital, and so on.

Alternatively, as shown in FIG. 5, the M voltage domains V ₁ ～V _M The N groups of chips 320 may be arranged longitudinally in N columns on the circuit board, N groups of chip ICs ₁ ～IC _N As shown by the dashed box in fig. 5, M voltage domains V ₁ ～V _M As shown by the solid line boxes in fig. 5. Alternatively, the M voltage domains may be longitudinally arranged on the circuit board in M columns, and the N groups of chips may be transversely arranged on the circuit board in N rows. The following and the illustrated embodiments are all exemplified by N groups of chips 320 arranged in N columns in the longitudinal direction, and the related technical solutions of the lateral arrangement may refer to the longitudinal arrangement, which is not repeated herein.

Optionally, the number of chips on each of the M voltage domains on the circuit board is equal.

In the circuit board shown in fig. 5, N groups of chips 320 include M times N (mxn) chips in total, each group of chips in the N groups of chips includes M chips, the M chips are respectively located on M voltage domains, N chips are disposed on each of the M voltage domains, and the N chips respectively belong to different groups of chips. In other words, in the circuit board shown in fig. 5, different chips in each of the N groups of chips 320 are located on different voltage domains, respectively.

Alternatively, as shown in FIG. 6, N sets of chip ICs ₁ ～IC _a×N Each group of chips in the N groups of chips comprises a column of chips, a is an integer greater than 1, M voltage domains V ₁ ～V _M Are arranged transversely in M rows. Specifically, each of the N groups of chips includes a×m chips, which are respectively located on M voltage domains, and a×n chips are disposed on each of the M voltage domains, wherein M, N is a positive integer greater than 1.

Alternatively, as shown in FIG. 7, N sets of chip ICs ₁ ～IC _N In N columns longitudinally arranged, M voltage domains V ₁ ～V _b×M And b rows of chips are arranged transversely in b multiplied by M rows, and b is an integer greater than 1 in each of the M voltage domains. Specifically, each of the N groups of chips includes b×m chips respectively located on M voltage domains, where b×n chips are disposed on each of the M voltage domains, and M, N is a positive integer greater than 1.

In other words, in the frequency sweep apparatus as shown in fig. 6 and 7, part of the chips in each of the N groups of chips are located on the same voltage domain.

Similar to fig. 2, a plurality of chips located on the same voltage domain are powered in parallel by the same power source, and data lines of a plurality of chips in the N groups of chips are connected in series to transmit data signals.

Alternatively, the number of chips on each of the M voltage domains on the circuit board may not be equal.

For example, as shown in fig. 8, N sets of chips 320 are disposed on M voltage domains, wherein M, N is a positive integer greater than 1. M voltage domains, voltage domain V ₁ ～V _M-1 The number of the chips is the same, and N chips are arranged on the same chip, and the voltage domain V _M The number of upper chips is less than N, alternatively only N-1 or less. In this embodiment, the circuit board is used to carry the N groups of chips 320 and electrically connect the N groups of chips 320.

It should be appreciated that the circuit board includes, but is not limited to, a printed circuit board (Printed Circuit Board, PCB), a flexible circuit board (Flexible Printed Circuit board, PFC), or a software combination board (Soft and hard combination plate), as embodiments of the present application are not limited in this regard.

It should also be understood that, in the processing device of digital certificates, the combination of the circuit board and the N groups of chips may also be referred to as a computing board, and the circuit board and the N groups of chips in the embodiments of the present application are not limited to the computing board in the processing device of digital certificates, but may be a circuit board and the N groups of chips in any scenario, and the embodiments of the present application are not limited thereto.

Alternatively, the controller 310 may be an example of the control module 130 in fig. 1, a system chip of the frequency sweeping device 300, or other electrical components with control functions, and may control the operation of the N groups of chips 320.

Specifically, in this embodiment, when each of the N groups of chips 320 includes one chip, the controller 310 may be configured to perform a frequency sweep test on each of the chips to obtain a highest frequency and an operating frequency of each of the chips, and when each of the N groups of chips 320 includes a plurality of chips, the controller 310 may be configured to perform a frequency sweep test on the plurality of chips, determine the highest frequency for the plurality of chips of the same group, and determine the operating frequency of each of the N groups of chips according to the highest frequency of each of the N groups of chips, where the plurality of chips of the same group are located in a plurality of different voltage domains, or are located in part in the same voltage domain, and the sum of the operating frequencies of the chips located in the same voltage domain is equal.

In other words, instead of performing the sweep test on all the chips in the N groups of chips 320 to obtain the uniform working frequency of all the chips, the controller 310 performs the sweep test on each of the N groups of chips to obtain the highest frequency of each of the chips, where the highest frequencies of different chips in the N groups of chips may be the same or different, and the sweep process of each of the chips is not affected by the other chips, so that the sweep test on the chips with poor performance in the N groups of chips will not affect the sweep test on the other chips, in other words, when the sweep test is performed on the other chips, the highest frequencies obtained by the sweep test on the other chips are not affected by the chips with poor performance. On the basis of the highest frequency of each chip, the working frequency of each chip is determined by considering the working balance of the chips among different voltage domains, so that the sum of the working frequencies of the chips on the different voltage domains is equal, and on the basis of ensuring the system balance, the working frequency of the whole N groups of chips is improved, and the calculation power and the performance of the whole N groups of chips are improved.

Specifically, in this case, the controller 310 may perform the frequency sweep test on the N groups of chips using the chip frequency sweep method 30.

Alternatively, FIG. 9 shows a schematic flow diagram of a chip sweep method 30.

S300: a sweep test is performed on the N sets of chips to determine the highest frequency of each chip in the N sets of chips.

Optionally, the frequency sweep test may be sequentially performed on each chip in the N groups of chips, that is, after the frequency sweep test of the first chip is completed to determine the highest frequency of the first chip, the frequency sweep test may be performed on the second chip to determine the highest frequency of the second chip, until the frequency sweep test of all chips in the N groups of chips is completed to obtain the highest frequencies of all chips. In the embodiment of the present application, the chip sequence of the sweep test is not limited in the embodiment of the present application.

In this case, when a sweep test is performed on any one of the N groups of chips, for example, the first chip, the operation frequencies of the other chips except the first chip are the same, and the other chips are all operated normally.

Optionally, the frequency sweep test may be sequentially performed on each of the N groups of chips to determine a highest frequency of each of the N groups of chips, for example, performing the frequency sweep test on a first group of chips in the N groups of chips to obtain a highest frequency of each of the first group of chips, and then performing the frequency sweep test on a second group of chips in the N groups of chips to obtain a highest frequency of each of the second group of chips. By adopting the method, the frequency sweeping process of multiple chips can be simplified, the frequency sweeping test time is reduced, the frequency sweeping test efficiency is improved, and the method is described in detail below.

S400: and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips in at least two voltage domains in the M voltage domains is the same, and M, N is a positive integer greater than 1.

After the highest frequency of each chip in the N groups of chips is obtained, the working frequency of each chip in the N groups of chips is determined according to the condition of the sum of the working frequencies of the chips in at least two voltage domains in the M voltage domains, and the working frequency of each chip is smaller than or equal to the highest frequency of the chip.

Optionally, the highest frequencies of the plurality of chips on each of the M voltage domains are ordered according to the highest frequency of each of the N groups of chips, and the number of chips on each of the M voltage domains may be equal or unequal.

In the case where the number of chips in each of the M voltage domains is not equal, for example, in the chip sweep apparatus shown in FIG. 8, the highest frequencies of the plurality of chips in the M voltage domains are ordered, voltage domain V ₁ ～V _M-1 The chips on each voltage domain are ordered to be 1-N, and the voltage domain V _M The chips in the same sequence number in the M voltage domains are sequenced to 1-N-1, and the highest frequency of the target chip is used as the working frequency of the chips with the same sequence number, wherein the highest frequency of the target chip is the smallest in the chips with the same sequence number. For example, among the plurality of chips with serial numbers of "1", the highest frequency of the first target chip is the smallest, and the highest frequency of the first target chip is set as the operating frequency of the plurality of chips with serial numbers of "1"; similarly, among the other chips of the same serial number, the target chip having the smallest highest frequency is also provided.

In the embodiment of the present application, after the working frequency of each chip is determined by the above method, the voltage domain V ₁ ～V _M-1 The sum of the operating frequencies of the chips on each voltage domain is equal, while the voltage domain V _M The sum of the operating frequencies of the chips on the other voltage domains is not equal to the sum of the operating frequencies of the chips on the other voltage domains. At this time, although the system performance of the chip sweep apparatus is not optimal, the operating frequency can be determined according to the highest frequency of the chip on the basis of the working balance of most of the chips, thereby improving the computing power and the system performance of a plurality of chips.

Next, a specific frequency sweep method in the case where the number of chips on each of the M voltage domains is equal will be described in detail with reference to fig. 10 to 18. Specifically, FIG. 10 shows a schematic flow chart of a specific chip sweep method 30. The chip frequency sweeping method is suitable for the chip frequency sweeping device shown in fig. 5.

As shown in fig. 10, the step S400 may specifically include:

s410: the highest frequencies of the N chips for each of the M voltage domains are ordered.

S420: and determining the highest frequency of the target chip as the working frequency of M chips with the same serial number, wherein the highest frequency of the target chip is the smallest among the highest frequencies of the M chips with the same serial number.

Optionally, in step S410, the highest frequencies of the N chips in each of the M voltage domains are ranked by size from 1 to N, where the chips with the same highest frequencies are ranked by position order.

For example, fig. 11 shows an example of the highest frequency for an N-group chip.

As shown in fig. 11, N groups of chips 320 are arranged in 6 rows and 10 columns on the circuit board, each row of chips is disposed on one voltage domain, and includes 6 voltage domains, and 10 chips are disposed on each voltage domain, and the highest frequency of each chip in the N groups of chips is shown in the figure, where the unit of the highest frequency is megahertz MHz.

The chips in each of the 6 voltage domains in fig. 11 are ranked according to the highest frequency, wherein the chips with the same highest frequency are ranked according to the ranking order, and the chips in each of the 6 voltage domains are ranked in turn according to the ranking rule, so as to obtain a ranking schematic diagram shown in fig. 12.

As shown in fig. 11 and 12, the first voltage domain V ₁ Of the top 10 chips, the top frequency of the first 8 chips from left to right is 320MHz, and the top frequencies of the 9 th and 10 th chips are 310MHz, so that the first 8 chips are ordered from 1 to 8 in the order from left to right, and then the last 2 chips are ordered from 9 to 10 in the order from left to right.

Alternatively, the first 8 chips may be ranked from 1 to 8 in the order from right to left, or may be ranked from x to x+7, where x is any integer, or may be ranked from letter a to h; correspondingly, the last 2 chips are ordered from 9 to 10, or x+8 to x+9, or letters i to j in the order of right to left. It should be understood that in the embodiment of the present application, the arrangement rule adopted by each voltage domain is the same, and the chip arrangement sequence number in each voltage domain is not repeated, but the chip ordering range is the same. The embodiment of the present application does not limit the specific arrangement rule.

And (3) carrying out serial number arrangement on the highest frequency of the chips on each voltage domain according to the same arrangement rule, and determining the working frequency of the chips with the same serial number.

For example, as shown in fig. 11 and 12, there are 6 chips with the same serial number in each of the N groups of chips, which are located on 6 voltage domains, respectively. For 6 chips with serial number "5", see the shaded portions in FIGS. 11 and 12, wherein the chip with the lowest highest frequency is the chip IC of the second row and the second column _2,2 The chip is a target chip of a plurality of chips with the serial number of '5', the highest frequency is 310MHz, the highest frequency of other 5 chips is 320MHz, and the working frequencies of 6 chips with the serial number of '5' are all determined as the highest frequency of the target chip, namely 310MHz.

According to the above method, the operating frequencies are determined for other chips with the same serial numbers, and fig. 13 shows a schematic diagram of the operating frequencies of N groups of chips. As shown in fig. 13, the sum of the operating frequencies of the 10 chips on each voltage domain is the same, and the operating frequency of each chip in the N groups of chips does not exceed its highest frequency, so that the whole system operates in balance.

Comparing fig. 13 with fig. 4, the working frequencies of most chips on the circuit board in fig. 13 are all greater than 250MHz, and on the premise of guaranteeing the balanced operation of the chips on each voltage domain on the circuit board, the working frequencies of a plurality of chips are greatly improved, the calculation power of the plurality of chips is improved, and therefore the performances of the plurality of chips and the whole system are optimized.

It should be understood that, for the chip sweep apparatus shown in fig. 6 and 7, it is also possible to sort the highest frequencies of the a×n chips or the b×n chips of each of the M voltage domains using a method similar to that described above, and determine the highest frequency of the target chip as the operating frequency of the M chips of the same serial number, wherein the highest frequency of the target chip is the smallest among the highest frequencies of the M chips of the same serial number. Specific embodiments may be referred to the above related descriptions, and are not repeated here.

Optionally, in step S300, a sweep test may be performed on the N groups of chips in sequence to determine the highest frequency of each chip in the N groups of chips.

In the chip sweep apparatus 300 shown in fig. 5, each of the N groups of chips 320 includes M chips, which are located in different voltage domains, respectively, whereas in the chip sweep apparatus 300 shown in fig. 6 and 7, each of the N groups of chips 320 includes a×m chips or b×m chips, in which some of the chips in each group of chips are located in the same voltage domain.

Since the chips on the same voltage domain will interfere with each other during the sweep test, alternatively, the chip sweep apparatus shown in fig. 5 is used, and only one set of chips in the N sets of chips is subjected to the sweep test at a time, and the N chips on the same voltage domain are not subjected to the sweep test at the same time, in which case, the performance of the chip sweep apparatus 300 is optimal.

The following description will be given by way of example to the sweep apparatus in fig. 5, and the sweep methods of the sweep apparatus in fig. 6 and 7 will be described with reference to the related descriptions, which are not repeated here.

Alternatively, FIG. 14 shows a schematic flow diagram of a chip sweep method 30.

As shown in fig. 14, the above step S300 may specifically include the following steps.

S310: and sequentially carrying out sweep frequency test on N groups of chips, wherein N is a positive integer greater than 1.

Optionally, in the frequency sweep apparatus 300 shown in fig. 5, each group of chips includes M chips, where M is a positive integer greater than 1, and the M chips are located on M voltage domains, respectively.

S320: the highest frequency of each chip in each set of chips is determined.

Optionally, in the process of sequentially performing the frequency sweep test on each of the N groups of chips, the frequency sweep test may be performed on the N groups of chips in any order, for example, the frequency sweep test is performed on the even groups of chips in sequence, and then the frequency sweep test is performed on the odd groups of chips in sequence. Or any other sequence, the sweep test of each group of chips in the N groups of chips is completed sequentially, and the specific sweep test sequence is not particularly limited in the embodiment of the application.

Optionally, in the process of sequentially carrying out sweep test on each group of chips in the N groups of chips according to the position sequence, IC of the a-th group of chips in the N groups of chips _a After the sweep test is completed, determining the highest frequency of each chip in the a-th group of chips, and then IC-mounting the a+1-th group of chips _a+1 Or group a-1 chip IC _a-1 A sweep test is performed to determine the highest frequency of each of the a+1 th group of chips or the a-1 st group of chips. Wherein a is more than or equal to 1 and less than or equal to N, and a is a positive integer.

Optionally, the sweep test may be performed from a first group of chips in the N groups of chips until the sweep test for the nth group of chips is completed, or the sweep test may be performed from the nth group of chips in the N groups of chips until the sweep test for the first group of chips is completed; the frequency sweep test can also be started from any one of the N groups of chips, for example, the frequency sweep test is started from the a group of chips, after the frequency sweep test of the N group of chips is completed, the frequency sweep test is started from the first group of chips until the frequency sweep test of the a-1 group of chips is completed, and the embodiment of the application does not specifically limit the initial frequency sweep chipset.

Alternatively, in one possible implementation, X test frequencies F are employed for each of the N sets of chips ₁ ，F ₂ ，……，F _X And carrying out sweep frequency test, wherein the X test frequencies are sequentially increased, and X is a positive integer greater than 1.

It should be noted that the first test frequency F of the X test frequencies ₁ Lower, each chip in the N groups of chips at the first test frequency F ₁ The lower part works normally.

In the following, in the embodiment of the present application, referring to fig. 15 and 16, a process of performing a sweep test on any one of N groups of chips, for example, the kth group of chips, to determine the highest frequency of each chip in the kth group of chips is described in detail, where k is 1. Ltoreq.k. Ltoreq.n, and k is a positive integer.

Fig. 15 shows a schematic flow diagram of a chip sweep method 30.

As shown in fig. 15, the above-described step S310 and step S320 may specifically include the following steps.

S311: setting the test frequency of the kth group of chips to the ith test frequency F of the X test frequencies _i Wherein i is more than or equal to 2 and less than or equal to X, and i is a positive integer.

Specifically, the controller 310 controls the operating frequency of the kth chip to be the ith test frequency F _i . Optionally, a controller 310 is connected to the clock lines of each of the k-th set of chips, the controller 310 generating a clock having an ith test frequency F _i Is set to the clock signal CLK _i And the clock signal CLK is supplied through the clock line _i The clock signal transmitted to each chip in the k group of chips is CLK _i 。

S312: test data is sent for the kth group of chips.

The chips in the k group all operate on the clock signal CLK _i In this case, the controller 310 transmits the same test data to each of the k-th group of chips. Specifically, after the controller 310 generates the test data, the test data is transmitted to each chip of the kth group of chips through the input signal line. After each chip receives the test data, a plurality of random numbers and other operation data are generated through operation.

Optionally, the test data and the random number in this step are the same as those described in step S220 in fig. 3, and the relevant features may be referred to the above description, which is not repeated here.

S321: acquiring and judging whether the number of random numbers of W chips in a kth group of chips is in a first threshold range; wherein W is a positive integer, W chips are chips with the highest frequency not determined in the kth group of chips, and the random number is data generated after the W chips receive test data.

Specifically, the random number or other operation data generated by each chip may be sent to the controller 310 through the output signal line, and the controller 310 receives the random number or other operation data, and determines whether the random number or other operation data of the W chips in the kth group is within the threshold range or not, where the random number or other operation data of the W chips is not determined to be the highest frequency.

Here, when the ith test frequency is used to perform the sweep test on the kth group of chips, if each chip in the kth group of chips determines the highest frequency, in other words, when w=0, the sweep of the kth group of chips is ended.

S322: and determining the highest frequency of the W chips according to the judging result.

Specifically, the operating frequencies of the W chips are determined based on the above-described result of judging whether the number of random numbers or other operation data is within the threshold range.

Optionally, the k group of chips are subjected to sweep test according to the arrangement sequence of the X test frequencies. That is, after the ith test frequency is used to perform the frequency sweep test on the kth set of chips, the ith test frequency is used to perform the frequency sweep test on the kth set of chips with a test frequency greater than the ith test frequency, for example, the (i+1) th test frequency.

Fig. 16 shows a schematic flow diagram of a specific chip sweep method 30.

As shown in fig. 16, in the chip sweep method 30, the above-mentioned step S321 and step S322 may specifically include the following steps.

S3210: the number of random numbers of the kth group of chips is obtained.

Optionally, the number of random numbers for each chip of the kth group of chips is obtained.

Alternatively, the number of random numbers of each of the W chips in the kth group of chips may also be acquired.

Specifically, the controller 310 receives each of the kth group of chips or each of the W chips at the ith test frequency F _i And obtaining the number of the random numbers of each chip in the k group of chips or each chip in the W chips.

S3211: judging that the number of random numbers of each chip in the W chips is in a first threshold range, and when i+1 is less than or equal to X;

s3221: and carrying out sweep frequency test on the kth group of chips by adopting the (i+1) th test frequency in the X test frequencies.

S3212: judging that the number of random numbers of each chip in the W chips is in a first threshold range, and when i+1 is more than X;

s3222: the highest frequency of the W chips is determined to be the xth test frequency of the X test frequencies.

S3213: judging that the number of random numbers of a first chip in the W chips is out of a first threshold range;

s3223: the highest frequency of the first chip is determined as the i-1 st test frequency of the X test frequencies.

Then, step S3221 is continued: and carrying out sweep frequency test on the kth group of chips by adopting the (i+1) th test frequency in the X test frequencies.

Specifically, each of the W-th chips is obtained at the ith test frequency F _i After the number of random numbers is counted, the number of random numbers of each chip is judged.

When the number of random numbers of each of the W chips is within the first threshold value range, it is indicated that each of the W chips operates normally at the ith test frequency, in which case, when i+1 is less than or equal to X, i.e., the ith+1 test frequency is the last test frequency F _X Or has not yet reached F _X And when the test frequency is used, the ith test frequency is adopted to carry out sweep frequency test on the kth group of chips, and whether the W chips work normally at the ith test frequency and the (1) th test frequency is tested.

Similarly, when the W chips work normally at the (i+1) th test frequency, the (i+2) th test frequency is continuously used for sweep test on the (k) th group of chips, and the sweep test is sequentially performed until the (X) th test frequency F is used as the last test frequency _X And carrying out sweep frequency test on the k group of chips. The method for performing the sweep test on the kth group of chips by using the (i+1) th test frequency and the (X) th test frequency is the same as the sweep method 30, and will not be repeated here.

Particularly, when the ith test frequency is the last test frequency, namely the xth test frequency, i+1 > X, the sweep test is ended at this time, and the highest frequency of the W chips is determined as the xth test frequency.

The above describes the case where the number of random numbers of each of the W chips is within the first threshold range, and when the number of random numbers of any one of the W chips, for example, the first chip, is out of the first threshold range, it is described that the first chip operates abnormally at the i-th test frequency, and the highest frequency of the first chip does not reach the i-th test frequency.

In the embodiment of the application, the W chips are determined to be at the i-1 th test frequency F _i-1 On the basis of normal lower operation, the ith test frequency F is adopted _i Performing sweep test when the first chip of the W chips is at the ith test frequency F _i Abnormal working, when the working is normal under the ith-1 st test frequency, determining that the highest frequency of the first chip is the ith-1 st test frequency F _i-1 。

Optionally, in the above-described frequency sweep method 30, when the frequency sweep test is performed on the kth chip in the N-group of chips, the test frequencies of the chips in the N-group of chips except for the kth chip are set to the same frequency. Optionally, the test frequency of the other group of chips is set to be the first test frequency F1 of the X test frequencies, and since each chip in the N group of chips can work normally under the test frequency F1, the test result is more accurate when the normal work of the N group of chips is ensured, the k group of chips in the N group of chips is subjected to the sweep test.

It should be appreciated that in the sweep method 30 of the present embodiment, during the sweep test of k sets of chips, the second test frequency F may be selected from ₂ The sweep test is started, or the test can be started from any test frequency after the second test frequency, which is not limited in the embodiment of the present application.

It should also be appreciated that in determining the number of random numbers for each of the W chips, there may be a number of random numbers for a plurality of the W chips that are outside of the first threshold range, and then the highest frequencies for the plurality of chips are determined simultaneously.

It should also be understood that, after the ith test frequency is used to perform the sweep test on the kth set of chips, if the highest frequency of the first chip is determined, in the process of performing the sweep test on the kth set of chips by using the i+1 test frequencies, the first chip does not belong to the chip with the undetermined highest frequency, and the number of random numbers of the first chip may not be acquired.

In addition, in the sweep method 30 of the present application, the sweep test is performed on the kth group of chips in the N groups of chips, and the sweep test method of the other groups of chips in the N groups of chips may be the same as or different from the sweep test method of the kth group of chips, which is not limited in the embodiments of the present application.

Alternatively, in another possible embodiment, Y test frequencies F are employed for each of the N sets of chips ₁ ，F ₂ ，……，F _Y And carrying out sweep frequency test, wherein the Y test frequencies are sequentially decreased, and Y is a positive integer greater than 1.

It should be noted that the Y-th test frequency F of the Y test frequencies _Y Lower, each chip in the N groups of chips at the Y-th test frequency F _Y The lower part works normally.

In the following, in the embodiment of the present application, a process of performing a sweep test on any one of N groups of chips, for example, the kth group of chips, is described in detail with reference to fig. 17 and 18, where k is 1+.ltoreq.n, and k is a positive integer.

Fig. 17 shows a schematic flow diagram of another chip sweep method 30.

As shown in fig. 17, the above steps S310 and S320 may specifically include:

s313: setting the test frequency of the kth group of chips as the jth test frequency Fj in the Y test frequencies, wherein j is more than or equal to 2 and less than or equal to Y, and j is a positive integer.

S314: test data is sent for the kth group of chips.

S323: acquiring and judging whether the number of random numbers of W chips in a kth group of chips is in a first threshold range; wherein W is a positive integer, W chips are chips with the highest frequency not determined in the kth group of chips, and the random number is data generated after the W chips receive test data.

S324: and determining the highest frequency of the W chips in the k group of chips according to the judging result.

Specifically, the operating frequency of the kth group of chips is determined based on the above-described result of judging whether the number of random numbers or other operation data is within the threshold range.

Alternatively, the steps S313 to S324 are similar to the steps S311 to S322 in fig. 14, and the related schemes may be referred to the description, and are not repeated here.

Optionally, the k group of chips are subjected to sweep test according to the arrangement sequence of Y test frequencies. That is, after the kth group of chips is subjected to the frequency sweep test by using the jth test frequency, the kth group of chips is subjected to the frequency sweep test by using the test frequency smaller than the jth test frequency, for example, the (j+1) th test frequency.

Fig. 18 shows a schematic flow diagram of a specific chip sweep method 30.

As shown in fig. 18, in the chip sweep method 30, the above-described step S323 and step S324 may specifically include the following steps.

S3230: the number of random numbers of the kth group of chips is obtained.

S3231: judging that the number of random numbers of each of the W chips is out of a first threshold range, and j+1 is less than Y;

s3241: and adopting the j+1th test frequency in the Y test frequencies to carry out sweep frequency test on the kth group of chips.

S3232: judging that the number of random numbers of each of the W chips is out of a first threshold range, and j+1=Y;

s3242: the highest frequency of the W chips is determined to be the Y-th test frequency of the Y test frequencies.

S3233: judging the number of random numbers of a first chip in the W chips to be in a first threshold range;

s3243: the highest frequency of the first chip is determined to be the j-th test frequency of the Y test frequencies.

Then, step S3241 is continuously performed: and adopting the j+1th test frequency in the Y test frequencies to carry out sweep frequency test on the kth group of chips.

In particular, the method comprises the steps of,acquiring the test frequency F of each chip in the W chips at the j-th test frequency _j After the number of random numbers is counted, the number of random numbers of each chip is judged.

When the number of random numbers of each of the W chips is out of the first threshold range, the W chips are abnormal in operation under the j-th test frequency, and the highest frequency of the W chips does not reach the j-th test frequency.

In this case, when j+1 < Y, i.e. the jth test frequency is greater than the Y-1 th test frequency F _Y-1 When the test frequency of the chip is tested, the j+1th test frequency is used for carrying out sweep frequency test on the kth group of chips, and whether the j+1th test frequency is the highest frequency of the W chips is tested.

Similarly, when the W chips cannot normally work at the (j+1) -th test frequency, continuing to perform sweep frequency test on the (j+2) -th test frequency on the (k) -th group of chips, and sequentially performing the sweep frequency test until the (Y-1) -th test frequency F is adopted _Y-1 And carrying out sweep frequency test on the k group of chips. The method for performing sweep test on the kth group of chips by using the (j+1) th test frequency and the (Y-1) th test frequency is the same as the sweep method 30, and will not be repeated here.

In particular, when the jth test frequency is the Y-1 th test frequency F _Y-1 If the W chips are at the Y-1 test frequency F _Y-1 When the test is still unable to work normally, the sweep test is ended at this time, and the highest frequency of the W chips is determined as the first test frequency F ₁ 。

When the number of random numbers of the first chip in the W chips is in the first threshold range, the first chip is indicated to work normally under the j-th test frequency, and the highest frequency of the first chip reaches the j-th test frequency.

In the embodiment of the application, the W chips are determined to be at the j-1 th test frequency F _j-1 Based on the abnormal operation, the jth test frequency F is adopted _j Performing sweep test when the first chip of the W chips is at j-1 st test frequency F _j-1 Abnormal operation at the jth test frequency F _j Determining the first core when working normallyThe highest frequency of the chip is the jth test frequency F _j 。

It should be appreciated that in the sweep method of the embodiments of the present application, during the sweep test of k sets of chips, the 1 st test frequency F may be selected _Y The sweep test is started, or the test can be started from any test frequency after the 1 st test frequency, which is not limited in the embodiment of the present application.

It should also be understood that, after the kth group of chips is subjected to the sweep test with the jth test frequency, if the highest frequency of the first chip is determined, the first chip does not belong to the chip with the undetermined highest frequency in the process of performing the sweep test with the jth+1 test frequency on the kth group of chips, and the number of random numbers of the first chip may not be acquired.

It should also be appreciated that in determining the number of random numbers for each of the W chips, there may be a case where the number of random numbers for a plurality of the W chips are all within the first threshold range, and then the highest frequencies for the plurality of chips are determined simultaneously.

Optionally, in the above-described frequency sweep method 30, when the frequency sweep test is performed on the kth chip in the N-group of chips, the test frequencies of the chips in the N-group of chips except for the kth chip are set to the same frequency.

Optionally, the test frequency of the other group of chips is set to be the Y-th test frequency F of the Y test frequencies _Y Since each chip in the N groups of chips is at the test frequency F _Y The test method can work normally, so that the test result is more accurate when the frequency sweep test is carried out on the kth group of chips in the N group of chips under the condition of ensuring the normal work of the N group of chips.

Alternatively, fig. 19 shows a schematic block diagram of another chip sweep apparatus 300.

As shown in fig. 19, the chip sweep apparatus 300 further includes:

a memory 330, where the memory 330 is configured to store an operating frequency of each of the N groups of chips 320, where N is a positive integer greater than 1.

Specifically, the memory 330 may be an example of the memory module 140 in fig. 1.

Optionally, the memory 330 may be used to store computer-executable instructions. The controller 310 is configured to access the memory 330 and execute the computer-executable instructions to perform the operations of the chip sweep method of the embodiments of the present application described above.

Specifically, the controller 310 sequentially performs a frequency sweep test on N groups of chips 320, determines the operating frequency of each chip, and then sends the operating frequency of each chip to the memory 330, where the memory 330 stores the operating frequency. After the sweep test is completed, the controller 310 may read the operating frequency of each of the N sets of chips 320 from the memory 330 and control the N sets of chips 320 to operate according to the operating frequency.

Alternatively, the memory 330 may be two devices independent from the controller 310, or may be a memory unit in the controller 310, or may also be a memory unit disposed on a circuit board where N groups of chips 320 are located, which is not limited in this embodiment of the present application.

As shown in fig. 19, the chip sweep apparatus 300 may further include:

a power supply 340, the power supply 340 is used to power the chip sweep apparatus 300.

Specifically, the power supply 340 may supply power to the controller 310, the N groups of chips 320 and the memory 330 according to different devices and voltage requirements, where N is a positive integer greater than 1, in other words, the power supply 340 may include various voltage conversion circuits, such as an ac-dc conversion circuit or a dc-dc conversion circuit, to generate multiple different voltages and connect to different devices and circuits on the chip sweep apparatus 300.

Alternatively, the power supply 340 is a constant power supply module, and may be a constant dc or ac power supply module, and the controller 310, the circuit board where the N groups of chips 320 are located, and the memory 330 all include voltage conversion circuits, so that the voltage of the power supply 340 can be converted into a suitable device voltage, so as to meet the working requirement of the frequency sweeping device 300.

It should be understood that the power source 340 may be a power source in the chip frequency sweeping device 300, or may be an external power source of the chip frequency sweeping device 300, which is not limited in this embodiment of the present application.

The embodiment of the application also provides electronic equipment, which can comprise the device for scanning the chip of the various embodiments of the application.

The embodiment of the invention also provides a chip frequency sweeping device, which comprises a processor and a memory, wherein the memory is used for storing program codes, and the processor is used for calling the program codes to execute the frequency sweeping method of the method embodiment.

The embodiment of the invention also provides a computer storage medium, on which a computer program is stored, which when executed by a computer causes the computer to perform the method of the above-mentioned method embodiment.

The present invention also provides a computer program product comprising instructions which, when executed by a computer, cause the computer to perform the method of the method embodiment described above.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip sweep apparatus, comprising:

the N groups of chips are arranged on M voltage domains of the circuit board, wherein each group of chips in the N groups of chips comprises at least one chip, M is more than 1, N is more than or equal to 1, and M, N is a positive integer;

And the controller is connected with the N groups of chips and is used for carrying out sweep frequency test on the N groups of chips to determine the highest frequency of each chip in the N groups of chips, and determining the working frequency of each chip in the N groups of chips according to the highest frequency of each chip in the N groups of chips, wherein the sum of the working frequencies of the chips in at least two voltage domains in the M voltage domains is the same.

2. A frequency sweep apparatus as claimed in claim 1 wherein the controller is configured to:

sequencing the highest frequencies of the plurality of chips on each of the M voltage domains according to the highest frequencies of each of the N groups of chips;

and determining the highest frequency of the target chip as the working frequency of a plurality of chips with the same serial numbers, wherein the highest frequency of the target chip is the smallest among the highest frequencies of the plurality of chips with the same serial numbers.

3. A frequency sweep apparatus as claimed in claim 2 wherein N chips are provided on each of the M voltage domains, the controller being for:

ordering the highest frequencies of the N chips on each of the M voltage domains;

4. A frequency sweep apparatus as claimed in claim 3 wherein the controller is adapted to:

and sequencing the highest frequencies of the N chips in each of the M voltage domains to be 1 to N according to the sizes, wherein the chips with the same highest frequencies and the same sizes are sequenced according to the position sequence.

5. A frequency sweep apparatus as claimed in any one of claims 1 to 4 wherein each of the N groups of chips comprises M chips, the M chips being located in the M voltage domains respectively.

6. A frequency sweep apparatus as defined in any one of claims 1-4 wherein the N sets of chips are arranged in N columns on the circuit board and the chips on the M voltage domains are arranged in M rows on the circuit board.

7. A frequency sweep apparatus as claimed in any one of claims 1 to 4 wherein the controller is configured to:

and carrying out sweep frequency test on the N groups of chips in sequence, and determining the highest frequency of each chip in the N groups of chips.

8. A frequency sweep apparatus as defined in claim 7 wherein the M voltage domains of chips located in the same voltage domain are not subjected to frequency sweep testing at the same time.

9. A frequency sweep apparatus as defined in claim 7 wherein the controller is configured to:

10. A frequency sweep apparatus as defined in claim 7 wherein the controller is configured to:

for the kth group of chips in the N groups of chips, wherein k is equal to or less than 1 and is equal to or less than N, k is a positive integer, the test frequency of the kth group of chips is set to be the ith test frequency in X test frequencies, and test data are sent to the kth group of chips, wherein the X test frequencies are sequentially increased, X is a positive integer greater than 1, i is equal to or less than 2 and is equal to or less than X, and i is a positive integer;

and acquiring and judging whether the number of random numbers of W chips in the kth group of chips is in a first threshold range or not so as to determine the highest frequency of the W chips in the kth group of chips, wherein W is a positive integer, the W chips are chips in the kth group of chips, the highest frequency of which is not determined, and the random numbers are data generated after the W chips receive test data.

11. A frequency sweep apparatus as claimed in claim 10 wherein the controller is configured to:

when the number of random numbers of the W chips is judged to be in a first threshold range and i+1 is less than or equal to X, carrying out sweep frequency test on the kth group of chips by adopting the (i+1) th test frequency in the X test frequencies;

Judging that the number of random numbers of the W chips is in a first threshold range, and determining that the highest frequency of the W chips is the X-th test frequency in the X test frequencies when i+1 > X;

12. A frequency sweep apparatus according to claim 10 or 11, wherein the controller is further adapted to:

and setting the test frequency of the chips of the N groups except the kth group of chips as the first test frequency of the X test frequencies.

13. A frequency sweep apparatus as defined in claim 7 wherein the controller is configured to:

14. A frequency sweep apparatus as claimed in claim 13 wherein the controller is configured to:

determining the working frequency of the W chips as the Y-th test frequency in the Y test frequencies when the number of the random numbers of the W chips is out of a first threshold range and j+1=Y;

and when the number of the random numbers of the first chip in the W chips is judged to be in a first threshold range, determining that the working frequency of the first chip is the j-th test frequency in the Y test frequencies, and carrying out sweep frequency test on the k-th group of chips by adopting the j+1th test frequency in the Y test frequencies.

15. A frequency sweep apparatus according to claim 13 or 14 wherein the controller is further operable to:

and setting the test frequency of the chips of the N groups except the kth group of chips as the Y test frequency of the Y test frequencies.

16. A frequency sweep apparatus as defined in any one of claims 1-4, further comprising: and the memory is used for storing the working frequency of each chip in the N groups of chips.

17. A frequency sweep apparatus as claimed in any one of claims 1 to 4 wherein the data lines of the N sets of chips are connected in series.

18. A method of sweeping a chip, comprising:

carrying out sweep frequency test on N groups of chips to determine the highest frequency of each chip in the N groups of chips, wherein the N groups of chips are arranged on M voltage domains of a circuit board, each group of chips in the N groups of chips comprises at least one chip, M is more than 1, N is more than or equal to 1, and M, N is a positive integer;

19. A method of sweeping according to claim 18, wherein determining the operating frequency of each of the N groups of chips based on the highest frequency of each of the N groups of chips comprises:

sorting the highest frequencies of the plurality of chips on each of the M voltage domains according to the highest frequencies of each of the N groups of chips;

20. A method of frequency sweeping according to claim 19 wherein N chips are provided on each of the M voltage domains, the ordering the highest frequencies of the plurality of chips of each of the M voltage domains comprising:

21. A method of frequency sweeping according to claim 20, wherein said ordering the highest frequencies of the N chips on each of the M voltage domains comprises:

and sequencing the highest frequencies of the N chips on each of the M voltage domains to be 1 to N according to the sizes, wherein the chips with the same highest frequencies are sequenced according to the position sequence.

22. A method of sweeping according to any one of claims 18 to 21, wherein each of the N groups of chips comprises M chips, the M chips being located in the M voltage domains respectively.

23. A method of sweeping according to claim 22, wherein the N groups of chips are arranged in N columns on the circuit board and the chips on the M voltage domains are arranged in M rows on the circuit board.

24. A method of frequency sweep according to any of claims 18 to 21, wherein the frequency sweep testing of the N groups of chips to determine the highest frequency of each of the N groups of chips comprises:

25. A method of sweeping the voltage across the M voltage domains according to claim 24, wherein the chips in the same voltage domain are not simultaneously sweep tested.

26. A method of frequency sweep according to claim 24, wherein the sequentially performing frequency sweep tests on the N sets of chips comprises:

27. A method of frequency sweep according to claim 24 wherein the sequentially performing a frequency sweep test on the N sets of chips and determining the highest frequency for each of the N sets of chips comprises:

28. The method of claim 27, wherein the obtaining and determining whether the number of random numbers of the W chips in the k-th set of chips is within a first threshold range to determine the highest frequency of the W chips in the k-th set of chips comprises:

29. A method of frequency sweep according to claim 27 or 28, wherein the sequentially performing sweep test on the N sets of chips and determining the highest frequency for each of the N sets of chips further comprises:

30. A method of frequency sweep according to claim 24 wherein the sequentially performing a frequency sweep test on the N sets of chips and determining the highest frequency for each of the N sets of chips comprises:

31. The method of claim 30, wherein the obtaining and determining whether the number of random numbers of the W chips in the k-th set of chips is within a first threshold range to determine the highest frequency of the W chips in the k-th set of chips comprises:

32. A method of frequency sweep according to claim 30 or 31, wherein the sequentially performing sweep test on the N sets of chips and determining the highest frequency for each of the N sets of chips further comprises:

33. A method of sweeping according to any one of claims 18 to 21, further comprising:

And storing the working frequency of each chip in the N groups of chips.

34. A method of sweeping according to any one of claims 18 to 21, wherein the data lines of the N groups of chips are connected in series.

35. An electronic device, comprising:

a chip frequency sweeping device according to any one of claims 1 to 17.

36. A chip frequency sweep apparatus comprising a processor and a memory for storing program code, the processor for invoking the program code to perform the frequency sweep method of any of claims 18 to 34.

37. A computer readable storage medium storing program code for performing a frequency sweep method according to any one of claims 18 to 34.