CN112637070A - Method and equipment for searching table item - Google Patents
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Abstract
The present disclosure provides a method and a device for searching table items, wherein the method is applied to searching a target numerical value corresponding to a keyword in an FPGA chip, and includes: acquiring a keyword; searching a first group number and a first group validity identification corresponding to a first index in a first table stored in the FPGA chip, wherein the first table is used for storing the group number of a large group to which a numerical value corresponding to each keyword belongs and the group validity identification of the large group, and the first index is obtained from a first part of the keywords; if the first identifier is valid, searching a table entry corresponding to a second index in a second table stored in the FPGA chip, wherein each table entry is used for storing a numerical value, each group valid identifier is valid and comprises a plurality of table entries, and the second index is obtained by a second part of the keyword and the first group number; and determining a target value according to the values in the table entries. The technical scheme provided by the disclosure reduces the searching times, improves the searching speed and realizes the balanced optimization of the area and the speed.
Description
Technical Field
The present disclosure relates to the field of lookup algorithm technologies, and in particular, to a method and an apparatus for table entry lookup.
Background
Area and speed are the persistent topics in the design of an FPGA (Field Programmable Gate Array), and how to handle the balance relationship between area and speed is very important in the design of the FPGA. On one hand, to increase the processing speed, more resources need to be consumed, i.e. a larger area is needed; on the other hand, in order to reduce the area, the processing speed needs to be reduced. When designing a search algorithm based on an FPGA, it is a primary task to save resources and increase processing speed as much as possible.
In practical application, when a packet is transmitted, after the number of packets of a certain type in each stream reaches a threshold N, the packet is processed, and the corresponding threshold N needs to be configured according to the transport layer protocol type and the destination port of the packet, where N is a positive integer within a range from 1 to 65536.
In the related art, the method for searching for the threshold value for different messages includes two methods: one method is a direct search method, which stores all threshold values N corresponding to messages with different transmission layer protocol types and different destination ports in an FPGA chip, and directly obtains a target value by searching once according to indexes, wherein the search speed is high, but the indexes and the corresponding values of different messages are mapped one by one, so that too many storage resources are consumed; the other method is a binary search method, which stores multiple types of messages to be searched, consumes less storage resources, needs to search for the messages for multiple times, and has too low search speed. Both searching methods fail to achieve the balanced processing of speed and area, and have defects.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a method and a device for searching a table entry, so as to solve the problems of a large area of a direct search method and a low speed of a binary search method when searching in an FPGA chip.
Specifically, the embodiment of the present disclosure is implemented by the following technical solutions:
in a first aspect, a method for searching a table entry is provided, where the method is applied to search a target value corresponding to a keyword in a field programmable gate array FPGA chip, and includes:
acquiring the keyword;
searching a first group number and a first group validity identification corresponding to a first index in a first table stored in an FPGA chip, wherein the first table is used for storing the group number of a large group to which each keyword belongs and the group validity identification of the large group, and the first index is obtained from a first part in the keywords;
if the first group validity identifier is valid, searching a table entry corresponding to a second index in a second table stored in an FPGA chip, wherein each table entry is used for storing a numerical value, the large group with each group validity identifier being valid comprises a plurality of table entries, and the second index is obtained from a second part of the keyword and the first group number;
and determining the target value according to the values in the table items.
In a second aspect, an apparatus for searching table entries is provided, where the apparatus is applied to search for a target value corresponding to a keyword, and includes:
the acquisition module is used for acquiring the keywords;
the first-level searching module is used for searching a first group number and a first group validity identification corresponding to a first index in a first table stored in an FPGA chip, the first table is used for storing the group number of a large group to which each keyword belongs and the group validity identification of the large group, and the first index is obtained from a first part of the keywords;
a second-level lookup module, configured to, if the first group validity flag is valid, lookup a table entry corresponding to a second index in a second table stored in an FPGA chip, where each table entry is used to store a numerical value, the large group with each group validity flag being valid includes a plurality of table entries, and the second index is obtained from a second part of the keyword and the first group number;
and the determining module is used for determining the target numerical value according to the numerical value in the table entry.
According to the technical scheme provided by the embodiment of the disclosure, the keywords are grouped, and then the numerical values and the indexes are subjected to many-to-one mapping relationship, so that the one-to-one mapping of the numerical values and the indexes is avoided, and the storage resources occupied by the mapping are reduced; the keyword is divided into a plurality of parts, and the parts of the keyword are sequentially indexed, so that the searching times are reduced, the searching speed is improved, and the balanced optimization of the area and the speed is realized.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the specification.
Drawings
In order to more clearly illustrate one or more embodiments of the present disclosure or technical solutions in related arts, the drawings used in the description of the embodiments or related arts will be briefly described below, it is obvious that the drawings in the description below are only some embodiments described in one or more embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive exercise.
FIG. 1 is a schematic diagram illustrating a grouping approach according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram illustrating a storage structure of a first table according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram illustrating a storage structure of a second table according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a memory structure of the direct lookup method;
FIG. 5 is a flow chart illustrating a method of table entry lookup according to an embodiment of the present disclosure;
fig. 6 is a block diagram of an entry lookup apparatus according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the specification, as detailed in the appended claims.
The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present specification. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
In order to realize the balance between the speed and the area in the FPGA chip, the technical scheme provided by the disclosure introduces a method for storing numerical values through a first table and a second table, and the first table and the second table are pre-established before searching. The method comprises the following steps:
firstly, dividing each keyword into a plurality of large groups according to the sequence of the keywords from small to large, wherein the first part of the keywords in each large group is the same. And selecting the large groups to which the keywords needing to be searched for numerical values belong, and continuously allocating a unique group number and an effective group validity identifier for each selected large group from 0. The group validity flag of the other unselected large group is set to invalid, and the group number may not be set, or may be set to 0. And sequentially storing the group number of the large group and the group validity identification of the large group in a storage space corresponding to a first table in the FPGA chip by taking the first part of the keyword as an index address.
And further, the selected large groups are regrouped, and the keywords of each large group are divided into a plurality of small groups from small to large. And sequentially storing table items in a storage space corresponding to a second table in the FPGA chip by taking the group number of the large group to which the small group belongs before grouping and the second part of the key word as index addresses, wherein each table item is a numerical value corresponding to the key word in each small group and the validity identification of the numerical value.
The grouping and storage manner when the first table and the second table are established will be further described below with reference to different specific embodiments of searching for corresponding thresholds in a packet.
Grouping mode referring to fig. 1, a key is binary data, and the key is represented in decimal form in fig. 1. For messages of different transport layer protocol types and destination ports, the extracted keywords are 17 bits, the value range is decimal 0 to 131071, wherein the protocol type occupies the highest bit, and the next 16 bits represent the destination port number. The 131072 keywords are divided into one group of 64 keywords and 2048 groups in descending order. The high 11 bits of each group of keys are the same, and the high 11 bits of the key are the first part of the key: protocol type and destination port number first part bits. Since each message does not have a corresponding threshold, nor does each type of message need to search for a threshold, the large group to which the keyword requiring the threshold is assigned is selected, in this embodiment, 256 large groups are selected, each group is arbitrarily assigned with a unique group number, the group number group has a value range of 0 to 255, and occupies 8 bits.
Further, the selected 256 groups of keywords are regrouped, and the 64 keywords in each group are grouped in the order from small to large, in this embodiment, every 4 keywords are divided into a small group, which is totally 4096 small groups. The high 15 bits of each small group of keywords are the same, and the first part of the keywords in the high 15 bits is removed, namely the second part of the keywords: the second part of the bits of the destination port number, the lower 2 to 5 bits of the destination port number (dport [5:2 ]).
The specific storage mode is as follows: first, referring to the first table shown in fig. 2, with the high 11 bits of each group of keys as the index address, a group number and a group validity flag are written in the storage space corresponding to each large group in the first table. Wherein, the storage space corresponding to the selected 256 large groups is written with the group numbers distributed respectively and the group validity identifier group _ vld is set to be 1, which indicates that the large group is valid; and writing a group number into the storage space corresponding to the rest unselected large groups to be 0, and setting a group validity identifier group _ vld to be 0, so as to indicate that the large group is invalid. The first table uses a storage space having a depth of 2048 bits and a width of 9 bits in total, and can be stored in a BRAM (Block RAM) having a capacity of 18 kb.
Referring to the second table shown in fig. 3, with the group number of the big group to which the small group belongs before grouping and the second partial sum of the keys as the index address, writing the N value corresponding to each key in the small group in the storage space corresponding to each small group in the second table: n0, N1, N2 and N3, and simultaneously writing 4 corresponding validity flags vld, wherein vld is 1 to indicate that the N value is valid, and vld is 0 to indicate that the N value is invalid. The second table uses a memory space having a depth of 4k and a width of 68 bits in total, and can be stored in a URAM (Ultra RAM) having a depth of 4k and a width of 72 bits and a capacity of 288 kb.
In the scheme of the direct lookup method, the values and the indexes are mapped one by one for storage, and even if only part of the transport layer protocol types and the threshold of the destination port message need to be searched, all the thresholds need to be stored, as shown in fig. 4, a storage space with the depth of 131072 and the width of 16 is consumed, and 2160Kb of BRAM resources are consumed. The technical scheme disclosed by the invention needs one BRAM with 18kb and one URAM with 288kb, and consumes 306kb of storage resources, so that the occupation of the storage resources is greatly reduced.
The following describes a search process of the technical solution provided by the present disclosure.
As shown in fig. 5, fig. 5 is a flowchart of a method for searching a table entry according to an embodiment of the present disclosure, where the method is used to search a target value corresponding to a keyword in an FPGA chip, and includes the following steps:
and step S11, acquiring the keywords.
The keyword is binary data, and words, letters, symbols, numbers, and the like may be obtained by various methods and then converted into a binary form of the keyword, which is not limited in this disclosure.
Still, searching for corresponding thresholds in different messages is taken as an embodiment to explain how to obtain keywords, and when it is necessary to configure a corresponding threshold N according to a transport layer protocol type and a destination port of a target message, so that different processing can be subsequently performed on target messages with different thresholds, obtaining the keywords may be:
and receiving a target message to be processed. The target packet carries a transport layer Protocol (TCP) or a User Datagram Protocol (UDP), and the destination port number has a value range from 0 to 65535.
Extracting the keywords from the target message, wherein the keywords comprise: the protocol type and the destination port number of the target message. And (3) using 1-bit data pro to represent the protocol type of the target message, wherein the pro value is 0 to represent that the protocol type is TCP, and the pro value is 1 to represent that the protocol type is UDP. The destination port number of the destination packet can be represented by 16-bit data dport, and the binary form of the destination port number at least includes: a first part of bits of the destination port number and a second part of bits of the destination port number. Combining Pro with 1 bit and dport with 16 bits into a key with 17 bits, wherein Pro with 1 bit is at the highest position of the data, and the value range of the key is 0 to 131071 in decimal.
Step S12, a first group number and a first group validity flag corresponding to a first index are searched in a first table stored in the FPGA chip, the first table is used to store a group number of a large group to which each keyword belongs and a group validity flag of the large group, and the first index is obtained from a first part of the keyword.
In this step, after the keyword is obtained, a first index is obtained from a first part of the keyword, a storage space corresponding to the first index is searched in a first table stored in the FPGA chip, and the storage space stores a first group number and a first group validity identifier.
And if the first group of validity marks are invalid, determining that no target numerical value corresponding to the keyword exists, and not searching.
The following steps are explained by using the above examples of searching for the corresponding threshold N in different messages:
after the key is fetched, the first index, i.e. the protocol type Pro and the high 10-bit data dport [15:6] of the destination port number, is derived from the high 11 bits [16:6] in the key. And looking up the group number and the group validity identification in the storage space corresponding to the first index in the first table, namely the first group number and the first group validity identification.
If the first group of validity flags group _ vld is 0, determining that no target threshold corresponding to the keyword exists in the first table, and not searching.
Step S13, if the first group validity flag is valid, looking up a table entry corresponding to a second index in a second table stored in the FPGA chip, where each table entry is used to store a numerical value, the large group with each group validity flag being valid includes a plurality of table entries, and the second index is obtained from the second part of the keyword and the first group number.
In this step, if the first group validity flag is valid, a second index is obtained from the first group number and the second part of the keyword, and a table entry corresponding to the second index is searched in a second table stored in the FPGA chip.
The following steps are explained by using the above examples of searching for the corresponding threshold N in different messages:
if the first group validity flag group _ vld is 1, it indicates that the first group number is valid, and the 8-bit first group number and the second part of the key, i.e. the 2 nd to 5 th bits [5:2], are combined into 12-bit binary data, i.e. the second index. Referring to fig. 3, the second table is searched according to the second index, and 4 sets of N values and corresponding vld identifiers in the corresponding storage space are obtained: vld0, N0; vld1, N1; vld2, N2; vld3, N3.
Step S14, determining the target value according to the values in the table entry.
The number of the table entry may be multiple or one.
In an embodiment, when each of the entries stores M values and a value validity flag corresponding to each of the values, where M is a natural number, the determining the target value according to the values in the entries includes:
determining a value and a value validity identifier corresponding to an index value of a third index in the table entry, where the third index is obtained from a third part of the keyword, the index value of the third index is one of M index values, and the M index values are in one-to-one correspondence with the M values in the table entry;
and if the value validity identification is valid, determining the value as a target value.
And if the value validity identification is invalid, determining that no target value corresponding to the keyword exists.
The above description is given by using the example of searching for the corresponding threshold N in different messages:
each entry of fig. 3 stores 4 values and a value validity flag corresponding to each of the values, and then a third index is obtained according to a third part of the key, i.e. two lower bits [1:0], where the index value of the third index may be one of the 4 values: 00, 01, 10, 11, i.e. 0, 1, 2, 3. The destination port number at this time further includes: the third part bits (dport [1:0 ]). If the index value is 0, then N0 is determined to be the threshold value to be looked up; if the index value is 1, determining N1 as the threshold value to be searched; if the index value is 2, then N2 is determined to be the threshold value to be looked up; if the index value is 3, then N3 is determined to be the threshold value to be looked up. Finally, whether the threshold N is valid or not is determined according to the numerical value validity identifier vld, wherein the vld is 0, so that the N value is invalid, and a target numerical value corresponding to the keyword does not exist, namely the N value is not configured in the message; and vld is 1, which means that the value of N is effective, and N is determined as a target numerical value, namely the value of N is a search result.
In an embodiment, in a case that a value and a value validity flag corresponding to the value are stored in each of the entries, the determining the target value according to the values in the entries includes:
and if the value validity identification is valid, determining the value as a target value.
In this embodiment, S12 and S13 are two-stage pipeline operations, and for the operations of target values corresponding to multiple lookup keys, two-stage pipeline parallel processing is performed, that is, one lookup operation is performed in S12, and the other lookup operation is performed in S13, so that, in terms of time, the operation of target value corresponding to one lookup key only takes one lookup time. In addition, even if two-stage pipeline parallel processing is not used, the technical scheme disclosed by the invention only needs two times of searching, and compared with multiple times of searching of dichotomy searching operation, the searching speed is greatly improved.
According to the technical scheme provided by the embodiment of the disclosure, the keywords are grouped, and then the numerical values and the indexes are subjected to many-to-one mapping relationship, so that the one-to-one mapping of the numerical values and the indexes is avoided, and the storage resources occupied by the mapping are reduced; the keyword is divided into a plurality of parts, and the parts of the keyword are sequentially indexed, so that the searching times are reduced, the searching speed is improved, and the balanced optimization of the area and the speed is realized.
As shown in fig. 6, fig. 6 is a block diagram of an entry lookup apparatus according to an embodiment of the present disclosure, where the apparatus includes:
an obtaining module 21, configured to obtain the keyword;
the first-level lookup module 22 is configured to lookup a first group number and a first group validity identifier corresponding to a first index in a first table stored in the FPGA chip, where the first table is used to store a group number of a large group to which each keyword belongs and a group validity identifier of the large group, and the first index is obtained from a first part of the keyword;
a secondary searching module 23, configured to search, if the first group validity flag is valid, a table entry corresponding to a second index in a second table stored in an FPGA chip, where each table entry is used to store a numerical value, the large group with each group validity flag being valid includes multiple table entries, and the second index is obtained from the second part of the keyword and the first group number;
a determining module 24, configured to determine the target value according to the value in the table entry.
The device provided by the embodiment of the disclosure can group the keywords, and further establish a mapping relationship between a plurality of values and the indexes, thereby avoiding one-to-one mapping between the values and the indexes, and reducing storage resources occupied by the mapping; the keyword is divided into a plurality of parts, and the parts of the keyword are sequentially indexed, so that the searching times are reduced, the searching speed is improved, and the balanced optimization of the area and the speed is realized.
In one example, the obtaining module, when configured to obtain the keyword, includes: receiving a target message to be processed; extracting the keywords from the target message, wherein the keywords comprise: the protocol type and the destination port number of the target message, wherein the binary form of the destination port number at least comprises: a first part of bits of a destination port number and a second part of bits of the destination port number; the first portion of the keyword comprises: a first part of bits of the protocol type and the destination port number; the second portion of the keyword comprises: and the second part of bits of the destination port number.
In an example, when each of the entries stores M values and a value validity flag corresponding to each of the values, where M is a natural number, the determining module, when configured to determine the target value according to the values in the entries, includes: determining a value and a value validity identifier corresponding to an index value of a third index in the table entry, where the third index is obtained from a third part of the keyword, the index value of the third index is one of M index values, and the M index values are in one-to-one correspondence with the M values in the table entry; and if the value validity identification is valid, determining the value as a target value. And if the value validity identification is invalid, determining that no target value corresponding to the keyword exists.
In an example, in a case that a value and a value validity flag corresponding to the value are stored in each of the entries, the determining module, when configured to determine the target value according to the values in the entries, includes: and if the value validity identification is valid, determining the value as a target value.
On the basis of the above device embodiment, the device may be an FPGA chip.
The implementation process of the functions and actions of the modules is specifically described in the implementation process of the corresponding steps in the method, and is not described herein again.
The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Other embodiments of the present description will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This specification is intended to cover any variations, uses, or adaptations of the specification following, in general, the principles of the specification and including such departures from the present disclosure as come within known or customary practice within the art to which the specification pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the specification being indicated by the following claims.
It will be understood that the present description is not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.
The above description is only a preferred embodiment of the present disclosure, and should not be taken as limiting the present disclosure, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A method for searching table items is characterized in that the method is applied to searching target numerical values corresponding to keywords in a Field Programmable Gate Array (FPGA) chip, and the method comprises the following steps:
acquiring the keyword;
searching a first group number and a first group validity identification corresponding to a first index in a first table stored in an FPGA chip, wherein the first table is used for storing the group number of a large group to which each keyword belongs and the group validity identification of the large group, and the first index is obtained from a first part of the keyword;
if the first group validity identifier is valid, searching a table entry corresponding to a second index in a second table stored in an FPGA chip, wherein each table entry is used for storing a numerical value, the large group with each group validity identifier being valid comprises a plurality of table entries, and the second index is obtained from a second part of the keyword and the first group number;
and determining the target value according to the values in the table items.
2. The method of claim 1, wherein the obtaining the keyword comprises:
receiving a target message to be processed;
extracting the keywords from the target message, wherein the keywords comprise: the protocol type and the destination port number of the target packet, wherein the destination port number at least includes: a first part of bits and a second part of bits;
the first portion of the keyword comprises: a first portion of bits of the protocol type and the destination port number;
the second portion of the keyword comprises: a second part of bits of the destination port number.
3. The method of claim 1, wherein, when each of the entries stores M values and a value validity indicator corresponding to each of the values, where M is a natural number, the determining the target value according to the values in the entries comprises:
determining a value and a value validity identifier corresponding to an index value of a third index in the table entry, where the third index is obtained from a third part of the keyword, the index value of the third index is one of M index values, and the M index values are in one-to-one correspondence with the M values in the table entry;
and if the value validity identification is valid, determining the value as a target value.
4. The method of claim 3, further comprising:
and if the value validity identification is invalid, determining that no target value corresponding to the keyword exists.
5. The method of claim 1, wherein, in the case that each of the entries stores a value and a value validity indicator corresponding to the value, the determining the target value according to the values in the entries comprises:
and if the value validity identification is valid, determining the value as a target value.
6. An item lookup apparatus, wherein the apparatus is applied to lookup a target value corresponding to a keyword, and includes:
the acquisition module is used for acquiring the keywords;
the first-level searching module is used for searching a first group number and a first group validity identification corresponding to a first index in a first table stored in an FPGA chip, the first table is used for storing the group number of a large group to which each keyword belongs and the group validity identification of the large group, and the first index is obtained from a first part of the keyword;
a second-level lookup module, configured to, if the first group validity flag is valid, lookup a table entry corresponding to a second index in a second table stored in an FPGA chip, where each table entry is used to store a numerical value, the large group with each group validity flag being valid includes a plurality of table entries, and the second index is obtained from a second part of the keyword and the first group number;
and the determining module is used for determining the target numerical value according to the numerical value in the table entry.
7. The apparatus of claim 6, wherein the obtaining module, when configured to obtain the keyword, comprises:
receiving a target message to be processed;
extracting the keywords from the target message, wherein the keywords comprise: the protocol type and the destination port number of the target message, wherein the binary form of the destination port number at least comprises: a first part of bits of a destination port number and a second part of bits of the destination port number;
the first portion of the keyword comprises: a first part of bits of the protocol type and the destination port number;
the second portion of the keyword comprises: and the second part of bits of the destination port number.
8. The apparatus of claim 6, wherein, when each of said entries stores M values and a value validity indicator corresponding to each of said values, said M being a natural number, said determining module, when configured to determine said target value based on the values in said entries, comprises:
determining a value and a value validity identifier corresponding to an index value of a third index in the table entry, where the third index is obtained from a third part of the keyword, the index value of the third index is one of M index values, and the M index values are in one-to-one correspondence with the M values in the table entry;
and if the value validity identification is valid, determining the value as a target value.
9. The apparatus of claim 8, wherein the determining module is further configured to:
and if the value validity identification is invalid, determining that no target value corresponding to the keyword exists.
10. The apparatus of claim 6, wherein, when each of said entries stores a value and a value validity indicator corresponding to said value, said determining module, when configured to determine said target value based on values in said entries, comprises:
and if the value validity identification is valid, determining the value as a target value.
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