CN112636717A - Impedance calibration circuit and method - Google Patents
Impedance calibration circuit and method Download PDFInfo
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- CN112636717A CN112636717A CN202011612009.XA CN202011612009A CN112636717A CN 112636717 A CN112636717 A CN 112636717A CN 202011612009 A CN202011612009 A CN 202011612009A CN 112636717 A CN112636717 A CN 112636717A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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- H03H11/02—Multiple-port networks
- H03H11/28—Impedance matching networks
- H03H11/30—Automatic matching of source impedance to load impedance
Abstract
An impedance calibration circuit and method provided by the embodiments of the present application, the impedance calibration circuit includes: the calibration unit is used for calibrating a pull-up resistor device to be calibrated, a first connecting end of the pull-up resistor device to be calibrated is connected with the calibration unit, and a second connecting end of the pull-up resistor device to be calibrated is connected with a power supply end; the calibration unit is used for calibrating the pull-down resistor device to be calibrated, a first connecting end of the pull-down resistor device to be calibrated is connected with the calibration unit, a second connecting end of the pull-down resistor device to be calibrated is connected with a third connecting end of the pull-up resistor device to be calibrated, and the third connecting end of the pull-down resistor device to be calibrated is grounded; the calibration unit comprises a voltage receiving end and a calibration code output end, and receives the first voltage and the second voltage through the voltage receiving end. The resistor calibration device comprises a calibration unit, a calibration unit and a calibration pull-up resistor device.
Description
Technical Field
The embodiments of the present application relate to the field of integrated circuit design, and in particular, but not limited to, an impedance calibration circuit and method.
Background
With the development of electronic information technology, the requirement for the resistance of the transistor inside the chip is higher and higher, for example, in the manufacturing process of various transistors, since the resistance of the resistor inside the transistor varies greatly with the process, it is generally difficult to directly manufacture an on-chip resistor with accurate resistance, and therefore, it is necessary to calibrate the resistance of the on-chip resistor additionally, and how to calibrate the impedance inside the chip better is an urgent problem to be solved.
Disclosure of Invention
The impedance calibration circuit and the method provided by the embodiment of the application mainly solve the technical problem of how to simplify the impedance calibration process.
In a first aspect, an embodiment of the present application provides an impedance calibration circuit, including: the calibration unit is used for calibrating a pull-up resistor device to be calibrated, a first connecting end of the pull-up resistor device to be calibrated is connected with the calibration unit, and a second connecting end of the pull-up resistor device to be calibrated is connected with a power supply end; the calibration unit is used for calibrating the pull-down resistor device to be calibrated, a first connecting end of the pull-down resistor device to be calibrated is connected with the calibration unit, a second connecting end of the pull-down resistor device to be calibrated is connected with a third connecting end of the pull-up resistor device to be calibrated, and the third connecting end of the pull-down resistor device to be calibrated is grounded; the calibration unit is used for obtaining a first calibration code and a second calibration code according to the first voltage and the second voltage, and the calibration unit is used for calibrating the resistance value of the pull-up resistor to be calibrated by using the first calibration code and calibrating the resistance value of the pull-down resistor to be calibrated by using the second calibration code.
Optionally, the impedance calibration circuit further includes a calibration resistor, a first connection end of the calibration resistor is connected to the pull-up resistor device to be calibrated and the calibration unit, respectively, and a second connection end of the calibration resistor is grounded.
Optionally, the pull-up resistor device to be calibrated includes a plurality of pull-up sub-resistor devices, each of the pull-up sub-resistor devices includes a first switch element and a first resistor, a first connection end of the first switch element is connected to the power supply end, a control end of the first switch element is connected to the calibration unit, a second connection end of the first switch element is connected to a first connection end of the first resistor, and a second connection end of the first resistor is connected to the calibration resistor and the pull-down resistor device to be calibrated, respectively.
Optionally, the first switch element is a PMOS transistor, a source of the PMOS transistor is connected to the power supply terminal, a gate of the PMOS transistor is connected to the calibration unit, and a drain of the PMOS transistor is connected to the first connection terminal of the first resistor.
Optionally, the pull-down resistor device to be calibrated includes a plurality of pull-down sub-resistor devices, each of the pull-down sub-resistor devices includes a second resistor and a second switch element, a first connection end of the second resistor is connected to the first resistor, a second connection end of the second resistor is connected to the first connection end of the second switch element, a control end of the second switch element is connected to the calibration unit, and a second connection end of the second switch element is grounded.
Optionally, the second switch element is an NMOS transistor, a source of the NMOS transistor is connected to the second connection end of the second resistor, a gate of the NMOS transistor is connected to the calibration unit, and a drain of the NMOS transistor is grounded.
Optionally, the impedance calibration circuit further includes a calibration resistor, a first connection end of the calibration resistor is connected to the pull-down resistor device to be calibrated and the calibration unit, respectively, and a second connection end of the calibration resistor is grounded.
Optionally, the calibration unit includes a comparator, a logic processing unit, a converter, and a latch; the comparator comprises a first voltage receiving end and a second voltage receiving end, the first voltage receiving end is used for receiving the first voltage or the second voltage, the second voltage receiving end is used for receiving the reference voltage, the comparator is used for comparing the first voltage with the reference voltage to obtain the first calibration code, and comparing the second voltage with the reference voltage to obtain the second calibration code; the first connection end of the logic processing unit is connected with the comparator, the second connection end of the logic processing unit is connected with the first connection end of the converter, the second connection end of the converter is connected with the first connection end or the second connection end of the latch, the second connection end of the latch is connected with the pull-up resistor to be calibrated, and the latch is used for storing the first calibration code or the second calibration code transmitted by the converter.
In a second aspect, an embodiment of the present application further provides an impedance calibration method, which is applied to the impedance calibration circuit of the first aspect, and the method includes: receiving a first voltage and a second voltage, wherein the first voltage is the output voltage of the pull-up resistor device to be calibrated, and the second voltage is the output voltage of the pull-down resistor device to be calibrated; obtaining a first calibration code and a second calibration code according to the first voltage and the second voltage; and calibrating the resistance value of the pull-up resistor device to be calibrated by using the first calibration code, and calibrating the resistance value of the pull-down resistor device to be calibrated by using the second calibration code.
Optionally, the calibrating the resistance of the pull-up resistor device to be calibrated by using the first calibration code, and calibrating the resistance of the pull-down resistor device to be calibrated by using the second calibration code, includes: and determining the number of effective resistors according to the first calibration code and the second calibration code, and calibrating the resistance values of the pull-up resistor device to be calibrated and the pull-down resistor device to be calibrated according to the number of the effective resistors.
The impedance calibration circuit comprises a pull-up resistor device to be calibrated, a pull-down resistor device to be calibrated and a calibration unit, wherein a first connection end of the pull-up resistor device to be calibrated is connected with the calibration unit, a second connection end of the pull-up resistor device to be calibrated is connected with a power supply end, a first connection end of the pull-down resistor device to be calibrated is connected with the calibration unit, a second connection end of the pull-down resistor device to be calibrated is connected with a third connection end of the pull-up resistor device to be calibrated, a third connection end of the pull-down resistor device to be calibrated is grounded, the calibration unit comprises a voltage receiving end and a calibration code output end, the calibration unit receives a first voltage and a second voltage through the voltage receiving end, the first voltage is an output voltage of the pull-up resistor device to be calibrated, the calibration unit is configured to calibrate a resistance value of the pull-up resistor device to be calibrated by using the first calibration code, and calibrate a resistance value of the pull-down resistor device to be calibrated by using the second calibration code. The calibration unit is used for calibrating the pull-up resistor device, the pull-down resistor device and the calibration unit, so that the calibration of the resistor can be realized more simply and effectively, and the impedance calibration condition can be simplified to a certain extent.
Additional features and corresponding advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic diagram of a basic impedance calibration circuit;
FIG. 2 is a diagram of a pull-up resistor calibration structure in a basic impedance calibration circuit;
FIG. 3 is a schematic diagram of a pull-up resistor calibration in a basic impedance calibration circuit;
FIG. 4 is a schematic diagram of a pull-down resistor calibration in the basic impedance calibration circuit;
fig. 5 is a schematic structural diagram of an impedance calibration circuit according to an embodiment of the present application;
fig. 6 is a schematic physical structure diagram of an impedance calibration circuit according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a pull-up resistor device to be calibrated in an impedance calibration circuit according to an embodiment of the present application;
fig. 8 is a schematic diagram of a pull-down resistor device to be calibrated in an impedance calibration circuit according to an embodiment of the present application;
FIG. 9 is a flowchart of a method for calibrating impedance according to an embodiment of the present application;
fig. 10 is a block diagram of a circuit corresponding to a pull-up resistor device to be calibrated in an impedance calibration method according to an embodiment of the present application;
fig. 11 is a circuit block diagram corresponding to a pull-down resistor device to be calibrated in an impedance calibration method according to an embodiment of the present application.
Detailed Description
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Currently, to ensure signal integrity, chip high speed io (input output) usually requires impedance of a transmitting end and a receiving end to match the impedance with a channel characteristic impedance, wherein the channel characteristic impedance is typically 50 Ω. However, since the difference in the manufacturing process may cause the transistor and the resistor in the chip to have a deviation of about 20%, the impedance needs to be calibrated to avoid the influence of the deviation on the signal integrity. Because the IO in an FPGA (Field-Programmable Gate Array) generally needs to support a very large number of protocol requirements, and the level standards of different protocols make the transistors operate in different voltage regions, and the output impedance of the transistors may also be different. Therefore, a single impedance calibration condition cannot guarantee general applicability or meet the accuracy requirement. Also, selecting different calibration adjustments for different protocols can be costly. In addition, because the IO resources are limited, the fewer the number of enabled IOs for calibration, the more the resources that can be provided to the application side, so reducing the IO resources used for calibration is an urgent problem to be solved.
The basic structure of the existing impedance calibration circuit is shown in fig. 1, R in fig. 1uAnd RdRespectively pull-up and pull-down output impedance, MP<m:0>To adjust the control code of the pull-up impedance, MP<m:0>For controlling the number of branches turned on, e.g. MP<m:0>11000, which means 2 channels open and 3 other channels closed; MN (Mobile node)<m:0>For adjusting the control code of the pull-down impedance, MN<m:0>And the number of the branches is used for controlling the opening and the conduction. Due to the requirement of impedance matching, R needs to be guaranteeduAnd RdA reliable accuracy range is achieved so that the pull-up resistor and the pull-down resistor need to be calibrated separately.
To calibrate the pull-up output impedance RuFor example (when the pull-down path is closed), the conventional calibration method is shown in FIG. 2, where V in FIG. 2refIs a reference voltage, VoutFor the output voltage, the function of the calibration circuit module is to compare VoutAnd VrefThe voltage of the two is judged, and the control code MP is obtained by comparison<m:0>Adjusting the number of the conduction paths to adjust the driving strength so that VoutThe output voltage is equal to the set reference voltage Vref。
When the prior art is used for calibrating the impedance of different protocols, different resistors and voltages are required to be externally connected, the cost of chip configuration is increased to a certain extent, and the applicability is lower. Protocol 1 requires a common mode level of 0.5VCCIO(VCCIO1.2V), then the external VC needs to be grounded when Vout is calibrated to 0.5VCCIOAt this time Ru＝RrefAnd common mode level of 0.5VCCIO. Protocol 2 also requires a common mode level of 0.75VCCIO(VCCIO1.2V), it is necessary to connect the external VC to 0.5VCCIOWhen Vout is calibrated to 0.75VCCIOThen at this time Ru＝RrefAnd common mode level of 0.75VCCIO. Calibration circuits for protocol 1 and protocol 2 as shown in fig. 3 and 4, it can be seen from fig. 3 and 4 that the common mode level requirement is 0.5VCCIOWhen necessary, willExternal VC connects VCCIOAnd the common mode level is required to be 0.5VCCIOWhen the external VC is required to be connected with 0.75VCCIO。
In summary, in the prior art, when impedance is calibrated, different protocols require different potentials provided by a system, and the pull-up IO and the pull-down IO need to be connected with external resistors at the same time, so that the calibration of the pull-up resistor and the pull-down resistor can be achieved respectively, so that the chip environment configuration cost is increased to a certain extent, the user experience is not high, and the applicability is also low.
In view of the above problems, the inventor proposes an impedance calibration circuit and method provided in the embodiments of the present application, and the embodiments of the present application can simplify the implementation conditions of impedance calibration by combining the pull-up resistor device to be calibrated, the pull-down resistor device to be calibrated, and the calibration unit, and can reduce the requirements for plate making to a certain extent.
Referring to fig. 5, for an impedance calibration circuit according to an embodiment of the present application, the impedance calibration circuit 100 may include a pull-up resistance device 110 to be calibrated, a pull-down resistance device 120 to be calibrated, and a calibration unit 130.
In some embodiments, the first connection terminal 111 of the pull-up resistance device 110 to be calibrated is connected to the calibration unit 130, and the second connection terminal 112 of the pull-up resistance device 110 to be calibrated is connected to the power terminal 114. In addition, the first connection terminal 121 of the pull-down resistor device 120 to be calibrated is connected to the calibration unit 130, the second connection terminal 122 of the pull-down resistor device 120 to be calibrated is connected to the third connection terminal 113 of the pull-up resistor device 110 to be calibrated, and the third connection terminal 123 of the pull-down resistor device 120 to be calibrated is grounded.
In this embodiment, the calibration unit 130 may include a voltage receiving terminal 131 and a calibration code output terminal 132, the calibration unit 130 receives a first voltage and a second voltage through the voltage receiving terminal 131, the first voltage is an output voltage of the pull-up resistor device 110 to be calibrated, the second voltage is an output voltage of the pull-down resistor device 120 to be calibrated, the calibration unit 130 obtains a first calibration code and a second calibration code according to the first voltage and the second voltage, and the calibration unit 130 is configured to calibrate the resistance of the pull-up resistor device 110 to be calibrated by using the first calibration code, and calibrate the resistance of the pull-down resistor device 120 to be calibrated by using the second calibration code.
For a clearer understanding of the relationship between the pull-up resistor device 110 to be calibrated, the pull-down resistor device 120 to be calibrated, and the calibration unit 130, the embodiment of the present application provides a physical structure diagram of the calibration circuit shown in fig. 6. As shown in fig. 6, in other embodiments, the impedance calibration circuit 100 may further include a calibration resistor 140 in addition to the pull-up resistor device 110 to be calibrated, the pull-down resistor device 120 to be calibrated, and the calibration unit 130, wherein a first connection end of the calibration resistor 140 is connected to the pull-up resistor device 110 to be calibrated and the calibration unit 130, respectively, and a second connection end of the calibration resistor 140 is connected to Ground (GND).
By one approach, the pull-up resistor device to be calibrated 110 includes a plurality of pull-up sub-resistor devices 115, each of the pull-up sub-resistor devices 115 (R)u) Includes a first switching element 1151 and a first resistor 1152, a first connection terminal of the first switching element 1151 is connected to the power supply terminal 114 (V)CCIO) A control terminal of the first switching element 1151 is connected to the calibration unit 130, a second connection terminal of the first switching element 1151 is connected to a first connection terminal of the first resistor 1152, and second connection terminals of the first resistor 1152 are respectively connected to the calibration resistors 140 (R)ref) And is connected to the pull-down resistor device to be calibrated 120.
In a specific embodiment, the first switch element 1151 is a PMOS transistor, a source of the PMOS transistor is connected to the power supply terminal, a gate of the PMOS transistor is connected to the calibration unit 130, and a drain of the PMOS transistor is connected to the first connection terminal of the first resistor 1152. The first switch element 1152 may be an NMOS transistor, and the type of the switch that the first switch element 1152 is specific is not specifically limited, and may be selected according to actual circumstances.
In other embodiments, the pull-down resistor device 1 to be calibrated20 includes a plurality of pull-down sub-resistor devices 124 (R)d) Each of the pull-down sub-resistor devices 124 includes a second resistor 1241 and a second switch element 1242, a first connection terminal of the second resistor 1241 is connected to the first resistor 1152, a second connection terminal of the second resistor 1241 is connected to a first connection terminal of the second switch element 1242, a control terminal of the second switch element 1242 is connected to the calibration unit 130, and a second connection terminal of the second switch element 1242 is connected to Ground (GND).
Alternatively, the second switch element 1242 is an NMOS transistor, a source of the NMOS transistor may be connected to the second connection terminal of the second resistor 1241, a gate of the NMOS transistor may be connected to the calibration unit 130, and a drain terminal of the NMOS transistor is grounded. The second switching element 1242 may be a PMOS transistor, and the type of the second switching element 1242 is not specifically limited and may be selected according to actual circumstances.
In order to more clearly understand the calibration process of the corresponding resistance values of the pull-up resistor device to be calibrated and the pull-down resistor device to be calibrated, the schematic diagrams of the structures shown in fig. 7 and 8 are given. Fig. 7 is a schematic structural diagram of a pull-up resistor device to be calibrated, and it can be seen from fig. 7 that the calibration unit 130 may include a comparator 133, a logic processing unit 134, a converter 135 and a latch 136.
In some embodiments, the comparator 133 may include a first voltage receiving terminal for receiving the first voltage or the second voltage (V)out) Said second voltage receiving terminal is used for receiving said reference voltage (V)ref) The first voltage receiving terminal may include a first sub-voltage receiving terminal and a second sub-voltage receiving terminal, and the calibration unit 130 is connected to the pull-up resistance device to be calibrated 110 through the first sub-voltage receiving terminal and receives an output voltage of the pull-up resistance device to be calibrated, which may be a first voltage; the calibration unit 130 is connected to the pull-down resistor device 120 to be calibrated through the second sub-voltage receiving terminal, and receives an output voltage of the pull-down resistor device to be calibrated, where the output voltage may be used as a second voltage. The comparator 133 is configured to compare the first voltage with the reference voltage to obtain the first calibration code (Mp)<m:0>) And comparing the second voltage with the reference voltage to obtain the second calibration code (Mn)<m:0>)。
In addition, the first connection end of the logic processing unit 134 is connected to the comparator 133, the second connection end of the logic processing unit 134 is connected to the first connection end of the converter 135, the logic processing unit 134 may also be referred to as successive approximation logic, and the logic processing unit 134 is configured to receive the comparison result sent by the comparator 133 and receive a clock signal (CLK), and when the comparison result sent by the comparator 133 does not meet a preset condition, successively adjust the first voltage or the second voltage. Therefore, the impedance calibration circuit in the embodiment of the present invention may further include a clock generation sub-circuit, which is connected to the logic processing unit 134 and configured to provide a clock signal to the logic processing unit 134.
As a mode, the second connection terminal of the converter 135 is connected to the first connection terminal or the second connection terminal of the latch, and the converter 135 is used to control whether to calibrate the resistance of the pull-up resistor device 110 to be calibrated or calibrate the resistance of the pull-down resistor device 120 to be calibrated, that is, when the converter 135 is connected to IO1 (output of the pull-up resistor device 110 to be calibrated), the impedance calibration circuit 100 adjusts the resistance of the pull-up resistor device 110 to be calibrated in the pull-up branch, at this time, the pull-down branch is in a closed state, that is, the second calibration code (Mn < m:0>) of the pull-down branch is set to 0, and at this time, the pull-down branch where the pull-down resistor device 120 to be calibrated is located is in a closed state. Optionally, a second connection terminal of the latch 136 is connected to the pull-up resistor device 110 to be calibrated, and the latch 136 is configured to store the first calibration code or the second calibration code transmitted by the converter 135.
In summary, when the resistance value of the pull-up resistor device 110 to be calibrated is calibrated, the input of the comparator 133 is the reference voltage (Vref) and the first voltage (Vout1), wherein the first voltage is the output voltage of the pull-up resistor device 110 to be calibrated, and the converter 135 is connected to the first calibration code value (Mp < m:0>) of the IO1 corresponding to the pull-up resistor device 110 to be calibrated. The internal pull-down branch (the branch in which the pull-down resistive device 120 is to be calibrated) is in the OFF state by setting the second calibration code value (Mn < m:0>) to 0.
In the embodiment of the present invention, the comparator 133 and the logic processing unit 134 may obtain the first calibration code (Mp < m:0>), and then the resistance in the pull-up resistance device to be calibrated 110 may be adjusted from a high level to a low level based on the first calibration code, so that the first voltage Vout gradually approaches the reference voltage Vref until the last bit is quantized. The latch stores the acquired first calibration code Mp < m:0> value. Therefore, the resistance value of the pull-up resistor to be calibrated can be calibrated. After the resistance of the pull-up resistor device 110 to be calibrated is calibrated, the converter 130 switches to Mn < m:0> (branch of the pull-down resistor device 120 to be calibrated) of IO2, and one end of the comparator 133 is connected to the reference voltage Vref, and the other end is connected to the voltage output end of the pull-down resistor device 120 to be calibrated, so as to receive the second voltage.
As one way, the structure of the pull-down resistor device 120 to be calibrated is shown in fig. 8, and as can be seen from fig. 8, when the resistance value of the pull-down resistor device 120 to be calibrated is calibrated, it is mainly performed based on the first calibration code obtained by the pull-up resistor device 110 to be calibrated. When the resistance value of the pull-down resistor device 120 to be calibrated is calibrated, the first calibration code Mp < m:0> obtained by calibrating the pull-up resistor device 110 to be calibrated is mainly mapped to Mp < m:0> of the IO 2. The comparator 133 and the logic processing unit 134 obtain a second calibration code Mn < m:0>, and then, the resistance in the pull-down resistor 120 to be calibrated can be adjusted from high to low based on the second calibration code, so that the second voltage Vout gradually approaches the reference voltage Vref until the last bit is quantized. At this time, the latch stores the acquired second calibration code Mn < m:0 >.
In some embodiments, the first calibration code value Mp output by the calibration unit 130<m:0>And a second calibration code value Mn<m:0>The output impedance is the calibrated pull-up resistor R corresponding to the driving of each segmentuAnd a pull-down resistor RdThe resistance value of (c).
In other embodiments, the calibration resistor 140 included in the impedance calibration circuit 100 may also be connected to the pull-down resistor device 120 to be calibrated (not shown), specifically, a first connection terminal of the calibration resistor 140 is connected to the pull-down resistor device 120 to be calibrated and the calibration unit 130, respectively, and a second connection terminal of the calibration resistor 140 is connected to ground. In addition, the pull-down resistance device 120 to be calibrated includes a plurality of pull-down sub-resistance devices 124, each of the pull-down sub-resistance devices 124 may include a second switch element 1242 and a second resistor 1241, a first connection terminal of the second switch element 1242 is connected to the power source terminal 114, a control of the second switch element 1242 is connected to the calibration unit 130, a second connection terminal of the second switch element 1242 is connected to a first connection terminal of the second resistor 1241, and a second connection terminal of the second resistor 1242 is connected to the calibration resistor 140 and the pull-up resistance device 110 to be calibrated, respectively. The second switching element 1242 may be a PMOS transistor or an NMOS transistor.
Alternatively, the pull-up resistor device to be calibrated 110 includes a plurality of pull-up sub-resistor devices 115, each of the pull-up sub-resistor devices 115 (R)u) The calibration circuit comprises a first switch element 1151 and a first resistor 1152, a first connection end of the first resistor 1152 is connected with the second resistor 1242, a second connection end of the first resistor 1152 is connected with a first connection end of the first switch element 1151, a control end of the first switch element 1151 is connected with the calibration unit 130, and a connection end of the first switch element 1151 is grounded. The first switching element 1242 may be a PMOS transistor or an NMOS transistor.
To sum up, in the embodiment of the present invention, the calibration resistor 140 may be connected to the pull-up resistor device 110 to be calibrated, the resistance of the pull-up resistor device 110 to be calibrated is calibrated through the calibration resistor 140, and then the resistance of the pull-down resistor device 120 to be calibrated is calibrated based on the calibration result of the pull-up resistor device 110 to be calibrated; or in the embodiment of the present invention, a calibration resistor 140 may be connected to the pull-down resistor device 120 to be calibrated, the resistance of the pull-down resistor device 120 to be calibrated is calibrated through the calibration resistor 140, and then the resistance of the pull-up resistor device 110 to be calibrated is calibrated based on the calibration result of the pull-down resistor device 120 to be calibrated. It can be seen that the calibration resistor 140 may be connected to the pull-up resistor device 110 to be calibrated, or may be connected to the pull-down resistor device 120 to be calibrated, specifically, connected to the pull-up resistor device 110 to be calibrated or connected to the pull-down resistor device 120 to be calibrated, and this may be selected according to the actual situation without explicit limitation.
The impedance calibration circuit provided by the embodiment of the application comprises a pull-up resistor device to be calibrated, a pull-down resistor device to be calibrated and a calibration unit, wherein a first connection end of the pull-up resistor device to be calibrated is connected with the calibration unit, a second connection end of the pull-up resistor device to be calibrated is connected with a power end, a first connection end of the pull-down resistor device to be calibrated is connected with the calibration unit, a second connection end of the pull-down resistor device to be calibrated is connected with a third connection end of the pull-up resistor device to be calibrated, a third connection end of the pull-down resistor device to be calibrated is grounded, the calibration unit comprises a voltage receiving end and a calibration code output end, the calibration unit receives a first voltage and a second voltage through the voltage receiving end, and the first voltage is the output voltage of the pull-up resistor device to be calibrated, the calibration unit is configured to calibrate a resistance value of the pull-up resistor device to be calibrated by using the first calibration code, and calibrate a resistance value of the pull-down resistor device to be calibrated by using the second calibration code. The calibration unit is used for calibrating the pull-up resistor device, the pull-down resistor device and the calibration unit, so that the resistor can be calibrated more simply and effectively, and the impedance calibration condition is simplified to a certain extent.
Referring to fig. 9, a flowchart of a method for calibrating impedance according to an embodiment of the present invention is provided, where the flowchart is applied to the impedance calibration circuit, and it can be seen from fig. 9 that the method may include steps S210 to S230.
Step S210: receiving a first voltage and a second voltage, wherein the first voltage is an output voltage of the pull-up resistor device to be calibrated, and the second voltage is an output voltage of the pull-down resistor device to be calibrated.
Step S220: and obtaining a first calibration code and a second calibration code according to the first voltage and the second voltage.
As a manner, in the embodiment of the present invention, when the first voltage is obtained, the first voltage may be compared with a reference voltage, and whether the first voltage is greater than the reference voltage is determined, if the first voltage is greater than the reference voltage, a bit number corresponding to the first calibration code value is 1, and if the first voltage is less than the reference voltage, a bit number corresponding to the first calibration code value is 0.
In addition, when the first voltage is greater than the reference voltage, the embodiment of the invention may adjust the first voltage, that is, increase the first voltage, and then compare the increased first voltage with the reference voltage again, so as to obtain another bit value corresponding to the first calibration code, where the number of comparison times is several bits, and the number of comparison times may be selected according to the actual situation, where no explicit limitation is made here. For example, when the pull-up resistor is calibrated, the reference voltage is compared with the first voltage and adjusted five times, then the first voltage is equal to the reference voltage, the first voltage is greater than the reference voltage for the first two times, and the first voltage is less than the reference voltage for the last three times, the obtained first calibration code is 11000, that is, MP < m:0> is 11000, and it is known from the above description that MP < m:0> controls the number of the corresponding branches of the pull-up resistor to be calibrated, which are opened and conducted. In addition, the embodiment of the invention can also judge whether the first voltage is greater than the reference voltage, if so, the first voltage is correspondingly increased, so that the calibration of the pull-up resistor or the pull-down resistor is realized.
Similar to the first calibration code obtaining process, in the embodiment of the present invention, when the second voltage is obtained, the second voltage may be compared with the reference voltage, and whether the second voltage is greater than the reference voltage is determined, if so, the bit number corresponding to the second calibration code value is 1, and if the second voltage is less than the reference voltage, the bit number corresponding to the second calibration code value is 0. In addition, when the second voltage is greater than the reference voltage, the embodiment of the invention can adjust the second voltage, that is, increase the second voltage, and then compare the increased second voltage with the reference voltage again, so as to obtain another bit value corresponding to the second calibration code, and if the comparison is performed for a plurality of times, the number of bits of the corresponding code value is several bits. For example, when the pull-down resistor is calibrated, the reference voltage and the second voltage are compared and adjusted five times, the second voltage of the first time is greater than the reference voltage, and the second voltage of the second time is less than the reference voltage, the obtained second calibration code is 11100, that is, MN < m:0> -11100, and it is known from the above description that MN < m:0> controls the number of branches corresponding to the pull-down resistor to be calibrated, which is turned on. The adjustment of the pull-down resistor is similar to the adjustment of the pull-up resistor, and is not described in detail here.
Step S230: and calibrating the resistance value of the pull-up resistor device to be calibrated by using the first calibration code, and calibrating the resistance value of the pull-down resistor device to be calibrated by using the second calibration code.
In some embodiments, after the first calibration code and the second calibration code are obtained, the resistance value of the pull-up resistor device to be calibrated may be calibrated by using the first calibration code, and the resistance value of the pull-down resistor device to be calibrated may be calibrated by using the second calibration code.
In other embodiments, after obtaining the reference voltage and the output voltage, the embodiment of the present invention may also obtain the number N of the first resistors connected in the pull-up resistor to be calibrated according to a preset formulapAnd the number N of second resistors connected in the pull-down resistor to be calibratednAnd obtaining the resistance R of the calibration resistorref. Specifically, in calibrating the pull-up resistor, the embodiment of the invention can enable the resistor R to be calibratedref＝a*Ru，Vref＝b*VCCIOWherein R isrefTo calibrate the resistance, RuIs a pull-up resistor, VCCIOIs the first voltage, a is the resistivity, b is the voltage coefficient, where b ∈ (0, 1). In addition, the following formula is satisfied for the reference voltage Vref:
the above formula represents the relationship between voltage and resistance, where NpRefers to the number of effective resistors in the pull-up resistor device to be calibrated, i.e. refers to the number of segments in the pull-up resistor device to be calibrated, and the actual number of segments is Np+1。RuRefers to a pull-up resistance value, RrefIs referred to as the calibration resistance value, VCCIORefers to the output voltage value, i.e. the first voltage value, V, of the pull-up resistor device to be calibratedrefIt refers to a reference voltage value.
In some embodiments, after obtaining the above formula, the embodiment of the present invention may convert the above formula into a solution of a and b, and obtain the following formula:
the embodiment of the invention can be used for
Converting the numerator and denominator into minimum irreducible integer to obtain
As can be understood from the above description, the reference voltage VrefIs known, so the b value is known. For example, the first voltage VCCIO1V, reference voltage Vref0.7V, b is calculated to be 0.7, the obtained value of b is substituted into the above formula, and
converted into the minimum irreducible integer to obtain
Let Np+1＝b2，
N can be calculated by the formulapAnd RrefWhile N can be obtainedn＝b1。
As one way, the embodiment of the present invention may determine the number of effective resistors according to the first calibration code and the second calibration code, and calibrate the resistance values of the pull-up resistor device to be calibrated and the pull-down resistor device to be calibrated according to the number of effective resistors.
For a better understanding of the embodiments of the present invention, a specific implementation will now be given. Reference voltage VrefIs 0.75VCCIOWherein the first voltage VCCIO1.2V, a calibrated post pull-up resistor R is requireduIs equal to the pull-down resistor RdAnd the resistance value is 50 omega. Using the method described above, b-V can be calculatedref/VCCIO＝0.75，
Namely, it is
Thus can obtain b2＝3，b1N is then known as 1p+1 ═ 3, i.e. N p2, and N n1. For this reason, a calibration result diagram as shown in fig. 10 and 11 can be obtained.
The embodiment of the invention comprehensively considers the programmable devices such as FPGA and IO configurable driving capability, can fully utilize configurable resources and achieve the optimal solution of convenience and resource utilization rate. The embodiment of the invention integrates the calibration function under different common mode levels (reference voltages) into the chip, can be easily realized through configuration, does not need to provide an additional voltage source externally, simplifies the implementation condition of impedance calibration, and can reduce the plate making requirement to a certain extent.
In summary, the impedance calibration circuit and method provided in the embodiments of the present application can calibrate impedance more simply and efficiently by using the impedance calibration circuit, where the impedance calibration circuit includes a pull-up resistor device to be calibrated, a pull-down resistor device to be calibrated, and a calibration unit, where a first connection end of the pull-up resistor device to be calibrated is connected to the calibration unit, a second connection end of the pull-up resistor device to be calibrated is connected to a power supply end, a first connection end of the pull-down resistor device to be calibrated is connected to the calibration unit, a second connection end of the pull-down resistor device to be calibrated is connected to a third connection end of the pull-up resistor device to be calibrated, a third connection end of the pull-down resistor device to be calibrated is grounded, the calibration unit includes a voltage receiving end and a calibration code output end, and the calibration unit receives a first voltage and a second voltage through the voltage receiving end, the calibration unit is configured to obtain a first calibration code and a second calibration code according to the first voltage and the second voltage, and the calibration unit is configured to calibrate a resistance value of the pull-up resistor device to be calibrated by using the first calibration code and calibrate a resistance value of the pull-down resistor device to be calibrated by using the second calibration code. The calibration unit is used for calibrating the pull-up resistor device, the pull-down resistor device and the calibration unit, so that the resistor can be calibrated more simply and effectively, and the impedance calibration condition is simplified to a certain extent. In addition, only one calibration resistor is needed in the calibration process, and partial IO can be released after the calibration is completed, so that the IO is saved, and the universal applicability of customers is enhanced.
It will be apparent to those skilled in the art that all or some of the steps of the methods, systems, functional modules/units in the systems disclosed above may be implemented as software (which may be implemented in computer program code executable by a computing system), firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit.
In addition, communication media typically embodies computer readable instructions, data structures, computer program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to one of ordinary skill in the art. Thus, the present invention is not limited to any specific combination of hardware and software.
The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. An impedance calibration circuit, comprising:
the calibration unit is used for calibrating a pull-up resistor device to be calibrated, a first connecting end of the pull-up resistor device to be calibrated is connected with the calibration unit, and a second connecting end of the pull-up resistor device to be calibrated is connected with a power supply end;
the calibration unit is used for calibrating the pull-down resistor device to be calibrated, a first connecting end of the pull-down resistor device to be calibrated is connected with the calibration unit, a second connecting end of the pull-down resistor device to be calibrated is connected with a third connecting end of the pull-up resistor device to be calibrated, and the third connecting end of the pull-down resistor device to be calibrated is grounded;
the calibration unit is used for obtaining a first calibration code and a second calibration code according to the first voltage and the second voltage, and the calibration unit is used for calibrating the resistance value of the pull-up resistor to be calibrated by using the first calibration code and calibrating the resistance value of the pull-down resistor to be calibrated by using the second calibration code.
2. The impedance calibration circuit according to claim 1, further comprising a calibration resistor, wherein a first connection terminal of the calibration resistor is connected to the pull-up resistor device to be calibrated and the calibration unit, respectively, and a second connection terminal of the calibration resistor is grounded.
3. The impedance calibration circuit according to claim 2, wherein the pull-up resistor device to be calibrated comprises a plurality of pull-up sub-resistor devices, each of the pull-up sub-resistor devices comprises a first switch element and a first resistor, a first connection terminal of the first switch element is connected to the power supply terminal, a control terminal of the first switch element is connected to the calibration unit, a second connection terminal of the first switch element is connected to a first connection terminal of the first resistor, and a second connection terminal of the first resistor is connected to the calibration resistor and the pull-down resistor device to be calibrated, respectively.
4. The impedance calibration circuit according to claim 3, wherein the first switching element is a PMOS transistor, a source of the PMOS transistor is connected to the power supply terminal, a gate of the PMOS transistor is connected to the calibration unit, and a drain of the PMOS transistor is connected to the first connection terminal of the first resistor.
5. The impedance calibration circuit according to claim 3, wherein the pull-down resistor device to be calibrated comprises a plurality of pull-down sub-resistor devices, each of the pull-down sub-resistor devices comprises a second resistor and a second switch element, a first connection end of the second resistor is connected to the first resistor, a second connection end of the second resistor is connected to a first connection end of the second switch element, a control end of the second switch element is connected to the calibration unit, and a second connection end of the second switch element is grounded.
6. The impedance calibration circuit of claim 5, wherein the second switch element is an NMOS transistor, a source of the NMOS transistor is connected to the second connection terminal of the second resistor, a gate of the NMOS transistor is connected to the calibration unit, and a drain terminal of the NMOS transistor is grounded.
7. The impedance calibration circuit according to claim 1, further comprising a calibration resistor, wherein a first connection terminal of the calibration resistor is connected to the pull-down resistor device to be calibrated and the calibration unit, respectively, and a second connection terminal of the calibration resistor is grounded.
8. The impedance calibration circuit of claim 1, wherein the calibration unit comprises a comparator, a logic processing unit, a converter, and a latch;
the comparator comprises a first voltage receiving end and a second voltage receiving end, the first voltage receiving end is used for receiving the first voltage or the second voltage, the second voltage receiving end is used for receiving the reference voltage, the comparator is used for comparing the first voltage with the reference voltage to obtain the first calibration code, and comparing the second voltage with the reference voltage to obtain the second calibration code;
the first connection end of the logic processing unit is connected with the comparator, the second connection end of the logic processing unit is connected with the first connection end of the converter, the second connection end of the converter is connected with the first connection end or the second connection end of the latch, the second connection end of the latch is connected with the pull-up resistor to be calibrated, and the latch is used for storing the first calibration code or the second calibration code transmitted by the converter.
9. An impedance calibration method applied to the impedance calibration circuit according to any one of claims 1 to 8, the method comprising:
receiving a first voltage and a second voltage, wherein the first voltage is the output voltage of the pull-up resistor device to be calibrated, and the second voltage is the output voltage of the pull-down resistor device to be calibrated;
obtaining a first calibration code and a second calibration code according to the first voltage and the second voltage;
and calibrating the resistance value of the pull-up resistor device to be calibrated by using the first calibration code, and calibrating the resistance value of the pull-down resistor device to be calibrated by using the second calibration code.
10. The method of claim 9, wherein the calibrating the resistance of the pull-up resistor device to be calibrated using the first calibration code and the calibrating the resistance of the pull-down resistor device to be calibrated using the second calibration code comprises:
and determining the number of effective resistors according to the first calibration code and the second calibration code, and calibrating the resistance values of the pull-up resistor device to be calibrated and the pull-down resistor device to be calibrated according to the number of the effective resistors.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011612009.XA CN112636717A (en) | 2020-12-30 | 2020-12-30 | Impedance calibration circuit and method |
| KR1020237015849A KR20230086734A (en) | 2020-12-30 | 2021-03-09 | Impedance calibration circuit and method |
| PCT/CN2021/079751 WO2022141800A1 (en) | 2020-12-30 | 2021-03-09 | Impedance calibration circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011612009.XA CN112636717A (en) | 2020-12-30 | 2020-12-30 | Impedance calibration circuit and method |
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| CN112636717A true CN112636717A (en) | 2021-04-09 |
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| CN202011612009.XA Pending CN112636717A (en) | 2020-12-30 | 2020-12-30 | Impedance calibration circuit and method |
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| KR (1) | KR20230086734A (en) |
| CN (1) | CN112636717A (en) |
| WO (1) | WO2022141800A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7423450B2 (en) * | 2006-08-22 | 2008-09-09 | Altera Corporation | Techniques for providing calibrated on-chip termination impedance |
| US9780785B2 (en) * | 2015-12-21 | 2017-10-03 | Integrated Silicon Solution, Inc. | Calibration circuit for on-chip drive and on-die termination |
| US10003335B2 (en) * | 2016-08-25 | 2018-06-19 | SK Hynix Inc. | Data transmission device, and semiconductor device and system including the same |
| CN110289031B (en) * | 2018-03-19 | 2021-05-28 | 长鑫存储技术有限公司 | Memory driving circuit, impedance matching method thereof and semiconductor memory |
| CN111427812B (en) * | 2020-04-21 | 2022-05-20 | 中国科学院微电子研究所 | Impedance calibration circuit and calibration control method for physical interface of computer flash memory device |
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2020
- 2020-12-30 CN CN202011612009.XA patent/CN112636717A/en active Pending
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2021
- 2021-03-09 KR KR1020237015849A patent/KR20230086734A/en unknown
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| KR20230086734A (en) | 2023-06-15 |
| WO2022141800A1 (en) | 2022-07-07 |
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