CN112635936A - Phase shifter, driving method thereof and radio frequency device - Google Patents
Phase shifter, driving method thereof and radio frequency device Download PDFInfo
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- CN112635936A CN112635936A CN202011560579.9A CN202011560579A CN112635936A CN 112635936 A CN112635936 A CN 112635936A CN 202011560579 A CN202011560579 A CN 202011560579A CN 112635936 A CN112635936 A CN 112635936A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/18—Phase-shifters
- H01P1/184—Strip line phase-shifters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
- H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
- H01Q3/30—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array
- H01Q3/34—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means
Abstract
The invention provides a phase shifter, a driving method thereof and a radio frequency device, belongs to the technical field of phase shifters, and can at least partially solve the problem that the control mode of the phase shifter in the existing mobile terminal equipment has slow response. A phase shifter of the present invention includes: a first substrate; a transmission line disposed on the first substrate; at least one first electrode disposed on a side of the transmission line away from the first substrate, wherein at least one of the first electrodes partially overlaps the transmission line; at least one control unit electrically connected with at least one of the first electrodes, the control unit configured to provide a control signal to the first electrodes.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to a phase shifter, a driving method thereof and a radio frequency device.
Background
With the rapid development of communication technology, mobile terminal devices such as mobile phones and tablet computers also become rapidly developed communication products, and antennas are used as important components for transmitting and receiving signals of the mobile terminal devices, which directly affect the performance of the mobile terminal devices. Meanwhile, the mobile terminal equipment is also provided with a phase shifter for providing different phase signals for the antenna.
In the prior art, signals are provided to the phase shifter by an external control system, so that signals with different phases are provided to the antenna. However, this control method for the phase shifter has the disadvantage of slow response.
Disclosure of Invention
The invention at least partially solves the problem that the control mode of the phase shifter in the existing mobile terminal equipment has slow response, and provides a phase shifter capable of fast response.
The technical scheme adopted for solving the technical problem of the invention is a phase shifter, which comprises: a first substrate;
a transmission line disposed on the first substrate; at least one first electrode disposed on a side of the transmission line away from the first substrate, wherein at least one of the first electrodes partially overlaps the transmission line; at least one control unit electrically connected with at least one of the first electrodes, the control unit configured to provide a control signal to the first electrodes.
It is further preferred that the transmission line is a coplanar waveguide transmission line, and at least a portion of the first electrode partially overlaps with a signal line of the coplanar waveguide transmission line.
It is further preferable that the number of the first electrodes is plural, and the first electrodes are arranged along the extending direction of the transmission line.
Further preferably, a plurality of the control units are provided in one-to-one correspondence with the plurality of the first electrodes.
Further preferably, the phase shifter further includes: a support structure connected to the first electrode, the support structure disposed between a reference electrode of the coplanar waveguide transmission line and the first electrode.
It is further preferable that the control unit is disposed on the first substrate, and an orthographic projection of the control unit on the first substrate is non-overlapping with an orthographic projection of the coplanar waveguide transmission line on the first substrate.
Further preferably, the phase shifter further includes: the second substrate is arranged on one side, far away from the first substrate, of the first electrode, and the first electrode is arranged on the second substrate.
It is further preferred that the control unit is disposed on a side of the second substrate facing the first substrate, and a projection of the control unit on the second substrate does not overlap with a projection of the coplanar waveguide transmission line on the second substrate.
Further preferably, the control unit is a shift register, and the shift register includes an input sub-circuit, a pull-down control sub-circuit, an output sub-circuit, and a pull-down sub-circuit; the input sub-circuit is configured to respond to the control of the first clock signal end to write the input signal provided by the input end into the pull-up node; the pull-down control sub-circuit is configured to write an operating voltage provided by a first operating voltage terminal to a pull-down node in response to control of a first clock signal terminal, and write a first clock signal provided by the first clock signal terminal to the pull-down node in response to control of a voltage at the pull-up node; the output sub-circuit is configured to respond to the control of the voltage at the pull-up node to write the second clock signal provided by the second clock signal terminal into the output terminal, and respond to the control of the pull-down node to write the working voltage provided by the second working voltage terminal into the output terminal; the pull-down sub-circuit is configured to write a second operating voltage to the pull-up node in response to the voltage of the pull-down node and the control of the second clock signal terminal.
Further preferably, the input sub-circuit includes: a first transistor having a control electrode coupled to a first clock signal terminal, a first electrode coupled to an input terminal, and a second electrode coupled to a pull-up node; the pull-down control sub-circuit includes: a second transistor having a control electrode coupled to the pull-up node, a first electrode coupled to the first clock signal terminal, and a second electrode coupled to the pull-down node; a third transistor having a control electrode coupled to the first clock signal terminal, a first electrode coupled to the first working voltage terminal, and a second electrode coupled to the pull-down node; the output sub-circuit includes: a fourth transistor, a control electrode of which is coupled with the pull-down node, a first electrode of which is coupled with the second working voltage end, and a second electrode of which is coupled with the output end; a fifth transistor having a control electrode coupled to the pull-up node, a first electrode coupled to the output terminal, and a second electrode coupled to the second clock signal terminal; a first end of the first capacitor is connected with the control electrode of the fifth transistor, and a second end of the first capacitor is coupled with the output end; a second capacitor, wherein a first end of the second capacitor is coupled to the second working voltage end, and a second end of the second capacitor is coupled to the control electrode of the fourth transistor; the pull-down sub-circuit comprises: a sixth transistor having a control electrode and a first electrode both coupled to the pull-down node; and a control electrode and a second electrode of the seventh transistor are both coupled with the second clock signal end, and a first electrode of the seventh transistor is coupled with a second electrode of the sixth transistor.
Further preferably, the phase shifter further includes: a dielectric layer disposed between the first electrode and the transmission line.
The technical scheme adopted for solving the technical problem of the invention is a phase shifter driving method, and based on the phase shifter, the driving method comprises the following steps: a data writing stage, writing an input signal into the input end of the shift register, and inputting a conducting signal into a first clock signal end; and a signal output stage, namely inputting a turn-off signal to the first clock signal end.
The technical scheme adopted for solving the technical problem of the invention is a radio frequency device which comprises the phase shifter.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram illustrating a top view of a phase shifter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a phase shifter according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a phase shifter according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a shift register according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating a driving method of the shift register of FIG. 4;
FIG. 6 is a schematic structural diagram of a control unit according to an embodiment of the present invention;
FIG. 7 is a timing diagram of a driving method of the control unit of FIG. 6;
FIG. 8 is a flow schematic block diagram of a method of driving the control unit of FIG. 6;
FIG. 9 is a schematic structural diagram of a control unit according to an embodiment of the present invention;
fig. 10 is a timing diagram of a driving method of the control unit of fig. 9;
fig. 11 is a timing diagram of a driving method of the control unit of fig. 9.
Wherein the reference numerals are: 90. a first substrate; 91. a transmission line; 911. a signal line; 912. a first reference electrode; 913. a second reference electrode; 92. a first electrode; 93. a control unit; 95. a dielectric layer; 96. a second substrate; 97. a support structure; CK1, a first clock signal line; CK2, a second clock signal line; p, a signal output end; 10. a shift register group 2, an input sub-circuit; 3. a pull-down control sub-circuit; 4. an output sub-circuit; 5. a pull-down sub-circuit; CK. A first clock signal terminal; CKB, second clock signal end; STV, input terminal; OUT, an output terminal; VGL, a first operating voltage terminal; VGH, a second working voltage end; n1, pull-up node; n2, a pull-down node; c1, a first capacitance; c2, a second capacitor; m1, a first transistor; m2, a second transistor; m3, a third transistor; m4, a fourth transistor; m5, a fifth transistor; m6, a sixth transistor; m7, a seventh transistor; a. a main control subunit; b. a sub-control subunit; OUT _ a and the output end of the main control subunit; OUT _ b, the output end of the secondary control subunit; STV _ a, input end of main control subunit; STV _ b, input end of the sub-control subunit; CK _ a, a first clock signal end of the main control subunit; CK _ b, the first clock signal terminal of the sub-control subunit.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Example 1:
as shown in fig. 1 and 2, the present embodiment provides a phase shifter including: a first substrate 90, a transmission line 91, at least one first electrode 92, and a control unit 93.
The transmission line 91 is disposed on the first substrate 90. At least one first electrode 92 is arranged on the side of the transmission line 91 remote from the first substrate 90, wherein the at least one first electrode 92 partially overlaps the transmission line 91. At least one control unit 93 electrically connected to the at least one first electrode 92, the control unit 93 configured to provide a control signal to the first electrode 92.
Wherein the transmission line 91 is used for transmitting microwave signals, and the transmission line 91 is disposed on the first substrate 90. The first electrode 92 is arranged on the side of the transmission line 91 remote from the first substrate, and the first electrode 92 partially overlaps the transmission line 91, so that the phase of the microwave signal transmitted on the transmission line 91 can be changed by changing the electric field between the first electrode 92 and the transmission line 91.
The control unit 93 in the phase shifter is electrically connected to the first electrode 92, and can input a control signal to the first electrode 92 to make the first electrode 92 change the signal of the transmission line 91.
The phase shifter of this embodiment is provided with a control unit 93 connected to the first electrode 92, and the control unit 93 changes the electric field between the first electrode 92 and the transmission line 91 by inputting a control signal to the first electrode 92. Compared with the prior art, in the embodiment, the control unit 93 is integrated in the phase shifter, so that the lead distance between the control unit 93 and the first electrode 92 is shortened, and the resistance between the control unit 93 and the first electrode 92 is reduced, thereby improving the response speed of the phase shifter and reducing the transmission loss of signals.
Preferably, the transmission line 91 is a coplanar waveguide transmission line, and includes a signal line 911 and a first reference electrode 912 and a second reference electrode 913 disposed on both sides of the signal line 911, and at least a portion of the first electrode 92 partially overlaps the signal line 911.
The first electrode 92 partially overlaps the transmission line 91, and at least a portion of the first electrode 92 partially overlaps the signal line 911, which means that the first electrode 92 is disposed above the transmission line 91 and the signal line 911. This changes the phase of the microwave signal on the transmission line 91 by changing the electric field between the signal line 911 and the first electrode 92.
Preferably, as shown in fig. 1, the number of the first electrodes 92 is plural, and the plural first electrodes 92 are arranged along the extending direction of the transmission line 91. Preferably, the plurality of first electrodes 92 are arranged in parallel with each other along the extending direction of the transmission line 91.
Preferably, the number of the control units 93 is plural, and the plural control units 93 are provided in one-to-one correspondence with the plural first electrodes 92. That is, each first electrode 92 corresponds to one control unit 93, and each control unit 93 provides a signal to the first electrode 92 corresponding thereto.
By making each first electrode 92 independently receive the control signal of the corresponding control unit 93, the electric field in different areas on the transmission line 91 can be more accurately changed, and thus the phase of the microwave signal transmitted on the transmission line 91 can be more accurately changed.
Preferably, the phase shifter further comprises: a dielectric layer 95 disposed between the first electrode 92 and the transmission line 91. The dielectric layer 95 may be a liquid crystal layer, and specifically, the first electrode 92 and the transmission line 91, after being applied with a voltage to form an electric field, drive the liquid crystal layer to deflect, change the dielectric constant of the liquid crystal layer, and thus, change the phase of the microwave signal.
Preferably, the control unit 93 is disposed on the first substrate 90, and an orthogonal projection of the control unit 93 on the first substrate 90 does not overlap with an orthogonal projection of the coplanar waveguide transmission line 91 on the first substrate 90.
Preferably, the phase shifter further comprises: a second substrate 96, the second substrate 96 being disposed opposite the first substrate 90, the first electrode 92 being disposed on a side of the second substrate 96 facing the first substrate 90.
Preferably, the control unit 93 is disposed on a side of the second substrate 96 facing the first substrate 90, and a projection of the control unit 93 on the second substrate 96 does not overlap with a projection of the coplanar waveguide transmission line 91 on the second substrate 96.
By disposing the control unit 93 on the first substrate 90 or the second substrate 96, the control unit 93 can be integrated into the phase shifter by a semiconductor process, thereby simplifying an external control circuit of the phase shifter, further facilitating a control method of the phase shifter, and reducing a control difficulty of the phase shifter.
The phase shifter has the advantages of being beneficial to electric connection and array control, reducing wiring and arrangement pressure of the back plate, being beneficial to miniaturization and integration of devices, being high in compatibility with a back plate process, utilizing time domain to control, being capable of controlling time delay in a small range, not losing the characteristic of quick response, utilizing simple signal control, being easy to achieve, being beneficial to reducing cost and the like.
As shown in fig. 2, the phase shifter disclosed in this embodiment may be a liquid crystal phase shifter, and when different bias voltages are applied to the first electrode 92, the dielectric constant of the dielectric layer 95 (liquid crystal layer) is changed, so as to change the capacitance between the transmission line 91 and the first electrode 92, thereby achieving the phase shifting effect.
Preferably, as shown in fig. 3, the phase shifter of the present embodiment further includes: a support structure 97 disposed between said first electrode 92 and said first reference electrode 912 and said second reference electrode 913.
As shown in fig. 3, that is, the phase shifter of this embodiment may also be an MEMS phase shifter, when different bias voltages are applied to the first electrode 92 (bridge membrane), the voltage difference between the first electrode 92 and the transmission line 91 is changed, so as to drive the height of the first electrode 92 to change, and further change the capacitance between the transmission line 91 and the first electrode 92, thereby achieving the phase shifting effect.
Preferably, as shown in fig. 4 and 5, the control unit 93 is a shift register including: an input sub-circuit 2, a pull-down control sub-circuit 3, an output sub-circuit 4 and a pull-down sub-circuit 5.
The input sub-circuit 2 is configured to write the input signal provided by the input terminal STV to the pull-up node N1 in response to the control of the first clock signal terminal CK.
The pull-down control sub-circuit 3 is configured to write the operating voltage provided from the first operating voltage terminal VGL to the pull-down node N2 in response to the control of the first clock signal terminal CK, and write the first clock signal provided from the first clock signal terminal CK to the pull-down node N2 in response to the control of the voltage at the pull-up node N1.
The output sub-circuit 4 is configured to write the second clock signal provided from the second clock signal terminal CKB to the output terminal OUT in response to the control of the voltage at the pull-up node N1, and write the operating voltage provided from the second operating voltage terminal VGH to the output terminal OUT in response to the control of the pull-down node N2.
The pull-down sub-circuit 5 is configured to write the second operating voltage to the pull-up node N1 in response to the voltage of the pull-down node N2 and the control of the second clock signal terminal CKB.
Specifically, the input sub-circuit 2 includes: the first transistor M1 has a control electrode coupled to the first clock signal terminal CK, a first electrode coupled to the input terminal STV, and a second electrode coupled to the pull-up node N1.
The pull-down control sub-circuit 3 includes: a second transistor M2, having a control electrode coupled to the pull-up node N1, a first electrode coupled to the first clock signal terminal CK, and a second electrode coupled to the pull-down node N2; a third transistor M3 has a control electrode coupled to the first clock signal terminal CK, a first electrode coupled to the first operating voltage terminal VGL, and a second electrode coupled to the pull-down node N2.
The output sub-circuit 4 includes: a fourth transistor M4, having a control electrode coupled to the pull-down node N2, a first electrode coupled to the second operating voltage terminal VGH, and a second electrode coupled to the output terminal OUT; a fifth transistor M5 having a control electrode coupled to the pull-up node N1, a first electrode coupled to the output terminal OUT, and a second electrode coupled to the second clock signal terminal CKB; a first capacitor C1, having a first terminal connected to the control electrode of the fifth transistor M5 and a second terminal coupled to the output terminal OUT; a second capacitor C2, a first terminal of which is coupled to the second operating voltage terminal VGH, and a second terminal of which is coupled to the control electrode of the fourth transistor M4.
The pull-down sub-circuit 5 includes: a sixth transistor M6 having a control electrode and a first electrode both coupled to the pull-down node N2; a seventh transistor M7 having a control electrode and a second electrode both coupled to the second clock signal terminal CKB, and a first electrode coupled to the second electrode of the sixth transistor M6.
As shown in fig. 5, this embodiment further provides a driving method of a phase shifter, based on the phase shifter, the driving method includes:
and a data writing stage, writing an input signal into the input end STV of the shift register, and inputting a conducting signal into the first clock signal end CK.
That is, a negative voltage is input to the first clock signal terminal CK, so that the first transistor M1 is turned on to write the signal of the input terminal STV into the first capacitor C1. It should be noted that, if the input terminal STV is a negative voltage, the first capacitor C1 accumulates charges, so that the output terminal OUT outputs a negative voltage in the next stage; if the input terminal STV is positive, the first capacitor C1 is in a no-charge state, so that the output terminal OUT outputs a positive voltage in the next stage.
And a signal output stage, namely inputting a turn-off signal to the first clock signal CK end.
That is, a positive voltage is input to the first clock signal terminal CK, so that the first transistor M1 is turned off; under the action of the first capacitor C1, the output terminal OUT outputs a control signal to the first electrode 92.
It should be noted that the control unit in the phase shifter of this embodiment may also be an ADC controller, a logic controller, or other suitable controllers, which are not listed here.
Specifically, as shown in fig. 6 to 8, the case where signals are output from the cascaded shift registers to the first electrode 92 is described below:
each of the first electrodes 92 corresponds to a master control subunit a and a slave control subunit b, the output terminal OUT _ a of the master control subunit is coupled to the input terminal STV _ b of the slave control subunit, the first clock signal terminal CK _ a of the master control subunit is coupled to the first clock signal line CK1, the first clock signal terminal CK _ b of the slave control subunit is coupled to the second clock signal line CK2, and the output terminal OUT _ a of the master control subunit is coupled to the signal output terminal P.
That is, the sub-control sub-unit b also includes an input sub-circuit 2, a pull-down control sub-circuit 3, an output sub-circuit 4, and a pull-down sub-circuit 5, and the structures of the sub-circuits are identical to those of the sub-circuit in the main control sub-unit a.
It should be noted that all transistors in the shift register group 10 are N-type transistors; alternatively, all the transistors in the shift register group 10 are P-type transistors. Hereinafter, all the transistors will be described as P-type transistors.
As shown in fig. 7, the driving method includes:
s11, in the data writing phase, writing an input signal into the input terminal STV _ a of the main control subunit, and inputting a turn-on signal into the first clock signal terminal CK _ a of the main control subunit.
In other words, a negative voltage is inputted to the first clock signal terminal CK _ a of the main control subunit, so that the first transistor M1 of the main control subunit a is turned on, and the signal at the input terminal STV _ a of the main control subunit is written into the first capacitor C1. It should be noted that, if the input terminal STV _ a of the main control subunit is a negative voltage, the first capacitor C1 accumulates charges, so that the output terminal OUT _ a of the main control subunit outputs a negative voltage in the next stage; if the input terminal STV _ a of the main control subunit is positive, the first capacitor C1 is in a no-charge state, so that the output terminal OUT _ a of the main control subunit outputs a positive voltage in the next stage.
S12, a first signal output stage, inputting an off signal to the first clock signal terminal CK _ a of the main control subunit, and inputting an on signal to the first clock signal terminal CK _ b of the sub control subunit.
Wherein, that is, a positive voltage is input to the first clock signal terminal CK _ a of the main control subunit, so that the first transistor M1 of the main control subunit a is turned off; the sub voltage is input to the first clock signal terminal CK _ b of the sub control subunit, so that the first transistor M1 of the sub control subunit b is turned on. Under the action of the first capacitor C1, the output terminal OUT _ a of the main control subunit outputs the control signal of the first electrode 92 to the signal output terminal P, so that the first electrode 92 connected to the signal output terminal P receives the control signal; at the same time, the output terminal OUT _ a of the main control subunit inputs a signal to the input terminal STV _ b of the sub-control subunit, so that the signal of the input terminal STV _ b of the sub-control subunit is written into the first capacitor C1 thereof.
S13, a second signal output stage, inputting a turn-off signal to the first clock signal terminal CK _ b of the sub-control subunit.
Here, a negative voltage is input to the first clock signal terminal CK _ b of the sub-control subunit, so that the first transistor M1 of the sub-control subunit b is turned off. The output terminal OUT _ b of the sub-control subunit outputs the control signal of the first electrode 92 to the signal output terminal P under the action of the first capacitor C1 of the sub-control subunit b.
Further, as shown in fig. 9 to 11, the plurality of shift registers are cascaded, except for the last shift register group 10, the output terminal OUT _ b of the sub-control subunit of the other shift register groups 10 is coupled to the input terminal STV _ a of the main control subunit of the respective next shift register group 10.
It should be noted that the first clock signal terminal CK _ b of the sub-control subunit and the second clock signal terminal CKB of the main control subunit can be connected to the same signal line, such as the second clock signal line CK2 in fig. 9; the second clock signal terminal CKB of the sub-control subunit b and the first clock signal terminal CK _ a of the main control subunit may be connected to the same signal line, such as the first clock signal line CK1 in fig. 9.
As shown in fig. 9, that is, except for the last shift register group 10, each shift register group 10 inputs signals to the input end of the next shift register group 10, so that the next shift register group 10 outputs the control signal of the first electrode 92.
For example, if the control unit of the first electrode 92 has n stages of shift register groups 10 in cascade, based on the driving method in embodiment 1 (only the control signal of the first electrode 92 output by the main control subunit a in the first signal output stage of each shift register group 10 is valid, and the control signal of the first electrode 92 output by the sub-control subunit b in the second signal output stage is only used for outputting a signal to the control unit of the first electrode 92 of the next stage, i.e., outputting an invalid signal), the valid signals of the n stages of shift register groups 10 are output at intervals, and there is an output of an invalid signal between every two adjacent valid signals (the dotted line in fig. 11 and 10 indicates an invalid signal).
Preferably, the signal output terminal P of each shift register group 10 is connected to a first electrode 92.
As shown in fig. 9, the signal output terminal P of each shift register group 10 is connected to a first electrode 92. When different signals are input to the input terminal STV _ a of the main control subunit of the shift register group 10 of the first stage in multiple time periods, the shift register groups 10 of the respective stages can output different control signals of the first electrode 92 in different stages. Therefore, the signal output terminal P of the shift register group 10 of each stage can be connected to one first electrode 92 at this time.
Example 2:
as shown in fig. 1 to 11, the present embodiment provides a radio frequency device including the phase shifter.
The radio frequency device can be applied to a display device.
Specifically, the display device may be any product or component having a display function, such as a liquid crystal display panel, an Organic Light Emitting Diode (OLED) display panel, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (13)
1. A phase shifter, comprising:
a first substrate;
a transmission line disposed on the first substrate;
at least one first electrode disposed on a side of the transmission line away from the first substrate, wherein at least one of the first electrodes partially overlaps the transmission line;
at least one control unit electrically connected with at least one of the first electrodes, the control unit configured to provide a control signal to the first electrodes.
2. The phase shifter of claim 1, wherein the transmission line is a coplanar waveguide transmission line, and at least a portion of the first electrode partially overlaps a signal line of the coplanar waveguide transmission line.
3. The phase shifter according to claim 2, wherein the number of the first electrodes is plural, and the plural first electrodes are arranged along an extending direction of the transmission line.
4. The phase shifter according to claim 3, wherein a plurality of the control units are provided in one-to-one correspondence with a plurality of the first electrodes.
5. The phase shifter of claim 2, further comprising: a support structure connected to the first electrode, the support structure disposed between a reference electrode of the coplanar waveguide transmission line and the first electrode.
6. The phase shifter according to claim 5, wherein the control unit is disposed on the first substrate, and an orthographic projection of the control unit on the first substrate does not overlap with an orthographic projection of the coplanar waveguide transmission line on the first substrate.
7. The phase shifter of claim 2, further comprising: the second substrate is arranged on one side, far away from the first substrate, of the first electrode, and the first electrode is arranged on the second substrate.
8. The phase shifter according to claim 7, wherein the control unit is disposed on a side of the second substrate facing the first substrate, and a projection of the control unit on the second substrate does not overlap with a projection of the coplanar waveguide transmission line on the second substrate.
9. The phase shifter according to any one of claims 1 to 8, wherein the control unit is a shift register including an input sub-circuit, a pull-down control sub-circuit, an output sub-circuit, and a pull-down sub-circuit;
the input sub-circuit is configured to respond to the control of the first clock signal end to write the input signal provided by the input end into the pull-up node;
the pull-down control sub-circuit is configured to write an operating voltage provided by a first operating voltage terminal to a pull-down node in response to control of a first clock signal terminal, and write a first clock signal provided by the first clock signal terminal to the pull-down node in response to control of a voltage at the pull-up node;
the output sub-circuit is configured to respond to the control of the voltage at the pull-up node to write the second clock signal provided by the second clock signal terminal into the output terminal, and respond to the control of the pull-down node to write the working voltage provided by the second working voltage terminal into the output terminal;
the pull-down sub-circuit is configured to write a second operating voltage to the pull-up node in response to the voltage of the pull-down node and the control of the second clock signal terminal.
10. The phase shifter according to claim 9,
the input sub-circuit includes: a first transistor having a control electrode coupled to a first clock signal terminal, a first electrode coupled to an input terminal, and a second electrode coupled to a pull-up node;
the pull-down control sub-circuit includes: a second transistor having a control electrode coupled to the pull-up node, a first electrode coupled to the first clock signal terminal, and a second electrode coupled to the pull-down node;
a third transistor having a control electrode coupled to the first clock signal terminal, a first electrode coupled to the first working voltage terminal, and a second electrode coupled to the pull-down node;
the output sub-circuit includes: a fourth transistor, a control electrode of which is coupled with the pull-down node, a first electrode of which is coupled with the second working voltage end, and a second electrode of which is coupled with the output end;
a fifth transistor having a control electrode coupled to the pull-up node, a first electrode coupled to the output terminal, and a second electrode coupled to the second clock signal terminal;
a first end of the first capacitor is connected with the control electrode of the fifth transistor, and a second end of the first capacitor is coupled with the output end;
a second capacitor, wherein a first end of the second capacitor is coupled to the second working voltage end, and a second end of the second capacitor is coupled to the control electrode of the fourth transistor;
the pull-down sub-circuit comprises: a sixth transistor having a control electrode and a first electrode both coupled to the pull-down node;
and a control electrode and a second electrode of the seventh transistor are both coupled with the second clock signal end, and a first electrode of the seventh transistor is coupled with a second electrode of the sixth transistor.
11. The phase shifter of claim 1, further comprising: a dielectric layer disposed between the first electrode and the transmission line.
12. A method of driving a phase shifter, according to any one of claims 9 to 11, comprising:
a data writing stage, writing an input signal into the input end of the shift register, and inputting a conducting signal into the first clock signal end;
and a signal output stage, namely inputting a turn-off signal to the first clock signal end.
13. A radio frequency device comprising a phase shifter according to any one of claims 1 to 11.
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| CN112635936B (en) | 2022-04-08 |
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