CN112635568B - Power MOSFET, manufacturing method thereof and electronic equipment - Google Patents
Power MOSFET, manufacturing method thereof and electronic equipment Download PDFInfo
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- CN112635568B CN112635568B CN202011594199.7A CN202011594199A CN112635568B CN 112635568 B CN112635568 B CN 112635568B CN 202011594199 A CN202011594199 A CN 202011594199A CN 112635568 B CN112635568 B CN 112635568B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 80
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 78
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 78
- 239000010703 silicon Substances 0.000 claims abstract description 78
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 76
- 229920005591 polysilicon Polymers 0.000 claims abstract description 59
- 210000000746 body region Anatomy 0.000 claims abstract description 41
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 39
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 25
- 238000011049 filling Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 9
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 230000000717 retained effect Effects 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The present disclosure provides a power MOSFET, a method of manufacturing the same, and an electronic device. The power MOSFET includes: a silicon substrate and a silicon epitaxial layer on the silicon substrate; a plurality of trenches arranged at intervals and formed in the silicon epitaxial layer; source polycrystalline silicon formed in the lower parts of the trenches and surrounded by the field oxide layer; gate polysilicon formed in upper portions of the plurality of trenches and spaced apart from the source polysilicon by high density silicon dioxide; a gate oxide layer surrounds the periphery of the gate polysilicon; the first body areas are arranged at intervals and positioned among the grooves; a plurality of source regions located above the plurality of first body regions; a plurality of contact holes extending from a top surface of the silicon epitaxial layer to the first body region, the plurality of contact holes being formed self-aligned with the plurality of trenches.
Description
Technical Field
The invention belongs to the field of semiconductor power devices, and particularly relates to a power MOSFET, a manufacturing method thereof, a power MOSFET and electronic equipment.
Background
In the field of power semiconductor devices, the power density and on-resistance of the device are one of the most important indicators for measuring the performance of the product. The larger the power density, the lower the chip cost, the lower the parasitic capacitance and the miniaturized package.
The device structure of the deep trench MOSFET can lead the electric field of the drift region to be completely unfolded under the condition of higher concentration by the charge balance principle, thus realizing higher breakdown voltage of the device; the characteristic resistance of the device adopting the charge balance principle is 1/2-1/5 of that of a common plane product. With the continuous increase of the power capacity of the device, the cell size (cell pitch) of the device is also smaller and smaller, which increases the alignment difficulty between the contact hole and the trench, and the misalignment can cause poor uniformity of the device performance and even abnormal parameters.
Disclosure of Invention
In view of the above, the present invention provides a power MOSFET in which a contact hole is self-aligned with a trench, a method of manufacturing the same, and an electronic device including the same.
According to one aspect of the present invention, a method of manufacturing a power MOSFET is presented, characterized by: the method comprises the following steps: growing a silicon epitaxial layer on a silicon substrate; etching the silicon epitaxial layer to form a plurality of grooves which are arranged at intervals; growing silicon dioxide on the surfaces of the silicon epitaxial layers on the inner side wall and the bottom of the groove and forming a silicon dioxide layer as a field oxide layer; filling source polycrystalline silicon in the groove and carrying out back etching until the top surface of the silicon epitaxial layer is lower than the top surface of the silicon epitaxial layer; wet etching the field oxide layer on the side wall of the upper part of the groove; filling a high-density silicon dioxide layer in the groove, filling the groove and covering the top surface of the silicon epitaxial layer, grinding silicon dioxide by adopting a surface planarization process (CMP) and etching the silicon dioxide layer in the groove to be below the top surface of the silicon epitaxial layer by a wet method; growing a gate oxide layer; depositing gate polysilicon and carrying out back etching until the top surface of the silicon epitaxial layer is below; performing first body region injection and well pushing; performing source region implantation and annealing; depositing silicon dioxide, and removing the silicon dioxide on the top surface of the silicon epitaxial layer by adopting a surface planarization process (CMP) to form a dielectric oxide layer filling the groove; depositing an insulating medium layer; etching the insulating dielectric layer to the top surface of the silicon epitaxial layer by utilizing a photoetching plate pattern; carrying out dry etching on the silicon material between the grooves by adopting a high selectivity material to form trapezoid contact holes; hole injection is carried out through the contact hole, and annealing is carried out, so that a second body region is formed; and (5) carrying out a surface metal process to manufacture the electrode of the device.
Wherein, the etching the silicon epitaxial layer to form the trench includes: depositing a composite layer of silicon dioxide and silicon nitride on the silicon epitaxial layer to serve as a hard mask for subsequent trench etching and a barrier layer of a surface planarization process; and defining a groove region on the hard mask plate through a photoetching process, and then etching the silicon epitaxial layer to form a groove.
Wherein the field oxide layer may be formed by a combination of thermally grown silicon dioxide and deposited silicon dioxide.
Filling source polycrystalline silicon in the groove and carrying out back etching until the top surface of the silicon epitaxial layer is below, wherein the steps comprise: polysilicon on the top surface of the silicon epitaxial layer and in the upper portion of the trench is etched back, polysilicon in the lower portion of the trench is retained, and the retained polysilicon is connected to the source electrode.
Wherein the gate polysilicon is etched back to below the top surface of the silicon epitaxial layerFor filling the dielectric oxide layer.
Wherein the dielectric oxide layer in the trench is etched to a level with the top surface of the silicon epitaxial layer.
And etching the contact hole by adopting a dry etching process, wherein silicon is etched while a dielectric oxide layer is reserved in the dry etching process, and the shape and the inclination angle of the hole are controlled.
According to another aspect of the present invention, there is provided a power MOSFET comprising: a silicon substrate and a silicon epitaxial layer on the silicon substrate; a plurality of trenches arranged at intervals and formed in the silicon epitaxial layer; source polycrystalline silicon formed in the lower parts of the trenches and surrounded by the field oxide layer; gate polysilicon formed in upper portions of the plurality of trenches and spaced apart from the source polysilicon by high density silicon dioxide; a gate oxide layer surrounds the periphery of the gate polysilicon; the first body areas are arranged at intervals and positioned among the grooves; a plurality of source regions located above the plurality of first body regions; a plurality of contact holes extending from a top surface of the silicon epitaxial layer to the first body region, the plurality of contact holes being formed self-aligned with the plurality of trenches.
Wherein, a second body region with high concentration is formed between the bottom of the contact hole and the first body region.
According to a further aspect of the invention, an electronic device is proposed, comprising a power MOSFET according to any one of the preceding aspects.
Drawings
Fig. 1 shows a top view of a power MOSFET according to an embodiment of the disclosure.
Fig. 2 illustrates a cross-sectional view of the power MOSET taken along line X-X' of fig. 1, according to an embodiment of the present disclosure.
Fig. 3 illustrates a cross-sectional view of a power MOSET taken along line Y-Y' of fig. 1, according to an embodiment of the present disclosure.
Fig. 4 illustrates a cross-sectional view of a power MOSET taken along the line Z-Z' of fig. 1, according to an embodiment of the present disclosure.
Fig. 5 to 15 show cross-sectional views of steps of manufacturing a power MOSET according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
The power MOSFET according to the embodiments of the present disclosure may include a terminal structure region and an active region that may be divided in a lateral direction, and in the active region portion, the power MOSFET may include a semiconductor source region, a semiconductor drain region, a gate electrode, and a body region structure formed on a substrate. Wherein, there is epitaxial layer on the substrate, the substrate can include the silicon substrate, the epitaxial layer can include the silicon epitaxial layer; a plurality of grooves are formed in the epitaxial layer, and are arranged at intervals; filling source polycrystalline silicon and grid polycrystalline silicon in each groove of the active region, wherein the source polycrystalline silicon is formed in the lower parts of the grooves and surrounded by the field oxide layer; the gate polysilicon is formed within the plurality of trench upper portions and is spaced apart from the source polysilicon by high density silicon dioxide; a gate oxide layer surrounds the periphery of the gate polysilicon; first body regions are respectively formed between any two adjacent trenches in the plurality of trenches, so that a plurality of first body regions which are arranged at intervals are formed, a plurality of source regions are respectively formed above the plurality of first body regions, a plurality of contact holes extend from the top surface of the silicon epitaxial layer to the first body regions, and the plurality of contact holes are formed in a self-aligned mode with the plurality of trenches.
The present disclosure may be presented in various forms, some examples of which are described below.
Fig. 1 shows a top view of a power MOSFET according to an embodiment of the disclosure. As shown in fig. 1, a power MOSFET device according to an embodiment of the present disclosure includes an active area and a termination structure area. The termination structure region is located around the active region, the active region and the termination structure region being separated by a dashed line in fig. 1. As shown in fig. 1, the termination structure region is located to the right and above the active region. The cross section of the power MOSFET is taken at different positions in the longitudinal direction (the direction in which the trenches extend) by X-X ' lines, Y-Y ' lines, Z-Z ' lines, respectively. A large source region hole is formed in the active region at a position where the X-X ' line is taken, and a via hole is formed in the terminal structure region at a position where the Y-Y ' line is taken, and a via hole is formed in the terminal structure region at a position where the Z-Z ' line is taken, and a plurality of trenches are formed in the longitudinal direction so as to penetrate the active region and the terminal structure region at intervals. The power MOSFET is sectioned at different locations in the longitudinal direction with X-X ', Y-Y ', Z-Z ' lines, respectively, to be shown in fig. 2-4.
Fig. 2 illustrates a cross-sectional view of the power MOSET taken along line X-X' of fig. 1, according to an embodiment of the present disclosure. As shown in fig. 2, the power MOSET is formed into an active region and a termination structure region in a lateral direction. A plurality of trenches a are formed in the lateral direction of the power MOSFET at intervals. The plurality of trenches a in the active area and the terminal structure area are respectively provided with different filling structures, source polycrystalline silicon 6 and grid polycrystalline silicon 7 are filled in the trenches a in the active area, oxide layers 3 and 4 are respectively filled at the bottom and the periphery of the source polycrystalline silicon 6, a grid oxide layer 13 is surrounded at the periphery of the grid polycrystalline silicon 7, a dielectric oxide layer 12 is formed above the grid polycrystalline silicon, and a spacing oxide layer 5 is formed between the grid polycrystalline silicon and the source polycrystalline silicon. The spacer oxide layer 5 may comprise high density silicon oxide. A first body region 10 is formed between any adjacent two trenches, the upper portion of which is formed by doping as a second body region 11 of high doping concentration. A contact hole 9 is formed in the active region over the first body region 10 and the second body region 11, the boundary of the contact hole 9 being formed self-aligned with the boundary of the trench a. The contact hole 9 is filled with a conductive material by hole injection. The contact hole 9 extends from the top of the epitaxial layer all the way down to the upper part of the first body region, i.e. in contact with the high concentration second body region, thereby forming a conductive contact in the termination structure region, the trench a being filled with source polysilicon 6 and not with gate polysilicon 7. The level of the source polysilicon 6 located in the termination structure region is higher than the level of the source polysilicon 6 in the active region. In the active region, an electrode 15 is formed over the contact hole 9, which electrode 15 is integrated in the large window, which electrode 15 is in conductive contact with the conductive material in the contact hole 9, thereby forming a conductive path up to the second body region. In the termination structure region, an insulating dielectric layer 14 is formed over the trench, and an electrode 15 is formed over the insulating dielectric layer 14.
Fig. 3 illustrates a cross-sectional view of a power MOSET taken along line Y-Y' of fig. 1, according to an embodiment of the present disclosure. Since the cross section taken by the Y-Y 'line is different from the cross section taken by the X-X' line in position in the longitudinal direction, the electrode 15 located above the device is formed above the insulating dielectric layer 14. In the active region, the electrode 15 is in contact with the gate polysilicon 7 through a via in the insulating dielectric layer 14, which via is filled with electrode material up to the top surface of the gate polysilicon 7, thereby forming a gate conductive connection. In the termination structure region, the electrode 15 is located above the insulating dielectric layer 14 and is not in contact with the source polysilicon 6 located below the insulating dielectric layer.
Fig. 4 illustrates a cross-sectional view of a power MOSET taken along the line Z-Z' of fig. 1, according to an embodiment of the present disclosure. The cross section is located in the termination structure region and in the termination structure region where the cross section is located, the electrode 15 is in conductive contact with the source polysilicon 6 through a via in the insulating dielectric layer, thereby forming a source polysilicon conductive contact. As can also be seen from fig. 2 to 4, a drain metal electrode layer is formed on the back side of the device substrate.
Fig. 5 to 15 show cross-sectional views of steps of manufacturing a power MOSET according to an embodiment of the present disclosure. In particular, fig. 5 illustrates the preparation substrate and epitaxial layer structures required to fabricate a power MOSFET in accordance with an embodiment of the present disclosure. As shown in fig. 5, an epitaxial layer 2 is epitaxially grown over a substrate 1. Both the substrate 1 and the epitaxial layer 2 may comprise a silicon material. The epitaxial layer 3 has the same conductivity type as the substrate, i.e., a first conductivity type (e.g., N-type) and the epitaxial layer 3 may be a silicon epitaxial layer. Depositing a composite layer of silicon dioxide and silicon nitride on the silicon epitaxial layer 3 to serve as a hard mask for subsequent trench etching and a barrier layer for a surface planarization process; a trench region is defined on the hard mask by a photolithography process, and then the silicon epitaxial layer 3 is etched to form a trench a. Thereby, a plurality of trenches a are formed in the epitaxial layer in a spaced arrangement, the plurality of trenches a being distributed within the active region and the termination structure region.
Fig. 6 shows a power MOSFET structure according to an embodiment of the present disclosure with an oxide layer formed within trench a. As shown in fig. 6, oxide layers 3 and 4 are grown extending over the bottom and sidewall silicon surfaces of trench a, respectively, oxide layers 3 and 4 being located over the bottom and sidewall, respectively, within the trench, and each may comprise silicon dioxide. Oxide layers 3 and 4 may be used as field oxide layers 3 and 4.
Fig. 7 shows a power MOSFET structure according to an embodiment of the present disclosure with trench a filled with source polysilicon 6. As shown in fig. 7, the trench a is filled with source polysilicon 6, and in the active region, the source polysilicon 6 is etched back twice to a certain distance below the surface of the silicon epitaxial layer, wherein the first etching back is performed to the top surface of the silicon epitaxial layer, and the second etching back is performed to a certain distance below the surface of the silicon epitaxial layer. In the termination structure region, the source polysilicon 6 is etched back to the surface of the silicon epitaxial layer once, so that the top surface of the source polysilicon 6 is flush with the top surface of the silicon epitaxial layer. In the active region, the field oxide layer 4 of the side surface in the trench a is further wet etched to the same height as the source polysilicon 6. A power MOSFET structure according to an embodiment of the present disclosure is thereby formed having a trench filled with source polysilicon 6, wherein the level of source polysilicon 6 and field oxide layer 4 within trench a in the active area is lower than the top surface of silicon epitaxial layer 2, while the level of source polysilicon 6 and field oxide layer 4 within the termination structure area is flush with the top surface of silicon epitaxial layer 2.
Fig. 8 shows a power MOSFET structure according to an embodiment of the present disclosure with an isolation oxide layer 5 filled in the active area trench a. As shown in fig. 8, the trenches a of the active region are filled with high density silicon dioxide using a hard mask in the form of a composite layer of deposited silicon dioxide and silicon nitride. The high density silicon dioxide fills the trench and overlies the hard mask. Grinding the high-density silicon dioxide to the silicon nitride surface position of the hard mask plate by adopting a surface planarization process (CMP), and removing the silicon nitride layer; the wet etch of the silicon dioxide fill layer is a distance below the top surface of the silicon epitaxial layer such that the level of the high density silicon dioxide layer is below the top surface of the silicon epitaxial layer and above the level of the source polysilicon 6 within the active region. That is, the high-density silicon oxide covers the top surface of the source polysilicon 6 to serve as the isolation oxide layer 5.
Fig. 9 shows a power MOSFET structure according to an embodiment of the present disclosure with an active area trench a filled with gate polysilicon 7. As shown in fig. 9, silicon dioxide is grown on the trench sidewalls over the isolation oxide layer 5 to serve as a gate oxide layer. Then deposit gate polysilicon and etch back to the silicon surfaceAt a distance below, e.g., gate polysilicon is etched back from the top surface of the silicon epitaxial layerThe gate polysilicon 7 is electrically isolated from the source polysilicon 6 by the isolation oxide 5.
Fig. 10 illustrates a power MOSFET structure according to an embodiment of the disclosure with a first body region formed within an active area. As shown in fig. 10, a first body region 10 is formed by performing a first body region implantation and a push well, the first body region 10 being formed between any two adjacent trenches a of the active region, and a source region implantation and an anneal being performed in the first body region 10, thereby forming a source region 8 over the first body region.
Fig. 11 illustrates a power MOSFET structure according to an embodiment of the present disclosure with an active area trench a filled with a dielectric oxide layer 12. As shown in fig. 11, silicon dioxide is deposited over the gate polysilicon 7 in the active region trench a, the silicon dioxide filling the trench a and covering the top surface of the silicon epitaxial layer, and the silicon dioxide on the top surface of the silicon epitaxial layer is removed using a surface planarization process (CMP) to form a dielectric oxide layer 12 filling the trench.
Fig. 12 shows a power MOSFET structure according to an embodiment of the present disclosure with a termination structure region formed with an insulating dielectric layer 14. As shown in fig. 12, an insulating dielectric layer is deposited over the silicon epitaxial layer and then etched using a photolithographic plate pattern to the top surface of the silicon epitaxial layer, thereby removing the insulating dielectric layer over the silicon epitaxial layer in the active region while retaining the insulating dielectric layer 14 over the termination structure region.
Fig. 13 illustrates a power MOSFET structure according to an embodiment of the present disclosure with contact holes formed in the source region of the active area. As shown in fig. 13, the silicon material between the trenches is dry etched with a high selectivity material to form trapezoid contact holes, thereby forming trapezoid contact holes 9 in the source region 8. The angle of the trapezoid can be adjusted as required. Since the silicon material between trenches is dry etched with a high selectivity material, the dry etch self-aligned etches the silicon material between adjacent trenches without etching the silicon dioxide material within the trenches. Thereby causing the contact hole boundaries to self-align with the trench filled silicon dioxide boundaries, i.e. the contact hole 9 is self-aligned with trench a. Thus, the problem of poor isolation possibly caused by the deviation of the contact hole into the groove can be avoided.
Figure 14 illustrates a power MOSFET structure according to an embodiment of the present disclosure with an active area formed with a second body area. As shown in fig. 14, the contact hole is hole-implanted and annealed, thereby forming a high concentration of the second body region 11. The second body region 11 is located at an upper portion of the first body region 10 and has a high doping concentration.
Fig. 15 shows a power MOSFET structure according to an embodiment of the disclosure formed with a metal electrode. As shown in fig. 15, a surface metal process is performed to form a metal electrode 15 on the front side of the device, i.e., on the top surface of the silicon epitaxial layer. The metal electrode 15 covers the contact hole 9 in the active region and makes electrical contact with the high concentration second body region 11 through the contact hole 9. The metal electrode 15 is covered over the insulating dielectric layer 14 in the termination structure region, thereby being electrically insulated from the source polysilicon 6 located in the trench a of the termination structure region by the insulating dielectric layer 14.
It should be appreciated that fig. 15 shows a cross-section taken along line X-X' of fig. 1, where the electrode 15 is not in electrical contact with the source polysilicon 6 at the termination structure region. Whereas in the Z-Z' position of fig. 1, i.e. where all trenches are in the termination structure region, the electrode 15 is in electrical contact with the source polysilicon 6 in the trenches through a via in the insulating dielectric layer 14. When the device is operated, as shown in fig. 1, since the source polysilicon within the same trench (i.e., the source polysilicon in the active region and the source polysilicon in the termination structure region within the same trench) are in physical communication. Thus, the same potential can be applied to the source polysilicon located in the active region and the source polysilicon located in the termination structure region by the electrode located at the Z-Z' position of fig. 1.
A power MOSFET device according to embodiments of the present disclosure can thus be formed that includes a semiconductor source region, a semiconductor drain region, a trench, and a body region structure formed in an epitaxial layer of a substrate. The illustrated trench also includes gate polysilicon and source polysilicon located within it. The body region structure includes a first body region and a second body region, the semiconductor source region is formed over the first body region, and a trapezoidal contact hole is formed within the source region. The trapezoid contact hole is formed in self-alignment with the trench by dry etching of a high selectivity material, i.e., the boundary of the trapezoid contact hole is self-aligned with the boundary of the trench adjacent to the trapezoid contact hole without misalignment. The trapezoid contact hole formed by the self-alignment process can avoid the influence of offset between the contact hole and the groove, such as poor isolation and reduced insulation caused by offset. In addition, the self-alignment process can reduce the process difficulty and improve the power density of the device and the stability of the device parameters.
It should be clear to a person skilled in the art that the above-described power MOSFET device structure is only one specific embodiment based on the inventive concept, and is not intended to limit the scope of the present invention. Modifications and substitutions of the device structure of the present invention may be made by those skilled in the art without departing from the spirit of the present invention. Such modified and substituted device structures are also within the scope of the present invention.
The power MOSFET device according to the embodiments of the present disclosure can be applied to various electronic apparatuses. For example, by integrating a plurality of such power MOSFET devices, as well as other devices (e.g., other forms of transistors, etc.), an Integrated Circuit (IC) may be formed and an electronic device constructed therefrom. Therefore, the present disclosure also provides an electronic device including the above power device. The electronic device may also include a display screen that mates with the integrated circuit and a wireless transceiver that mates with the integrated circuit. Such electronic devices are e.g. smart phones, computers, tablet computers (PCs), artificial intelligence, wearable devices, mobile power supplies etc.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (9)
1. A method of manufacturing a power MOSFET, characterized by:
the method comprises the following steps:
growing a silicon epitaxial layer on a silicon substrate;
etching the silicon epitaxial layer to form a plurality of grooves which are arranged at intervals;
growing silicon dioxide on the surfaces of the silicon epitaxial layers on the inner side wall and the bottom of the groove and forming a silicon dioxide layer as a field oxide layer;
filling source polycrystalline silicon in the groove and carrying out back etching until the top surface of the silicon epitaxial layer is lower than the top surface of the silicon epitaxial layer;
wet etching the field oxide layer on the side wall of the upper part of the groove;
filling a high-density silicon dioxide layer in the groove, filling the groove with the silicon dioxide layer and covering the top surface of the silicon epitaxial layer, grinding silicon dioxide by adopting a surface planarization process CMP and wet etching the silicon dioxide layer in the groove to be below the top surface of the silicon epitaxial layer;
growing a gate oxide layer;
depositing gate polysilicon and carrying out back etching until the top surface of the silicon epitaxial layer is below;
performing first body region injection and well pushing;
performing source region implantation and annealing;
depositing silicon dioxide, and removing the silicon dioxide on the top surface of the silicon epitaxial layer by adopting a surface planarization process (CMP) to form a dielectric oxide layer filling the groove;
depositing an insulating medium layer; etching the insulating dielectric layer to the top surface of the silicon epitaxial layer by utilizing a photoetching plate pattern;
carrying out dry etching on the silicon material between the grooves by adopting a high selectivity material to form trapezoid contact holes;
hole injection is carried out through the contact hole, and annealing is carried out, so that a second body region is formed;
performing a surface metal process to manufacture an electrode of the device;
and etching the contact hole by adopting a dry etching process, wherein in the dry etching process, silicon is etched while the dielectric oxide layer is reserved, and the shape and the inclination angle of the hole are controlled.
2. The method according to claim 1, characterized in that:
the etching the silicon epitaxial layer to form the groove comprises the following steps: depositing a composite layer of silicon dioxide and silicon nitride on the silicon epitaxial layer to serve as a hard mask for subsequent trench etching and a barrier layer of a surface planarization process; and defining a groove region on the hard mask plate through a photoetching process, and then etching the silicon epitaxial layer to form a groove.
3. The method according to claim 1, characterized in that:
the field oxide layer may be formed from a combination of thermally grown silicon dioxide and deposited silicon dioxide.
4. The method according to claim 1, characterized in that:
filling source polycrystalline silicon in the groove and carrying out back etching until the top surface of the silicon epitaxial layer is below: polysilicon on the top surface of the silicon epitaxial layer and in the upper portion of the trench is etched back, polysilicon in the lower portion of the trench is retained, and the retained polysilicon is connected to the source electrode.
5. The method according to claim 1, characterized in that:
the gate polysilicon is etched back to a position below the top surface of the silicon epitaxial layerFor filling the dielectric oxide layer.
6. The method according to claim 1, characterized in that:
the dielectric oxide layer within the trench is etched to a level with the top surface of the silicon epitaxial layer.
7. A power MOSFET comprising:
a silicon substrate and a silicon epitaxial layer on the silicon substrate;
a plurality of trenches arranged at intervals and formed in the silicon epitaxial layer;
source polycrystalline silicon formed in the lower parts of the trenches and surrounded by the field oxide layer;
gate polysilicon formed in upper portions of the plurality of trenches and spaced apart from the source polysilicon by high density silicon dioxide; a gate oxide layer surrounds the periphery of the gate polysilicon;
a dielectric oxide layer formed over the gate polysilicon;
the first body areas are arranged at intervals and positioned among the grooves;
a plurality of source regions located above the plurality of first body regions;
a plurality of contact holes extending from a top surface of the silicon epitaxial layer to the first body region, the plurality of contact holes being formed self-aligned with the plurality of trenches,
and etching the contact hole by adopting a dry etching process, wherein in the dry etching process, silicon is etched while the dielectric oxide layer is reserved, and the shape and the inclination angle of the hole are controlled.
8. The power MOSFET of claim 7, wherein: a second body region with high concentration is formed between the bottom of the contact hole and the first body region.
9. An electronic device comprising a power MOSFET according to any one of claims 7-8.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101889334A (en) * | 2007-10-04 | 2010-11-17 | 飞兆半导体公司 | High density FET with integrated schottky |
| CN102270662A (en) * | 2010-06-01 | 2011-12-07 | 万国半导体股份有限公司 | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
| CN111370463A (en) * | 2018-12-26 | 2020-07-03 | 深圳尚阳通科技有限公司 | Trench gate power device and manufacturing method thereof |
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| US8580667B2 (en) * | 2010-12-14 | 2013-11-12 | Alpha And Omega Semiconductor Incorporated | Self aligned trench MOSFET with integrated diode |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101889334A (en) * | 2007-10-04 | 2010-11-17 | 飞兆半导体公司 | High density FET with integrated schottky |
| CN102270662A (en) * | 2010-06-01 | 2011-12-07 | 万国半导体股份有限公司 | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
| CN111370463A (en) * | 2018-12-26 | 2020-07-03 | 深圳尚阳通科技有限公司 | Trench gate power device and manufacturing method thereof |
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