CN112635475A - Stacking structure and preparation method thereof - Google Patents

Stacking structure and preparation method thereof Download PDF

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Publication number
CN112635475A
CN112635475A CN202011504926.6A CN202011504926A CN112635475A CN 112635475 A CN112635475 A CN 112635475A CN 202011504926 A CN202011504926 A CN 202011504926A CN 112635475 A CN112635475 A CN 112635475A
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nitride layer
substrate
layer
nitride
oxygen
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杨事成
张莉
阙凤森
贺晓平
陈冠桦
施生巍
李康
钟磊
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

The application discloses stacked structure and preparation method thereof, wherein, stacked structure includes nitride layer and oxide layer that alternative stack set up, the nitride layer includes at least partly adulterate the oxynitrides layer, just it is adjacent with the oxide layer that is located the nitride layer deviates from one side of the substrate to adulterate the oxynitrides layer, the adulteration oxynitrides layer that so sets up can play the cushioning effect in the etching process, avoided the etching process when from the oxide layer to the nitride layer, the problem of nitride layer damage or defect that causes because the drive mode sudden change, promoted the electricity performance of the three-dimensional NAND memory based on stacked structure preparation.

Description

Stacking structure and preparation method thereof
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a stacked structure and a method for fabricating the same.
Background
In the preparation process of the three-dimensional NAND (NAND) memory, a stacked structure formed by alternately stacking a plurality of layers of nitride and oxide is required to grow, and deep holes are required to be formed in the stacked structure based on an etching process, so that a foundation is laid for the subsequent formation of structures such as silicon columns.
In the practical application process, unnecessary film layer damage or defects can occur in the deep hole etching process of the existing stack structure, and adverse effects are brought to the electrical properties of the three-dimensional NAND memory obtained by subsequent preparation.
Disclosure of Invention
In order to solve the technical problems, the application provides a stacked structure and a preparation method thereof, so as to solve the problem of damage or defects of some films caused in the deep hole etching process of the stacked structure and improve the electrical performance of the prepared three-dimensional NAND memory.
In order to achieve the technical purpose, the embodiment of the application provides the following technical scheme:
a stacked structure applied to a three-dimensional NAND memory, the stacked structure being disposed based on a substrate, the stacked structure comprising:
nitride layers and oxide layers alternately stacked on the substrate;
the nitride layer comprises at least a portion of a doped oxynitride layer adjacent to an oxide layer on a side of the nitride layer facing away from the substrate.
Optionally, the nitride layer includes:
a first nitride layer;
a first doped oxynitride layer on a side of the first nitride layer facing away from the substrate.
Optionally, the first nitride layer comprises a silicon nitride layer;
the first oxygen-doped nitride layer comprises an oxygen-doped silicon nitride layer.
Optionally, the nitride layer includes:
a second doped oxynitride layer having an increasing concentration of oxygen along a first direction, the first direction being perpendicular to the substrate and directed from the substrate toward the stacked structure.
Optionally, the second oxygen-doped nitride layer includes an oxygen-doped silicon nitride layer.
Optionally, the method further includes:
a via through the stacked structure and exposing the substrate.
A preparation method of a stacked structure is applied to a three-dimensional NAND memory, and comprises the following steps:
providing a substrate;
alternately depositing nitride layers and oxide layers on the substrate in sequence to form nitride layers and oxide layers alternately stacked on the substrate; the nitride layer comprises at least a portion of a doped oxynitride layer adjacent to an oxide layer on a side of the nitride layer facing away from the substrate.
Optionally, the sequentially and alternately depositing a nitride layer and an oxide layer on the substrate includes:
and alternately depositing a nitride layer and an oxide layer on the substrate in sequence, and introducing oxygen-containing gas at least in a back-end process for forming the nitride layer.
Optionally, the sequentially and alternately depositing a nitride layer and an oxide layer on the substrate includes:
and alternately depositing nitride layers and oxide layers on the substrate in sequence, and introducing oxygen-containing gas during the deposition of the nitride layers, wherein the introduction amount of the oxygen-containing gas is increased along with the progress of the deposition process of the nitride layers.
Optionally, the oxygen-containing gas comprises: nitric oxide gas or nitrous oxide gas.
It can be seen from the foregoing technical solutions that the present application provides a stacked structure and a method for manufacturing the same, where the stacked structure includes a nitride layer and an oxide layer that are alternately stacked, where the nitride layer includes at least a portion of an oxynitride doped layer, and the oxynitride doped layer is adjacent to the oxide layer on a side of the nitride layer away from the substrate, and the thus-disposed oxygen-doped nitride layer may play a role in buffering during an etching process, thereby avoiding a problem of damage or defect of the nitride layer due to abrupt change of a driving manner when an etching process is performed from the oxide layer to the nitride layer, and improving electrical performance of a three-dimensional NAND memory manufactured based on the stacked structure.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a stacked structure according to an embodiment of the present application;
FIG. 2 is a cross-sectional view of a stacked structure in the prior art;
FIG. 3 is a schematic diagram of a prior art notch in the formation of a deep hole in a stacked structure;
FIG. 4 is a schematic cross-sectional view of a stacked structure according to another embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a stacked structure according to yet another embodiment of the present application;
fig. 6 is a schematic flow chart of a method for manufacturing a stacked structure according to an embodiment of the present disclosure;
fig. 7 is a schematic flow chart of a method for fabricating a stacked structure according to another embodiment of the present disclosure;
fig. 8 is a schematic flow chart of a method for manufacturing a stacked structure according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the present application provides a stacked structure, as shown in fig. 1, applied to a three-dimensional NAND memory, the stacked structure being disposed on a substrate 30, the stacked structure including:
nitride layers 20 and oxide layers 10 alternately stacked on the substrate 30;
the nitride layer 20 comprises at least a partially doped oxynitride layer adjacent to the oxide layer 10 on the side of the nitride layer 20 facing away from the substrate 30.
The inventor has found through research that, in the prior art, the stacked structure is shown in fig. 2, and the stacked structure shown in fig. 2 is formed by simply alternately arranging the nitride layer 1 and the oxide layer 2, and after deep hole etching, a gap De of the nitride layer 1 shown in fig. 3 is formed, and the gap De is located on a contact surface between the nitride layer 1 and the oxide layer 2 of an upper layer (i.e., a direction away from the substrate 3).
Further studies have found that the etching principle for the oxide layer 2 is Ion Driven (Ion drive) during dry etching, i.e. the etching process is mainly carried out by means of the etching reaction of the etching gas with the oxide layer 2, and that the etching principle for the nitride layer 1 is Chemical Driven (Chemical drive) and i.e. the etching process is mainly carried out by means of Ion bombardment in the etching gas. The immediate switching of the two different driving modes when etching the nitride layer 1 after the oxide layer 2 has been etched results in the formation of a gap De in the nitride layer 1 as shown in fig. 3.
Therefore, in the embodiment of the present application, still referring to fig. 1, at least a portion of the structure above the nitride layer 20 is configured as an oxynitride doped layer, so that the oxynitride doped layer plays a role of buffering during the etching process, thereby avoiding the problem of the gap of the nitride layer 20 caused by the immediate switching of two different driving manners of the dry etching, and improving the electrical performance of the three-dimensional NAND memory prepared based on the stacked structure.
On the basis of the above embodiment, in an embodiment of the present application, still referring to fig. 1, the nitride layer 20 includes:
a first nitride layer 21;
a first doped oxynitride layer 22 on the side of the first nitride layer 21 facing away from the substrate 30.
Optionally, the first nitride layer 21 includes a silicon nitride layer;
the first doped oxynitride layer 22 comprises an oxygen-doped silicon nitride layer.
In this embodiment, the nitride layer 20 is divided into an upper layer and a lower layer, and the upper layer is an oxygen-doped nitride structure, i.e., the first oxygen-doped nitride oxide layer 22. The underlying structure is a first nitride layer 21, and the deposition of the oxide layer 10 may include: the nitride layer 20 is normally prepared in the first half of the deposition process to form the first nitride layer 21, and an oxygen-containing gas is additionally introduced in the second half of the deposition process to form the first doped oxynitride layer 22, and the time period of introducing the oxygen-containing gas can be obtained by experiments according to different processes, for example, assuming that the deposition process time period of a certain nitride layer 20 is 15s, the optimal time period of introducing the oxygen-containing gas can be determined by experiments (for example, introducing the oxygen-containing gas in different time periods such as 2s, 3s, 4s, 5s, and the like, and performing deep hole etching verification).
On the basis of the above embodiment, in another embodiment of the present application, as shown in fig. 4, the nitride layer 20 includes:
a second doped oxynitride layer 23, wherein the oxygen concentration of the second doped oxynitride layer 23 increases along a first direction, the first direction is perpendicular to the substrate 30 and is directed from the substrate 30 to the stacked structure.
In the present embodiment, the entire nitride layer 20 is an oxygen-doped structure, but the oxygen-doped concentration increases from bottom to top, so that the upper second oxygen-doped nitride layer 23 functions as a good buffer, and the lower second oxygen-doped nitride layer 23 functions as the nitride layer 20.
On the basis of the above-described embodiment, in a further embodiment of the present application, as shown in fig. 5, the stack structure further includes:
through the stacked structure and exposes the vias 24 of the substrate 30.
The vias 24 may be used to deposit structures such as silicon pillars during the fabrication process of the three-dimensional NAND memory.
The following describes a method for manufacturing a stacked structure provided in an embodiment of the present application, and the method for manufacturing a stacked structure described below and the stacked structure described above may be referred to in correspondence.
Correspondingly, an embodiment of the present application further provides a method for manufacturing a stacked structure, as shown in fig. 6, and the method is applied to a three-dimensional NAND memory, and the method for manufacturing the stacked structure includes:
s101: providing a substrate;
s102: alternately depositing nitride layers and oxide layers on the substrate in sequence to form nitride layers and oxide layers alternately stacked on the substrate; the nitride layer comprises at least a portion of a doped oxynitride layer adjacent to an oxide layer on a side of the nitride layer facing away from the substrate.
Referring to fig. 1, in this embodiment, at least a portion of the structure above the nitride layer of the stacked structure is configured as an oxynitride doped layer, so that the oxynitride doped layer plays a role in buffering during etching, the problem of a gap in the nitride layer caused by the immediate switching of two different driving methods of dry etching is avoided, and the electrical performance of the three-dimensional NAND memory prepared based on the stacked structure is improved.
Optionally, referring to fig. 7, the alternately depositing a nitride layer and an oxide layer on the substrate in sequence includes:
s1021: and alternately depositing a nitride layer and an oxide layer on the substrate in sequence, and introducing oxygen-containing gas at least in a back-end process for forming the nitride layer.
The stacked structure prepared in this embodiment referring to fig. 1, the nitride layer includes:
a first nitride layer;
a first doped oxynitride layer on a side of the first nitride layer facing away from the substrate.
Optionally, the first nitride layer comprises a silicon nitride layer;
the first oxygen-doped nitride layer comprises an oxygen-doped silicon nitride layer.
In this embodiment, the nitride layer is divided into an upper layer and a lower layer, and the upper layer is an oxygen-doped nitride structure, i.e., the first oxygen-doped nitride oxide layer. The underlying structure is a first nitride layer, and the deposition of the oxide layer may include: normally preparing a nitride layer in the first half of the deposition process to form the first nitride layer, additionally introducing an oxygen-containing gas in the second half of the deposition process to form the first doped oxynitride layer, wherein the time period of introducing the oxygen-containing gas can be obtained by experiments according to different processes, for example, assuming that the time period of a deposition process of a certain nitride layer is 15s, the optimal time period of introducing the oxygen-containing gas can be determined by experiments (for example, introducing the oxygen-containing gas in different time periods such as 2s, 3s, 4s, 5s and the like and performing deep hole etching verification).
Optionally, referring to fig. 8, the alternately depositing a nitride layer and an oxide layer on the substrate in sequence includes:
s1022: and alternately depositing nitride layers and oxide layers on the substrate in sequence, and introducing oxygen-containing gas during the deposition of the nitride layers, wherein the introduction amount of the oxygen-containing gas is increased along with the progress of the deposition process of the nitride layers.
The stacked structure prepared in this embodiment referring to fig. 4, the nitride layer includes:
a second doped oxynitride layer having an increasing concentration of oxygen along a first direction, the first direction being perpendicular to the substrate and directed from the substrate toward the stacked structure.
In this embodiment, the entire nitride layer is an oxygen-doped structure, but the oxygen concentration increases from bottom to top, so that the second oxygen-doped nitride layer on the upper layer plays a good role in buffering, and the second oxygen-doped nitride layer on the lower layer plays a role in the nitride layer.
Optionally, the oxygen-containing gas comprises: nitric oxide gas or nitrous oxide gas.
In summary, the embodiment of the present application provides a stacked structure and a method for manufacturing the same, wherein the stacked structure includes a nitride layer and an oxide layer that are alternately stacked, the nitride layer includes at least a portion of an oxynitride doped layer, and the oxynitride doped layer is adjacent to the oxide layer located on a side of the nitride layer away from the substrate, so that the oxygen-doped nitride layer that is disposed can play a role in buffering during etching, thereby avoiding the problem of damage or defect of the nitride layer due to abrupt change of a driving manner when an etching process is performed from the oxide layer to the nitride layer, and improving the electrical performance of a three-dimensional NAND memory manufactured based on the stacked structure.
Features described in the embodiments in the present specification may be replaced with or combined with each other, each embodiment is described with a focus on differences from other embodiments, and the same and similar portions among the embodiments may be referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A stack structure applied to a three-dimensional NAND memory, the stack structure being provided based on a substrate, the stack structure comprising:
nitride layers and oxide layers alternately stacked on the substrate;
the nitride layer comprises at least a portion of a doped oxynitride layer adjacent to an oxide layer on a side of the nitride layer facing away from the substrate.
2. The stack structure of claim 1, wherein the nitride layer comprises:
a first nitride layer;
a first doped oxynitride layer on a side of the first nitride layer facing away from the substrate.
3. The stack structure of claim 2, wherein the first nitride layer comprises a silicon nitride layer;
the first oxygen-doped nitride layer comprises an oxygen-doped silicon nitride layer.
4. The stack structure of claim 1, wherein the nitride layer comprises:
a second doped oxynitride layer having an increasing concentration of oxygen along a first direction, the first direction being perpendicular to the substrate and directed from the substrate toward the stacked structure.
5. The stack structure of claim 4, wherein the second oxygen-doped nitride layer comprises an oxygen-doped silicon nitride layer.
6. The stack structure of claim 1, further comprising:
a via through the stacked structure and exposing the substrate.
7. A preparation method of a stacked structure is applied to a three-dimensional NAND memory, and comprises the following steps:
providing a substrate;
alternately depositing nitride layers and oxide layers on the substrate in sequence to form nitride layers and oxide layers alternately stacked on the substrate; the nitride layer comprises at least a portion of a doped oxynitride layer adjacent to an oxide layer on a side of the nitride layer facing away from the substrate.
8. The method of claim 7, wherein the sequentially alternating deposition of nitride and oxide layers on the substrate comprises:
and alternately depositing a nitride layer and an oxide layer on the substrate in sequence, and introducing oxygen-containing gas at least in a back-end process for forming the nitride layer.
9. The method of claim 8, wherein the sequentially alternating deposition of nitride and oxide layers on the substrate comprises:
and alternately depositing nitride layers and oxide layers on the substrate in sequence, and introducing oxygen-containing gas during the deposition of the nitride layers, wherein the introduction amount of the oxygen-containing gas is increased along with the progress of the deposition process of the nitride layers.
10. The method of any one of claims 8 or 9, wherein the oxygen-containing gas comprises: nitric oxide gas or nitrous oxide gas.
CN202011504926.6A 2020-12-18 2020-12-18 Stacking structure and preparation method thereof Pending CN112635475A (en)

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