CN112634958A - Circuit for reducing SRAM sleep state electric leakage - Google Patents

Circuit for reducing SRAM sleep state electric leakage Download PDF

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Publication number
CN112634958A
CN112634958A CN202011608334.9A CN202011608334A CN112634958A CN 112634958 A CN112634958 A CN 112634958A CN 202011608334 A CN202011608334 A CN 202011608334A CN 112634958 A CN112634958 A CN 112634958A
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pmos
electrode
tube
nmos
transistor
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李晓敏
唐小青
王强
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Nanjing Low Power Chip Technology Research Institute Co ltd
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Nanjing Low Power Chip Technology Research Institute Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Abstract

The invention discloses a circuit for reducing SRAM sleep state electric leakage, which comprises a PVT tracking module and an array refreshing module; the PVT tracking module is used for tracking temperature variation and global process deviation and outputting a reference voltage value; and the array refreshing module is used for dynamically adjusting the power supply voltage of the SRAM memory array according to the output reference voltage value of the PVT tracking circuit. According to the invention, a series of connected MOS tubes are used for dividing the power voltage, and the voltage values at a plurality of voltage dividing points are used as reference values to supply power to a data-holding copying unit, so that the proper voltage of the turning point under different PVT conditions is tracked; meanwhile, the array adopts an alternate power supply mode, so that the data can be kept in a perfect way under an extremely low holding voltage in a sleep state, and lower array leakage is brought.

Description

Circuit for reducing SRAM sleep state electric leakage
Technical Field
The invention belongs to the technical field of low-power-consumption SRAM (static random access memory), and particularly relates to a circuit for reducing sleep-state electric leakage of the SRAM.
Background
Due to the characteristics of mobile applications, current internet of things (IoT) devices are in a sleep state most of the time, and their static energy loss ratio is gradually comparable to or even higher than the energy consumption in the working state. Therefore, the power consumption of the SRAM in the sleep state is reduced, the static energy loss of the whole system can be greatly reduced, and the endurance time of equipment is prolonged. The leakage of the SRAM array occupies the main component of the leakage in the standby mode, and along with the migration of the process, the sub-threshold leakage and the grid leakage of the transistor become the main components for limiting the reduction of the power consumption in the sleep mode of the SRAM. The prior design is biased to use a clamping structure, the voltage value of the SRAM in a sleep mode is singly reduced, the adaptability to process change is not achieved, and the reduction of electric leakage is directly realized passively. Therefore, it is important to track the process variation of the SRAM and enhance the data retention capability of the array, and to reduce the leakage current of the SRAM.
Disclosure of Invention
The purpose of the invention is as follows: in order to solve the above problems, the present invention provides a circuit for reducing SRAM sleep state leakage, which tracks temperature variation and global process deviation through a PVT tracking module, and outputs a reference voltage value for dynamically adjusting a supply voltage of an SRAM memory array, thereby enhancing a data retention capability of an SRAM memory cell.
The technical scheme is as follows: in order to realize the purpose of the invention, the technical scheme adopted by the invention is as follows: a circuit for reducing SRAM sleep state leakage comprises a PVT tracking module and an array refreshing module; the PVT tracking module is used for tracking temperature variation and global process deviation and outputting a reference voltage value; and the array refreshing module is used for dynamically adjusting the power supply voltage of the SRAM memory array according to the output reference voltage value of the PVT tracking circuit.
Further, the PVT tracking module comprises a plurality of MOS tubes, a plurality of copying units, an overturning detection circuit and an output driving module.
Further, the PVT tracking module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor; a first copy unit, a second copy unit, a third copy unit, a fourth copy unit, a fifth copy unit, a sixth copy unit, a seventh copy unit, an eighth copy unit, and a ninth copy unit; the device comprises a turnover detection circuit and an output driving module.
The source electrode of the first PMOS tube is connected to a power supply VDD; the grid electrode of the first PMOS tube is respectively connected with the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube and the source end of the first copying unit; the source electrode of the first NMOS tube is respectively connected with the source electrode of the second PMOS tube and the source end of the second copying unit; the grid electrode of the second PMOS tube is respectively connected with the drain electrode of the second PMOS tube, the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube and the source end of the third copying unit; the source electrode of the second NMOS tube is respectively connected with the source electrode of the third PMOS tube and the source end of the fourth copying unit; the grid electrode of the third PMOS tube is respectively connected with the drain electrode of the third PMOS tube, the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube and the source end of the fifth copying unit; the source electrode of the third NMOS tube is respectively connected with the source electrode of the fourth PMOS tube and the source end of the sixth copying unit; the grid electrode of the fourth PMOS tube is respectively connected with the drain electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube and the source end of the seventh copying unit; the source electrode of the fourth NMOS tube is respectively connected with the source electrode of the fifth PMOS tube and the source end of the eighth copying unit; the grid electrode of the fifth PMOS tube is respectively connected with the drain electrode of the fifth PMOS tube, the drain electrode of the fifth NMOS tube, the grid electrode of the fifth NMOS tube and the source end of the ninth copy unit; the source electrode of the fifth NMOS tube is connected to the ground.
The input end of the turnover detection circuit is connected with the output end of the output driving module, and the reference voltage output end of the output driving module is connected with the power supply end of the SRAM storage array.
Furthermore, the array refresh circuit includes a first sleep control signal, a second sleep control signal, a first bit line, a second bit line, a word line, a first buffer gate, a second buffer gate, a third buffer gate, a fourth buffer gate, a first tri-state gate, a second tri-state gate, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor P.
The grid electrode of the sixth NMOS tube is respectively connected with the drain electrode of the seventh NMOS tube, the grid electrode of the ninth PMOS tube, the drain electrode of the tenth PMOS tube and the drain electrode of the eleventh NMOS tube; the drain electrode of the sixth NMOS tube is respectively connected with the grid electrode of the seventh NMOS tube, the drain electrode of the ninth PMOS tube, the grid electrode of the tenth PMOS tube and the drain electrode of the tenth NMOS tube; the source electrode of the sixth NMOS tube is respectively connected with the drain electrode of the eighth NMOS tube and the output of the third buffer gate; the source electrode of the seventh NMOS tube is respectively connected with the drain electrode of the ninth NMOS tube and the output of the fourth buffer gate; the grid electrode of the eighth NMOS tube is connected with the grid electrode of the ninth NMOS tube and the second sleep control signal respectively; the source electrode of the eighth NMOS tube is connected with the ground wire; the source electrode of the ninth NMOS tube is connected with the ground wire; the source electrode of the ninth PMOS tube is respectively connected with the drain electrode of the seventh PMOS tube, the output of the first tri-state gate and the output of the first buffer gate; the source electrode of the tenth PMOS tube is respectively connected with the drain electrode of the eighth PMOS tube, the output of the second tri-state gate and the output of the second buffer gate; the grid electrode of the seventh PMOS tube is connected with the grid electrode of the eighth PMOS tube and the first sleep control signal; the source electrode of the seventh PMOS tube is connected to the power supply; and the source electrode of the eighth PMOS tube is connected to the power supply.
Further, the array refresh module alternately supplies power to the SRAM memory array.
Further, when the sleep control signal is turned over, the SRAM enters a sleep mode, and the refresh switching process of the sleep state is divided into four stages: in the first stage, the first buffer gate, the second tri-state gate and the third buffer gate are not enabled; in the second stage, all the buffer gates and the tri-state gates are not enabled; in the third stage, the second buffer gate, the first tri-state gate and the fourth buffer gate are not enabled; in the fourth stage, all buffer gates and tri-state gates are disabled.
Has the advantages that: according to the invention, a series of connected MOS tubes are used for dividing the power voltage, and the voltage values at a plurality of voltage dividing points are used as reference values to supply power to a data-holding copying unit, so that the proper voltage of the turning point under different PVT conditions is tracked; meanwhile, the array adopts an alternate power supply mode, so that the data can be kept in a perfect way under an extremely low holding voltage in a sleep state, and lower array leakage is brought.
Drawings
FIG. 1 is a circuit diagram of the present invention for reducing SRAM sleep state leakage;
FIG. 2 is a graph showing the change of supply voltage when SRAM enters a sleep state in TT process at 25 ℃.
Detailed Description
The technical solution of the present invention is further described below with reference to the accompanying drawings and examples.
As shown in fig. 1, the circuit for reducing SRAM sleep state leakage according to the present invention includes a PVT tracking module 1 and an array refresh module 2. The PVT tracking module is used for tracking temperature variation and global process deviation and outputting a reference voltage value; and the array refreshing module is used for dynamically adjusting the power supply voltage of the SRAM memory array according to the output reference voltage value of the PVT tracking module.
The PVT tracking module comprises a plurality of MOS tubes, a plurality of copying units, an overturning detection circuit and an output driving module. The PVT tracking module is used for tracking the minimum reference voltage value of data retention meeting the unit yield under the global process deviation and temperature variation, and outputting the reference voltage value to the power supply end of the SRAM storage array through the output driving module to retain data for the SRAM storage array.
On the basis, the array refreshing module refreshes the power supply voltage of the SRAM memory array, dynamically adjusts the power supply voltage of the SRAM memory array according to the output reference voltage value of the PVT tracking module, and strengthens the data retention capacity of the SRAM memory array. The array refreshing module supplies power for the SRAM in an alternating mode, so that the power supply voltage of the SRAM in a holding state is further reduced while the storage capacity is guaranteed.
The PVT tracking module comprises a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4 and a fifth NMOS transistor N5; a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4 and a fifth PMOS transistor P5; a first copy unit 1, a second copy unit 2, a third copy unit 3, a fourth copy unit 4, a fifth copy unit 5, a sixth copy unit 6, a seventh copy unit 7, an eighth copy unit 8, a ninth copy unit 9; the device comprises a turnover detection circuit and an output driving module.
The source electrode of the first PMOS tube P1 is connected to a power supply VDD, and the gate electrode of the first PMOS tube P1 is respectively connected to the drain electrode of the first PMOS tube P1, the drain electrode of the first NMOS tube N1, the gate electrode of the first NMOS tube N1 and the source end Vdda1 of the first copy unit 1; the source electrode of the first NMOS transistor N1 is respectively connected with the source electrode of the second PMOS transistor P2 and the source end Vdda2 of the second copying unit 2; the grid electrode of the second PMOS tube P2 is respectively connected with the drain electrode of the second PMOS tube P2, the drain electrode of the second NMOS tube N2, the grid electrode of the second NMOS tube N2 and the source end Vdda3 of the third copying unit 3; the source electrode of the second NMOS transistor N2 is respectively connected with the source electrode of the third PMOS transistor P3 and the source end Vdda4 of the fourth copying unit 4; the grid electrode of the third PMOS transistor P3 is respectively connected with the drain electrode of the third PMOS transistor P3, the drain electrode of the third NMOS transistor N3, the grid electrode of the third NMOS transistor N3 and the source end Vdda5 of the fifth replica unit 5; the source electrode of the third NMOS transistor N3 is respectively connected with the source electrode of the fourth PMOS transistor P4 and the source end Vdda6 of the sixth replication unit 6; the grid electrode of the fourth PMOS tube P4 is respectively connected with the drain electrode of the fourth PMOS tube P4, the drain electrode of the fourth NMOS tube N4, the grid electrode of the fourth NMOS tube N4 and the source end Vdda7 of the seventh replica unit 7; the source electrode of the fourth NMOS transistor N4 is respectively connected to the source electrode of the fifth PMOS transistor P5 and the source end Vdda8 of the eighth replica cell 8; the grid electrode of the fifth PMOS tube P5 is respectively connected with the drain electrode of the fifth PMOS tube P5, the drain electrode of the fifth NMOS tube N5, the grid electrode of the fifth NMOS tube N5 and the source end Vdda9 of the ninth copy unit 9; the source of the fifth NMOS transistor N5 is connected to ground.
An input end IN of the roll-over detection circuit is respectively connected with an output end OUT1 of the first copy unit 1, an output end OUT2 of the second copy unit 2, an output end OUT3 of the third copy unit 3, an output end OUT4 of the fourth copy unit 4, an output end OUT5 of the fifth copy unit 5, an output end OUT6 of the sixth copy unit 6, an output end OUT7 of the seventh copy unit 7, an output end OUT8 of the eighth copy unit 8 and an output end OUT9 of the ninth copy unit 9; an output end Fail of the turnover detection circuit is connected to a detection end Detect of the output driving module, and a reference voltage output end Vref of the output driving module is connected to a power supply end Vddarray of the SRAM array.
The array refreshing module comprises a first sleep control signal SLP, a second sleep control signal SLP, a first bit line BL, a second bit line BLB, a word line WL, a first buffer gate T1, a second buffer gate T2, a third buffer gate T3, a fourth buffer gate T4, a first tri-state gate D1 and a second tri-state gate D2; a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11; a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, and a tenth PMOS transistor P10.
The grid electrode of the sixth NMOS transistor N6 is respectively connected with the drain electrode of the seventh NMOS transistor N7, the grid electrode of the ninth PMOS transistor P9, the drain electrode of the tenth PMOS transistor P10 and the drain electrode of the eleventh NMOS transistor N11; the drain electrode of the sixth NMOS transistor N6 is respectively connected with the gate electrode of the seventh NMOS transistor N7, the drain electrode of the ninth PMOS transistor P9, the gate electrode of the tenth PMOS transistor P10 and the drain electrode of the tenth NMOS transistor N10; the source electrode of the sixth NMOS transistor N6 is respectively connected with the drain electrode of the eighth NMOS transistor N8 and the output of the third buffer gate T3; the source electrode of the seventh NMOS transistor N7 is respectively connected with the drain electrode of the ninth NMOS transistor N9 and the output of the fourth buffer gate T4; the grid electrode of the eighth NMOS tube N8 is respectively connected with the grid electrode of the ninth NMOS tube N9 and the second sleep control signal-SLP; the source electrode of the eighth NMOS tube N8 is connected with the ground wire; the source electrode of the ninth NMOS tube N9 is connected with the ground wire; the source electrode of the ninth PMOS pipe P9 is respectively connected with the drain electrode of the seventh PMOS pipe P7, the output of the first tri-state gate D1 and the output of the first buffer gate T1; the source electrode of the tenth PMOS pipe P10 is respectively connected with the drain electrode of the eighth PMOS pipe P8, the output of the second tri-state gate D2 and the output of the second buffer gate T2; the grid electrode of the seventh PMOS pipe P7 is connected with the grid electrode of the eighth PMOS pipe P8 and the first sleep control signal SLP; the source electrode of the seventh PMOS pipe P7 is connected with the power supply VDD; the source of the eighth PMOS transistor P8 is connected to the power supply VDD.
And when the sleep control signal is turned over, the SRAM enters a sleep mode. The refresh switching process of the sleep state is divided into four stages: in the first stage, the first buffer gate T1, the second tri-state gate D2 and the third buffer gate T3 are not enabled; in the second stage, all the buffer gates and the tri-state gates are not enabled; in the third stage, the second buffer gate T2, the first tri-state gate D1 and the fourth buffer gate T4 are not enabled; in the fourth stage, all buffer gates and tri-state gates are disabled. In the sleep mode, the four stages are circulated as one period to realize data retention.
As shown in fig. 2, in this embodiment, under the TT process condition, at a temperature of 25 ℃, the supply voltage of the SRAM changes after the SRAM enters the sleep state.
The invention uses series voltage nodes as reference values to supply power to the copy unit in a holding state, thereby tracking proper holding voltage under different PVT conditions, meanwhile, the data storage capacity of the storage unit is strengthened by compressing the drain-source voltage of the MOS tube in a closed state, and the storage unit in a sleep state can carry out data holding under extremely low holding voltage by means of power supply alternate switching, thereby greatly reducing static electric leakage.

Claims (6)

1. A circuit for reducing SRAM sleep state leakage is characterized by comprising a PVT tracking module (1) and an array refreshing module (2); the PVT tracking module is used for tracking temperature variation and global process deviation and outputting a reference voltage value; and the array refreshing module is used for dynamically adjusting the power supply voltage of the SRAM memory array according to the output reference voltage value of the PVT tracking circuit.
2. The circuit for reducing SRAM sleep state leakage according to claim 1, wherein the PVT tracking module comprises a plurality of MOS transistors, a plurality of replica cells, a flip detection circuit and an output driving module.
3. The circuit for reducing SRAM sleep state leakage according to claim 2, wherein the PVT tracking module comprises a first NMOS transistor (N1), a second NMOS transistor (N2), a third NMOS transistor (N3), a fourth NMOS transistor (N4), a fifth NMOS transistor (N5), a first PMOS transistor (P1), a second PMOS transistor (P2), a third PMOS transistor (P3), a fourth PMOS transistor (P4), and a fifth PMOS transistor (P5); a first copy unit (1), a second copy unit (2), a third copy unit (3), a fourth copy unit (4), a fifth copy unit (5), a sixth copy unit (6), a seventh copy unit (7), an eighth copy unit (8) and a ninth copy unit (9); the overturning detection circuit and the output driving module;
the source electrode of the first PMOS pipe (P1) is connected with a power supply (VDD); the grid electrode of the first PMOS tube (P1) is respectively connected with the drain electrode of the first PMOS tube (P1), the drain electrode of the first NMOS tube (N1), the grid electrode of the first NMOS tube (N1) and the source end (Vdda1) of the first copy unit (1); the source electrode of the first NMOS transistor (N1) is respectively connected with the source electrode of the second PMOS transistor (P2) and the source electrode (Vdda2) of the second copy unit (2); the grid electrode of the second PMOS tube (P2) is respectively connected with the drain electrode of the second PMOS tube (P2), the drain electrode of the second NMOS tube (N2), the grid electrode of the second NMOS tube (N2) and the source end (Vdda3) of the third copy unit (3); the source electrode of the second NMOS transistor (N2) is respectively connected with the source electrode of the third PMOS transistor (P3) and the source electrode (Vdda4) of the fourth copying unit (4); the grid electrode of the third PMOS tube (P3) is respectively connected with the drain electrode of the third PMOS tube (P3), the drain electrode of the third NMOS tube (N3), the grid electrode of the third NMOS tube (N3) and the source end (Vdda5) of the fifth copying unit (5); the source electrode of the third NMOS transistor (N3) is respectively connected with the source electrode of the fourth PMOS transistor (P4) and the source electrode (Vdda6) of the sixth copying unit (6); the grid electrode of the fourth PMOS tube (P4) is respectively connected with the drain electrode of the fourth PMOS tube (P4), the drain electrode of the fourth NMOS tube (N4), the grid electrode of the fourth NMOS tube (N4) and the source end (Vdda7) of the seventh replica cell (7); the source electrode of the fourth NMOS transistor (N4) is respectively connected with the source electrode of the fifth PMOS transistor (P5) and the source electrode (Vdda8) of the eighth copying unit (8); the grid electrode of the fifth PMOS tube (P5) is respectively connected with the drain electrode of the fifth PMOS tube (P5), the drain electrode of the fifth NMOS tube (N5), the grid electrode of the fifth NMOS tube (N5) and the source end (Vdda9) of the ninth replica cell (9); the source electrode of the fifth NMOS tube (N5) is connected with the ground line;
an input end (IN) of the overturn detection circuit is respectively connected with an output end (OUT1) of the first copy unit (1), an output end (OUT2) of the second copy unit (2), an output end (OUT3) of the third copy unit (3), an output end (OUT4) of the fourth copy unit (4), an output end (OUT5) of the fifth copy unit (5), an output end (OUT6) of the sixth copy unit (6), an output end (OUT7) of the seventh copy unit (7), an output end (OUT8) of the eighth copy unit (8) and an output end (OUT9) of the ninth copy unit (9); the output end (Fail) of the overturn detection circuit is connected with the detection end (Detect) of the output driving module, and the reference voltage output end (Vref) of the output driving module is connected with the power supply end (Vddarray) of the SRAM storage array.
4. The circuit for reducing SRAM sleep state leakage of claim 1, wherein the array refresh module comprises a first sleep control Signal (SLP), a second sleep control Signal (SLP), a first Bit Line (BL), a second Bit Line (BLB), a Word Line (WL), a first buffer gate (T1), a second buffer gate (T2), a third buffer gate (T3), a fourth buffer gate (T4), a first tri-state gate (D1), a second tri-state gate (D2), a sixth NMOS transistor (N6), a seventh NMOS transistor (N7), an eighth NMOS transistor (N8), a ninth NMOS transistor (N9), a tenth NMOS transistor (N10), an eleventh NMOS transistor (N11), a seventh PMOS transistor (P7), an eighth PMOS transistor (P8), a ninth PMOS transistor (P9), and a tenth PMOS transistor (P10);
the grid electrode of the sixth NMOS transistor (N6) is respectively connected with the drain electrode of the seventh NMOS transistor (N7), the grid electrode of the ninth PMOS transistor (P9), the drain electrode of the tenth PMOS transistor (P10) and the drain electrode of the eleventh NMOS transistor (N11); the drain electrode of the sixth NMOS tube (N6) is respectively connected with the gate electrode of the seventh NMOS tube (N7), the drain electrode of the ninth PMOS tube (P9), the gate electrode of the tenth PMOS tube (P10) and the drain electrode of the tenth NMOS tube (N10); the source electrode of the sixth NMOS tube (N6) is respectively connected with the drain electrode of the eighth NMOS tube (N8) and the output of the third buffer gate (T3); the source electrode of the seventh NMOS transistor (N7) is respectively connected with the drain electrode of the ninth NMOS transistor (N9) and the output of the fourth buffer gate (T4); the grid electrode of the eighth NMOS tube (N8) is respectively connected with the grid electrode of the ninth NMOS tube (N9) and the second sleep control signal (-SLP); the source electrode of the eighth NMOS tube (N8) is connected with the ground wire; the source electrode of the ninth NMOS tube (N9) is connected with the ground wire; the source electrode of the ninth PMOS pipe (P9) is respectively connected with the drain electrode of the seventh PMOS pipe (P7), the output of the first tri-state gate (D1) and the output of the first buffer gate (T1); the source electrode of the tenth PMOS pipe (P10) is respectively connected with the drain electrode of the eighth PMOS pipe (P8), the output of the second tri-state gate (D2) and the output of the second buffer gate (T2); the grid electrode of the seventh PMOS pipe (P7) is connected with the grid electrode of the eighth PMOS pipe (P8) and the first sleep control Signal (SLP); the source electrode of the seventh PMOS tube (P7) is connected with the power supply (VDD); the source of the eighth PMOS transistor (P8) is connected to the power supply (VDD).
5. The circuit of claim 1, wherein the array refresh module alternately powers the SRAM memory array.
6. The circuit according to claim 5, wherein when the sleep control signal is inverted, the SRAM enters a sleep mode, and the refresh switching process of the sleep state is divided into four stages: in the first stage, the first buffer gate (T1), the second tri-state gate (D2) and the third buffer gate (T3) are not enabled; in the second stage, all the buffer gates and the tri-state gates are not enabled; in the third stage, the second buffer gate (T2), the first tri-state gate (D1) and the fourth buffer gate (T4) are not enabled; in the fourth stage, all buffer gates and tri-state gates are disabled.
CN202011608334.9A 2020-12-30 2020-12-30 Circuit for reducing SRAM sleep state electric leakage Pending CN112634958A (en)

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