CN112631956B - Data processing method and device, electronic equipment and storage medium - Google Patents
Data processing method and device, electronic equipment and storage medium Download PDFInfo
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- CN112631956B CN112631956B CN202011545768.9A CN202011545768A CN112631956B CN 112631956 B CN112631956 B CN 112631956B CN 202011545768 A CN202011545768 A CN 202011545768A CN 112631956 B CN112631956 B CN 112631956B
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Abstract
A data processing method and device, electronic equipment and storage medium, the data processing method includes: responding to a first storage address request initiated by a processing unit, reading first data stored in a first storage address of a first storage unit, and returning the first data to a second storage unit, wherein the first storage address request comprises the first storage address; and in response to the processing unit initiating a second memory address request within a preset time threshold after the second memory unit returns the first data to the processing unit, determining whether to perform a chained data prefetch operation based on the first data and the second memory address request, the second memory address request including a second memory address. The data processing method can determine whether the judging process needs to be executed according to the time when the processing unit initiates the second storage address request before judging whether the chained data prefetching operation is executed or not based on the first data and the second storage address request, thereby reducing unnecessary operation flows.
Description
Technical Field
The embodiment of the disclosure relates to a data processing method and device, an electronic device and a storage medium.
Background
During operation of the processor, the processor needs to read from main memory the corresponding data needed to perform the data operation. However, the processor needs to read data from the main memory for a long time, so a multi-level cache (cache) manner is generally adopted in the current chip design for caching the data required to be read by the processor. In order to further reduce the delay of data acquisition, a data prefetching method is also generally adopted to load data required by the processor into a cache in advance during operation, so as to reduce the delay time of the processor in acquiring the data.
Disclosure of Invention
At least one embodiment of the present disclosure provides a data processing method, including: responding to a first storage address request initiated by a processing unit, reading first data stored in a first storage address of a first storage unit, and returning the first data to a second storage unit, wherein the first storage address request comprises the first storage address; and in response to the processing unit initiating a second memory address request within a preset time threshold after the second memory unit returns the first data to the processing unit, determining whether to perform a chained data prefetch operation based on the first data and the second memory address request, the second memory address request including a second memory address.
For example, the data processing method provided by an embodiment of the present disclosure further includes: in response to the processing unit initiating the second memory address request before the second memory unit returns the first data to the processing unit, not performing the chained data prefetch operation.
For example, the data processing method provided by an embodiment of the present disclosure further includes: and responding to the processing unit initiating the second storage address request after the preset time threshold value is exceeded after the second storage unit returns the first data to the processing unit, and not executing the chained data prefetching operation.
For example, in a data processing method provided by an embodiment of the present disclosure, in response to the first storage address request initiated by the processing unit, reading the first data stored in the first storage address of the first storage unit and returning the first data to the second storage unit, the method includes: responding to the first storage address request, initiating a first access request to the first storage unit, and reading the first data stored in the first storage address of the first storage unit; and storing the returned first data in the second storage unit.
For example, the data processing method provided in an embodiment of the present disclosure further includes: returning the read first data to the processing unit; and responding to the second storage address request initiated by the processing unit, reading second data stored in a second storage address of the first storage unit, and returning the second data to the second storage unit.
For example, in a data processing method provided by an embodiment of the present disclosure, in response to the second storage address request initiated by the processing unit, reading the second data stored in the second storage address of the first storage unit and returning the second data to the second storage unit, the method includes: storing the second storage address in the second storage unit; responding to the second storage address request, initiating a second access request to the first storage unit, and reading the second data stored in the second storage address of the first storage unit; and storing the returned second data in the second storage unit.
For example, in a data processing method provided by an embodiment of the present disclosure, determining whether to perform the chained data prefetch operation based on the first data and the second memory address request includes: determining whether a first virtual address matching the second storage address is included in the first data; in response to the first data including the first virtual address matching the second memory address, performing the chained data prefetch operation; and in response to not including the first virtual address in the first data that matches the second storage address, not performing the chained data prefetch operation.
For example, in a data processing method provided by an embodiment of the present disclosure, determining whether the first virtual address matching the second storage address is included in the first data includes: and judging whether the page offset of the first virtual address is consistent with the page offset of the second storage address or not so as to determine whether the first virtual address is matched with the second storage address or not.
For example, the data processing method provided by an embodiment of the present disclosure further includes: establishing a mapping relationship between the second storage address and the first virtual address in response to performing the chained data prefetch operation; determining whether a second virtual address is included in the second data; and responding to the second data comprising the second virtual address, obtaining a physical address corresponding to the second virtual address according to the mapping relation, reading the pre-fetching data stored in the physical address of the first storage unit, and returning the pre-fetching data to the second storage unit.
For example, the data processing method provided by an embodiment of the present disclosure further includes: in response to a third memory address request initiated by the processing unit, comparing whether the physical address is the same as a third memory address included in the third memory address request, and storing third data corresponding to the third memory address request in a third memory address of the first memory unit; and returning the prefetched data in the second memory location to the processing unit as the third data in response to the physical address being the same as the third memory address.
For example, the data processing method provided in an embodiment of the present disclosure further includes: in response to the physical address being the same as the third storage address, continuing to perform the chained data prefetch operation based on the third data and the mapping relationship.
For example, the data processing method provided in an embodiment of the present disclosure further includes: and in response to the physical address being different from the third storage address, reading the third data stored in the third storage address of the first storage unit and returning the third data to the second storage unit.
At least one embodiment of the present disclosure also provides a data processing apparatus including a data acquisition unit and a prefetch control unit; the data acquisition unit is configured to respond to a first storage address request initiated by the processing unit, read first data stored in a first storage address of the first storage unit and return the first data to the second storage unit, wherein the first storage address request comprises the first storage address; the prefetch control unit is configured to determine whether to perform a chained data prefetch operation based on the first data and a second memory address request in response to the processing unit initiating the second memory address request within a preset time threshold after the second memory unit returns the first data to the processing unit, the second memory address request including a second memory address.
For example, an embodiment of the present disclosure provides the data processing apparatus, which further includes a timing unit, where the timing unit is configured to acquire a time when the processing unit initiates the second storage address request.
For example, an embodiment of the present disclosure provides the data processing apparatus, which further includes an address comparison unit configured to determine whether the first data includes a first virtual address matching the second storage address.
For example, an embodiment of the present disclosure provides a data processing apparatus, which further includes an address generation unit, where the address generation unit is configured to establish a mapping relationship between the second storage address and the first virtual address, determine whether second data stored in the second storage address includes a second virtual address, and obtain a physical address corresponding to the second virtual address according to the mapping relationship.
At least one embodiment of the present disclosure also provides an electronic device comprising a processor, memory, and one or more computer program modules; the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for performing the data processing method of any embodiment of the present disclosure.
At least one embodiment of the present disclosure also provides a storage medium that non-transitory stores computer-readable instructions that when executed by a computer can perform a data processing method according to any one of the embodiments of the present disclosure.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
Fig. 1 is a schematic flow chart of a data processing method according to some embodiments of the present disclosure;
fig. 2 is a schematic diagram of a signal connection relationship among a processing unit, a first storage unit and a second storage unit according to some embodiments of the disclosure;
fig. 3 is a schematic flowchart of step S10 in a data processing method according to some embodiments of the present disclosure;
FIG. 4 is a schematic flow chart diagram of another data processing method provided by some embodiments of the present disclosure;
fig. 5 is a schematic flowchart of step S130 in a data processing method according to some embodiments of the present disclosure;
fig. 6 is a schematic flowchart of step S20 in a data processing method according to some embodiments of the present disclosure;
FIGS. 7A and 7B are schematic diagrams of a chained data structure provided by some embodiments of the present disclosure;
fig. 8 is a schematic flow chart of still another data processing method according to some embodiments of the present disclosure;
fig. 9A is a schematic block diagram of a data processing apparatus provided in some embodiments of the present disclosure;
fig. 9B is a schematic block diagram of another data processing apparatus provided in some embodiments of the present disclosure;
fig. 10 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure;
fig. 11 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure; and
fig. 12 is a schematic diagram of a storage medium according to some embodiments of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
Currently, when prefetching data needed by a processor, it is often necessary to identify the read mode of the data. For example, according to the recognized data reading mode, the memory address of the pre-fetch data is determined according to the step size of the interval between data to read the data needed by the processor in advance, or the continuous pre-fetch operation is performed according to the data stream. However, with the chained data structure, since the storage addresses of the data in the chained data structure are relatively dispersed, it is difficult to implement the prefetch operation only according to the read mode of the chained data structure. In addition, since the data stored in the main memory may change at any time, the prefetch operation is difficult to achieve real-time update of the prefetched data, and thus it is also difficult to ensure the accuracy and reliability of the prefetched data obtained.
At least one embodiment of the present disclosure provides a data processing method and apparatus, an electronic device, and a storage medium. The data processing method comprises the following steps: responding to a first storage address request initiated by a processing unit, reading first data stored in a first storage address of a first storage unit, and returning the first data to a second storage unit, wherein the first storage address request comprises the first storage address; and in response to the processing unit initiating a second memory address request within a preset time threshold after the second memory unit returns the first data to the processing unit, determining whether to perform a chained data prefetch operation based on the first data and the second memory address request, the second memory address request including a second memory address.
According to the data processing method provided by the embodiment of the disclosure, before the step of judging whether to execute the chained data prefetching operation based on the first data and the second storage address request according to the time of the processing unit initiating the second storage address request, whether to execute the judging process is determined, so that unnecessary operation processes are reduced, the cost of data processing is reduced, the processing efficiency for the chained data structure can be improved, and the prefetching method of the chained data is optimized.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.
Fig. 1 is a schematic flow chart of a data processing method according to some embodiments of the present disclosure. As shown in fig. 1, the data processing method includes the following operations.
Step S10: and in response to a first storage address request initiated by the processing unit, reading first data stored in a first storage address of the first storage unit and returning the first data to the second storage unit.
Step S20: in response to the processing unit initiating a second memory address request within a preset time threshold after the second memory unit returns the first data to the processing unit, determining whether to perform a chained data prefetch operation based on the first data and the second memory address request.
For step S10, for example, the first memory address request includes a first memory address. For example, the processing unit initiates a first storage address request to the second storage unit, so that the second storage unit reads the first data stored in the first storage address of the first storage unit and returns the read first data to the processing unit in a subsequent step, thereby implementing a response to the first storage address request initiated by the processing unit.
For step S20, for example, the second memory address request includes the second memory address. For example, according to the sequence between the time when the second storage unit returns the read first data to the processing unit and the time when the processing unit initiates the second storage address request, it is determined whether a determination process for determining whether to execute the chained data prefetching operation based on the first data and the second storage address request needs to be executed, that is, according to the time when the processing unit initiates the second storage address request, it is possible to implement a preliminary determination as to whether the second data needing to be read in the second storage address request and the first data belong to the same chained data structure, so as to determine whether to execute the chained data prefetching operation based on the first data and the second storage address request.
Therefore, the data processing method provided by the embodiment of the disclosure can judge in advance whether a judgment process that a chained data prefetching operation needs to be executed based on the first data and the second storage address request is necessary according to the time when the second storage unit returns the read first data to the processing unit and the time when the processing unit initiates the second storage address request, thereby reducing unnecessary operation flows, reducing the cost of data processing, and also can improve the processing efficiency for a chained data structure and optimize the prefetching method of chained data.
For example, taking the structure shown in fig. 2 as an example, the second storage unit 220 reads the first data from the first storage unit 230 after receiving the first storage address request sent by the processing unit 210, and returns the first data to the processing unit 210 after acquiring the first data, so as to implement a response to the first storage address request. Under the condition that the chained data prefetching operation is determined to be executed, the chained data prefetching operation can acquire the subsequent node data belonging to the same chained data structure as the first data from the first storage unit 230 to the second storage unit 220 in advance, so that in the subsequent process, when the processing unit 210 requests to acquire the subsequent node data, the second storage unit 220 can return the pre-acquired data to the processing unit 210, the response time to the first storage address request sent by the processing unit 210 is reduced, and the processing efficiency for the chained data structure is improved.
For example, the first storage unit 230 may be a memory unit, and the second storage unit 220 may be a cache unit. Because the time for reading data from the memory unit is relatively long, and the time for reading data from the cache unit is relatively short, under the condition that the chained data prefetching operation is determined to be executed, the subsequent node data belonging to the same chained data structure as the first data can be acquired from the memory unit to the cache unit in advance through the chained data prefetching operation, so that the response time of the cache unit when the processing unit requests to acquire the subsequent node data in the subsequent process is reduced, and the processing efficiency for the chained data structure is improved.
In some embodiments of the present disclosure, the data processing method further comprises: in response to the processing unit initiating a second memory address request before the second memory unit returns the first data to the processing unit, the chained data prefetch operation is not performed.
For example, according to the sequence between the time when the second storage unit returns the read first data to the processing unit and the time when the processing unit initiates the second storage address request, if the processing unit has initiated the second storage address request before the second storage unit returns the first data to the processing unit, it may be determined that the data requested to be acquired in the second storage address request and the first data do not belong to the same chained data structure, and thus it may be determined that the chained data prefetch operation does not need to be performed based on the first data and the second storage address request, so that unnecessary operation steps may be reduced or avoided, a data processing flow may be optimized, and costs may be reduced.
In some embodiments of the present disclosure, the data processing method further comprises: and responding to the processing unit initiating a second storage address request after the second storage unit returns the first data to the processing unit and exceeding a preset time threshold, and not executing the chained data prefetching operation.
For example, if the processing unit does not initiate a second storage address request within a preset time threshold after the second storage unit returns the first data to the processing unit, it may be determined that the data requested to be acquired in the second storage address request and the first data do not belong to the same chained data structure, and thus it may be determined that the chained data prefetch operation does not need to be performed based on the first data and the second storage address request, and thus a flow of determining whether the chained data prefetch operation is performed may be further optimized, unnecessary operation steps may be reduced or avoided, and costs may be reduced.
Fig. 3 is a schematic flowchart of step S10 in a data processing method according to some embodiments of the present disclosure.
For example, as shown in fig. 3, the step S10 may include steps S101 to S102.
Step S101: and responding to the first storage address request, initiating a first access request to the first storage unit, and reading the first data stored in the first storage address of the first storage unit.
Step S102: and storing the returned first data in the second storage unit.
For the above steps S101 to S102, after receiving the first storage address request initiated by the processing unit, the second storage unit sends a first access request to the first storage unit to request to acquire the first data stored in the first storage address, and stores the first data in the second storage unit after reading the first data from the first storage unit, so that in a case where it is required to determine whether to execute the chained data prefetch operation based on the first data and the second storage address request, the required first data can be directly acquired from the second storage unit, thereby improving the execution efficiency for the chained data prefetch operation.
Fig. 4 is a schematic flow chart of another data processing method according to some embodiments of the present disclosure. It should be noted that steps S110 and S140 shown in fig. 4 are substantially the same as or similar to steps S10 and S20 shown in fig. 1, respectively, and repeated descriptions are omitted.
For example, as shown in fig. 4, the data processing method may include steps S110 to S140.
Step S110: and in response to a first storage address request initiated by the processing unit, reading first data stored in a first storage address of the first storage unit and returning the first data to the second storage unit.
For example, for step S110, the first memory address request includes a first memory address.
Step S120: and returning the read first data to the processing unit.
Step S130: and in response to a second storage address request initiated by the processing unit, reading second data stored in a second storage address of the first storage unit and returning the second data to the second storage unit.
Step S140: in response to the processing unit initiating a second memory address request within a preset time threshold after the second memory unit returns the first data to the processing unit, determining whether to perform a chained data prefetch operation based on the first data and the second memory address request.
For example, for step S140, the second memory address request includes a second memory address.
For example, the above steps S130 and S140 may be performed simultaneously. Thus, it may be determined whether to perform a chained data prefetch operation based on the first data and the second memory address request when the second memory unit reads the second data from the first memory unit in response to the second memory address request initiated by the processing unit, if it is determined that the time at which the processing unit initiates the second memory address request is after the second memory unit returns the first data to the processing unit and within a preset time threshold.
Fig. 5 is a schematic flowchart of step S130 in a data processing method according to some embodiments of the present disclosure.
For example, as shown in fig. 5, the step S130 may include the following operations.
Step S131: the second memory address is stored in the second memory cell.
Step S132: and responding to the second storage address request, initiating a second access request to the first storage unit, and reading second data stored in the second storage address of the first storage unit.
Step S133: and storing the returned second data in the second storage unit.
With regard to step S131 described above, after receiving the second storage address request initiated by the processing unit, the second storage unit stores the second storage address in the second storage address request in the second storage unit, so that in a case where it needs to be determined whether the chained data prefetch operation needs to be executed based on the first data and the second storage address request, a determination may be made in the second storage unit whether the chained data prefetch operation needs to be executed based on the first data and the second storage address stored in the second storage unit. In the case where it is determined that a chained data prefetch operation needs to be requested to be performed based on the first data and the second memory address, a correspondence between the first data and the second memory address may be determined in the second memory unit to determine chained data that needs to be prefetched.
With regard to the above steps S132 and S133, after the second storage unit issues the second access request to the first storage unit to request to acquire the second data stored in the second storage address and reads the second data, the second data is stored in the second storage unit, so that in a case where it is subsequently determined that the chained data prefetch operation needs to be performed based on the first data and the second storage address request, the physical address of the chained data that needs to be prefetched may be determined in the second storage unit based on the second data stored in the second storage unit, thereby implementing the prefetch operation on the chained data.
The following embodiment of the present disclosure describes a specific process of determining whether to execute the chained data prefetch operation based on the first data and the second storage address request in step S20, taking as an example that the processing unit initiates the second storage address request within the preset time threshold after the second storage unit returns the first data to the processing unit in step S20.
Fig. 6 is a schematic flowchart of step S20 in a data processing method according to some embodiments of the present disclosure.
For example, as shown in fig. 6, the above step S20 may include the following steps S210 to S230.
Step S210: it is determined whether a first virtual address matching a second storage address is included in the first data.
Step S220: in response to the first data including a first virtual address matching the second memory address, a chained data prefetch operation is performed.
Step S230: in response to the first data not including the first virtual address matching the second memory address, a chained data prefetch operation is not performed.
For example, in the case where the first data and the second data belong to the same chain data structure, taking the chain data structure including the first data and the second data shown in fig. 7A and 7B as an example, the first data includes a first virtual address pointing to the second data, and the first virtual address includes a virtual page address and an intra-page offset amount. When the chained data structure including the first data and the second data is loaded into the first memory location, the first data is stored in a first memory address of the first memory location, and the second data is stored in a second memory address of the first memory location. For example, the second memory address includes a physical page address and an intra-page offset, and the intra-page offset of the second memory address is the same as the intra-page offset of the first virtual address. Therefore, the first virtual address and the second storage address have a corresponding relationship. Therefore, in step S210, it may be determined whether the first virtual address and the second storage address correspond to each other by determining whether the first data includes the first virtual address matching the second storage address, so as to determine whether the first data and the second data belong to the same chained data structure.
For example, the step S210 may include: and judging whether the in-page offset of the first virtual address is consistent with the in-page offset of the second storage address or not so as to determine whether the first virtual address is matched with the second storage address or not. Thus, by determining that there is a consistent in-page offset between the first virtual address and the second storage address, it can be determined that the first virtual address and the second storage address match each other.
Fig. 8 is a flowchart illustrating another data processing method according to some embodiments of the disclosure. It should be noted that steps S201 to S204 shown in fig. 8 are substantially the same as or similar to steps S110 to S140 shown in fig. 4, respectively, and repeated descriptions are omitted.
As shown in fig. 8, the data processing method further includes the following operations.
Step S205: in response to performing the chained data prefetch operation, a mapping relationship between the second storage address and the first virtual address is established.
Step S206: it is determined whether the second data includes the second virtual address.
Step S207: and responding to the second data comprising the second virtual address, obtaining a physical address corresponding to the second virtual address according to the mapping relation, reading the pre-fetching data stored in the physical address of the first storage unit, and returning the pre-fetching data to the second storage unit.
For example, taking the chained data structure shown in fig. 7A and 7B as an example, in the case that it is determined that the first data and the second data belong to the same chained data structure, step S205 is executed to establish an address mapping relationship between the physical page address of the second storage address and the virtual page address of the first virtual address as a mapping relationship between the second storage address and the first virtual address. In the case that step S206 is executed and it is determined that the second data includes the second virtual address, step S207 may be executed to determine, according to the established address mapping relationship, a physical page address in a physical address corresponding to the second virtual address, and use the intra-page offset in the second virtual address as the intra-page offset in the corresponding physical address, thereby obtaining the physical address.
For example, after determining the physical address, the second memory cell reads the prefetched data stored in the physical address of the first memory cell and returns the prefetched data to the second memory cell so that the prefetched data can be stored in the second memory cell. For example, the prefetched data is also the node data pointed to by the second virtual address in the chain data structure shown in fig. 7A. For example, in the case where the second storage unit includes a cache unit, the prefetch data stored in the cache unit may be maintained in a real-time update state, thereby improving the accuracy and reliability of the obtained prefetch data.
In some embodiments of the present disclosure, as shown in fig. 8, the data processing method further includes the following operations.
Step S208: in response to a third memory address request initiated by the processing unit, a comparison is made as to whether the physical address is the same as a third memory address included in the third memory address request. For example, third data corresponding to the third memory address request is stored in the third memory address of the first memory cell.
Step S209: and in response to the physical address being the same as the third memory address, returning the prefetched data in the second memory location to the processing unit as third data.
With step S208 described above, it is compared whether the physical address and the third memory address completely coincide with each other, for example, whether the physical page address and the intra-page offset of both completely coincide with each other needs to be compared, thereby determining whether the physical address and the third memory address are identical to each other.
With regard to the above step S209, in the case that the physical address and the third storage address are determined to be the same as each other, it may be determined that the pre-fetch data read in advance by the physical address, that is, the node data pointed to by the second virtual address in the chained data structure shown in fig. 7A, is the third data requested to be read by the third storage address. Therefore, the second storage unit returns the pre-fetch data read in advance as third data to the processing unit, time for responding to a third storage address request initiated by the processing unit can be reduced, processing efficiency of the chained data structure is improved, and a processing method of the chained data is optimized.
In some embodiments of the present disclosure, as shown in fig. 8, the data processing method further includes the following operations.
Step S210: and in response to the physical address being the same as the third storage address, continuing to perform the chained data prefetch operation based on the third data and the mapping relationship.
For example, after the second storage unit returns the prefetched data read in advance as the third data to the processing unit, the above-mentioned chained data prefetching operation may be continued based on the third data, so that when a subsequent processor issues a request for subsequent node data in the chained data structure shown in fig. 7A, the response time to the request may be reduced, thereby further improving the processing efficiency for the chained data structure.
In some embodiments of the present disclosure, the data processing method further includes: and in response to the physical address being different from the third storage address, reading third data stored in the third storage address of the first storage unit and returning the third data to the second storage unit.
For example, in the case that the physical address is different from the third storage address, it may be determined that the third data requested to be read by the processor is not the prefetch data, that is, the third data does not belong to the same chained data structure as the first data and the second data. Accordingly, the second memory unit needs to read the required third data from the third memory address of the first memory unit to complete the response to the third memory address request issued by the processor.
It should be noted that, each step in the data processing method provided by the embodiment of the present disclosure is executed starting from the first data, and correspondingly, the second data, the third data, and the like in the foregoing embodiment of the present disclosure may also be used as the first data to execute the foregoing steps in the data processing method provided by the embodiment of the present disclosure, that is, in a case that it is determined that the first data and the second data do not belong to the same chained data structure, it may be continuously determined whether the second data and the third data belong to the same chained data structure, and then it may be determined whether a chained data prefetch operation needs to be executed based on the second data and the third data.
It should be noted that, in the embodiments of the present disclosure, the flows of the data processing methods provided by the above-mentioned embodiments of the present disclosure may include more or less operations, and these operations may be executed sequentially or in parallel. Although the flow of the data processing method described above includes a plurality of operations occurring in a certain order, it should be clearly understood that the order of the plurality of operations is not limited. The data processing method described above may be executed once or a plurality of times according to a predetermined condition.
At least one embodiment of the present disclosure also provides a data processing apparatus. Fig. 9A is a schematic block diagram of a data processing apparatus according to some embodiments of the present disclosure. For example, as shown in fig. 9A, in some examples, data processing apparatus 200 includes a data fetch unit 210 and a prefetch control unit 220.
The data obtaining unit 210 is configured to read first data stored in a first storage address of the first storage unit and return the first data to the second storage unit in response to a first storage address request initiated by the processing unit. For example, the first memory address request includes a first memory address. For example, the data acquisition unit 210 may execute step S10 in the data processing method shown in fig. 1.
The prefetch control unit 220 is configured to determine whether to perform a chained data prefetch operation based on the first data and the second memory address request in response to the processing unit initiating the second memory address request within a preset time threshold after the second memory unit returns the first data to the processing unit. For example, the second memory address request includes a second memory address. For example, the prefetch control unit 220 may perform step S20 in the data processing method shown in fig. 1.
Fig. 9B is a schematic block diagram of another data processing apparatus provided in some embodiments of the present disclosure.
For example, as shown in fig. 9B, the data processing apparatus 200 further includes a timing unit 230 on the basis of the example shown in fig. 9A. The timing unit 230 is configured to obtain the time when the processing unit initiates the second memory address request. Thus, step S20 in the data processing method shown in fig. 1 is performed according to the time provided by the timing unit 230 when the processing unit initiates the second memory address request.
For example, as shown in fig. 9B, the data processing apparatus 200 further includes an address comparison unit 240 on the basis of the example shown in fig. 9A. The address comparison unit 240 is configured to determine whether a first virtual address matching a second storage address is included in the first data. For example, the address comparison unit 240 may perform step S201 in the data processing method shown in fig. 6.
For example, as shown in fig. 9B, on the basis of the example shown in fig. 9A, the data processing apparatus 200 further includes an address generation unit 250. For example, the address generating unit 250 is configured to establish a mapping relationship between the second storage address and the first virtual address, determine whether the second data stored in the second storage address includes the second virtual address, and obtain a physical address corresponding to the second virtual address according to the mapping relationship. For example, the address generation unit 250 may perform the respective operations in steps S205 to S207 in the data processing method shown in fig. 8.
For example, the data fetch unit 210, the prefetch control unit 220, the timing unit 230, the address comparison unit 240, and the address generation unit 250 may be hardware, software, firmware, and any feasible combination thereof. For example, the data obtaining unit 210, the prefetch control unit 220, the timing unit 230, the address comparison unit 240, and the address generation unit 250 may be dedicated or general circuits, chips, devices, or the like, or may be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.
It should be noted that, in the embodiment of the present disclosure, each unit of the data processing apparatus 200 corresponds to each step of the foregoing data processing method, and for a specific function of the data processing apparatus 200, reference may be made to the related description about the data processing method, which is not described herein again. The components and configuration of the data processing apparatus 200 shown in fig. 9A and 9B are exemplary only, and not limiting, and the data processing apparatus 200 may further include other components and configurations as necessary.
For example, the data processing apparatus described above may be implemented in the second storage unit. For example, the second storage unit may be a cache unit in the chip.
At least one embodiment of the present disclosure also provides an electronic device that includes a processor, memory, and one or more computer program modules. One or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for performing the data processing method provided by any of the embodiments of the present disclosure.
Fig. 10 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in fig. 10, the electronic device 300 includes a processor 310 and a memory 320. Memory 320 is used to store non-transitory computer readable instructions (e.g., one or more computer program modules). The processor 310 is configured to execute non-transitory computer readable instructions, which when executed by the processor 310 may perform one or more of the steps of the data processing method described above. The memory 320 and the processor 310 may be interconnected by a bus system and/or other form of connection mechanism (not shown).
For example, the processor 310 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. The processor 310 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 300 to perform desired functions.
For example, memory 320 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, erasable Programmable Read Only Memory (EPROM), portable compact disk read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by processor 310 to implement various functions of electronic device 300. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.
It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description about the data processing method and the data processing apparatus for specific functions and technical effects of the electronic device 300, and details are not described herein again.
Fig. 11 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 400 is, for example, suitable for implementing the data processing method provided by the embodiments of the present disclosure. The electronic device 400 may be a terminal device or the like. It should be noted that the electronic device 400 shown in fig. 11 is only an example, and does not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
As shown in fig. 11, electronic device 400 may include a processing means (e.g., central processing unit, graphics processor, etc.) 410 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM) 420 or a program loaded from a storage device 480 into a Random Access Memory (RAM) 430. In the RAM 430, various programs and data necessary for the operation of the electronic apparatus 400 are also stored. The processing device 410, the ROM 420, and the RAM 430 are connected to each other by a bus 440. An input/output (I/O) interface 450 is also connected to bus 440.
Generally, the following devices may be connected to the I/O interface 450: input devices 460 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 470 including, for example, a Liquid Crystal Display (LCD), speakers, vibrators, or the like; storage 480 including, for example, magnetic tape, hard disk, etc.; and a communication device 490. The communication device 490 may allow the electronic device 400 to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 11 illustrates an electronic device 400 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 400 may alternatively be implemented or provided with more or less means.
For example, according to an embodiment of the present disclosure, the above-described data processing method may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the above-described data processing method. In such embodiments, the computer program may be downloaded and installed from a network through communication device 490, or installed from storage device 480, or installed from ROM 420. When executed by the processing device 410, the computer program may implement the functions defined in the data processing method provided by the embodiments of the present disclosure.
Fig. 12 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. For example, as shown in fig. 12, the storage medium 500 may be a non-transitory computer-readable storage medium, on which one or more computer-readable instructions 501 may be non-temporarily stored on the storage medium 500. For example, the computer readable instructions 501, when executed by a processor, may perform one or more steps in a data processing method according to the above.
For example, the storage medium 500 may be applied to the electronic device described above, and for example, the storage medium 500 may include a memory in the electronic device.
For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), a flash memory, or any combination of the above, as well as other suitable storage media.
For example, the description of the storage medium 500 may refer to the description of the memory in the embodiment of the electronic device, and repeated descriptions are omitted. Specific functions and technical effects of the storage medium 500 can be referred to the above description of the data processing method and the data processing apparatus, and are not described herein again.
The following points need to be explained:
(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.
Claims (18)
1. A method of data processing, comprising:
in response to a first storage address request initiated by a processing unit, reading first data stored in a first storage address of a first storage unit and returning the first data to a second storage unit, wherein the first storage address request comprises the first storage address; and
in response to the processing unit initiating a second memory address request within a preset time threshold after the second memory unit returns the first data to the processing unit, determining whether to perform a chained data prefetch operation based on the first data and the second memory address request, wherein the second memory address request includes a second memory address.
2. The data processing method of claim 1, further comprising:
in response to the processing unit initiating the second memory address request before the second memory unit returns the first data to the processing unit, not performing the chained data prefetch operation.
3. The data processing method of claim 1, further comprising:
and in response to the processing unit initiating the second storage address request after exceeding the preset time threshold after the second storage unit returns the first data to the processing unit, not performing the chained data prefetch operation.
4. The data processing method of any of claims 1-3, wherein reading the first data stored in the first memory address of the first memory unit and returning the first data to the second memory unit in response to the first memory address request initiated by the processing unit comprises:
responding to the first storage address request, initiating a first access request to the first storage unit, and reading the first data stored in the first storage address of the first storage unit; and
storing the returned first data in the second storage unit.
5. The data processing method of any of claims 1-3, further comprising:
returning the read first data to the processing unit; and
and in response to the second storage address request initiated by the processing unit, reading second data stored in a second storage address of the first storage unit and returning the second data to the second storage unit.
6. The data processing method of claim 5, wherein reading the second data stored in the second memory address of the first memory unit and returning the second data to the second memory unit in response to the second memory address request initiated by the processing unit comprises:
storing the second storage address in the second storage unit;
responding to the second storage address request, initiating a second access request to the first storage unit, and reading the second data stored in the second storage address of the first storage unit; and
and storing the returned second data in the second storage unit.
7. The data processing method of claim 5, wherein determining whether to perform the chained data prefetch operation based on the first data and the second memory address request comprises:
determining whether a first virtual address matching the second storage address is included in the first data;
in response to the first data including the first virtual address matching the second storage address, performing the chained data prefetch operation; and
in response to not including the first virtual address in the first data that matches the second storage address, not performing the chained data prefetch operation.
8. The data processing method of claim 7, wherein determining whether the first virtual address matching the second storage address is included in the first data comprises:
and judging whether the page offset of the first virtual address is consistent with the page offset of the second storage address or not so as to determine whether the first virtual address is matched with the second storage address or not.
9. The data processing method of claim 7, further comprising:
establishing a mapping relationship between the second storage address and the first virtual address in response to performing the chained data prefetch operation;
determining whether a second virtual address is included in the second data; and
and responding to the second data including the second virtual address, obtaining a physical address corresponding to the second virtual address according to the mapping relation, reading the pre-fetching data stored in the physical address of the first storage unit, and returning the pre-fetching data to the second storage unit.
10. The data processing method of claim 9, further comprising:
in response to a third memory address request initiated by the processing unit, comparing whether the physical address is the same as a third memory address included in the third memory address request, wherein third data corresponding to the third memory address request is stored in the third memory address of the first memory unit; and
in response to the physical address being the same as the third memory address, returning the prefetched data in the second memory location to the processing unit as the third data.
11. The data processing method of claim 10, further comprising:
in response to the physical address being the same as the third storage address, continuing to perform the chained data prefetch operation based on the third data and the mapping relationship.
12. The data processing method of claim 10, further comprising:
and in response to the physical address being different from the third storage address, reading the third data stored in the third storage address of the first storage unit and returning the third data to the second storage unit.
13. A data processing apparatus comprising:
the data acquisition unit is configured to respond to a first storage address request initiated by the processing unit, read first data stored in a first storage address of the first storage unit and return the first data to the second storage unit, wherein the first storage address request comprises the first storage address;
a prefetch control unit configured to, in response to the processing unit initiating a second memory address request within a preset time threshold after the second memory unit returns the first data to the processing unit, determine whether to perform a chained data prefetch operation based on the first data and the second memory address request, wherein the second memory address request includes a second memory address.
14. The data processing apparatus according to claim 13, further comprising a timing unit,
wherein the timing unit is configured to obtain a time when the processing unit initiates the second memory address request.
15. The data processing apparatus of claim 13, further comprising an address comparison unit,
wherein the address comparison unit is configured to determine whether a first virtual address matching the second storage address is included in the first data.
16. The data processing apparatus of claim 15, further comprising an address generation unit,
the address generation unit is configured to establish a mapping relationship between the second storage address and the first virtual address, determine whether second data stored in the second storage address includes a second virtual address, and obtain a physical address corresponding to the second virtual address according to the mapping relationship.
17. An electronic device, comprising:
a processor;
a memory;
one or more computer program modules stored in the memory and configured to be executed by the processor, the one or more computer program modules comprising instructions for performing the data processing method of any of claims 1-12.
18. A storage medium non-transitory storing computer-readable instructions that, when executed by a computer, can perform the data processing method of any one of claims 1-12.
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