CN112630613A - Method for predicting channel temperature of multi-layer stacked gate-all-around field effect transistor - Google Patents

Method for predicting channel temperature of multi-layer stacked gate-all-around field effect transistor Download PDF

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CN112630613A
CN112630613A CN202011388665.6A CN202011388665A CN112630613A CN 112630613 A CN112630613 A CN 112630613A CN 202011388665 A CN202011388665 A CN 202011388665A CN 112630613 A CN112630613 A CN 112630613A
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刘人华
李小进
孙亚宾
石艳玲
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Abstract

The invention discloses a method for predicting the channel temperature of a multilayer stacked gate-all-around field effect transistor, which comprises the following steps: the method comprises the following steps: acquiring structural parameters and thermal parameters of a multi-layer stacked gate-all-around field effect transistor; step two: building a first type of de-embedding structure based on a finite element simulation tool; step three: extracting the structural thermal resistance of each layer of channel; step four: building a second type of de-embedding structure based on a finite element simulation tool; step five: extracting coupling thermal resistance between channels of each layer; step six: based on a thermal resistance matrix theory and a thermal linear superposition theory, a Newton iterative algorithm is used for predicting the working temperature of each layer of channel of the multi-layer stacked gate-all-around field effect transistor. The temperature prediction method provided by the invention incorporates the actual situation of thermal coupling among channels, and separates the material thermal resistance and the coupling thermal resistance of the multi-layer stacked gate-all-around field effect transistor, thereby accurately predicting the working temperature of each layer of channel.

Description

Method for predicting channel temperature of multi-layer stacked gate-all-around field effect transistor
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a method for predicting the channel temperature of a multi-layer stacked gate-all-around field effect transistor.
Background
As semiconductor process nodes are developed to deep nanometer level, Stacked Gate-All-Around Field-Effect Transistor (GAAFAT) has become the mainstream device of process node of 5nm and below due to its excellent Gate control capability. However, due to the limitations of three-dimensional structures, and the use of low thermal conductivity materials, the heat dissipation capability of the GAAFET device is reduced, and the Self-heating Effect (Self-heating Effect) is exacerbated. The temperature rise can cause the threshold voltage drift of the transistor, the degradation of on-state current and aggravate the reliability of the device, and further affect the working state of the whole circuit, so how to accurately extract the thermal resistance of the GAAFET device and predict the temperature of the device are problems to be solved and perfected urgently.
At present, a common method for thermal resistance extraction and temperature prediction of a GAAFET device is to obtain peak temperature change and total power consumption of the GAAFET device by means of finite element simulation tool simulation, and further calculate a ratio of the peak temperature change and the total power efficiency to obtain the device thermal resistance of the GAAFET device. The method can obtain the average thermal resistance of the device, but neglects the serious thermal coupling (thermal coupling) effect between channels of the stacked GAAFET device and the difference of heat dissipation paths of different channels, and is difficult to accurately describe the temperature of different channels.
Method of the invention
The purpose of the invention is: the method for predicting the channel temperature of the multilayer stacked gate-all-around field effect transistor is provided for accurately describing the temperature of different channels, can accurately separate the thermal resistance of a thermal coupling action part, and has certain applicability in a multi-gate device.
The specific technical scheme for realizing the purpose of the invention is as follows:
a method of channel temperature prediction for a multi-layer stacked gate-all-around field effect transistor, comprising:
the method comprises the following steps: acquiring structural parameters and thermal parameters of a gate-all-around field effect transistor stacked by multiple layers of channels, wherein the structural parameters and the thermal parameters comprise the geometric size of each region of the transistor, the number of stacked channels, the thermal conductivity of materials of each region, the boundary thermal resistance among different materials and the thermal boundary conditions of the transistor;
step two: based on a finite element simulation tool, a first class de-embedding structure Si-Ch for extracting thermal resistance of a ring gate field effect transistor structure is establishedaA is the mark number of the channel layer, the value of a is a positive integer and ranges from 1 to m, m is the number of the stacked channels, and the first-class de-embedding structure Si-ChaThe material of the channel of the a-th layer is the same as that of the ring gate field effect transistor channel stacked by the multiple layers of channels, and the materials of the channels of the other layers are insulators;
step three: extracting a first class of de-embedding structure Si-ch based on a finite element simulation toolaStructural thermal resistance R of middle a layer channelthaa；
Step four: constructing a second class de-embedding structure Si-Ch for extracting thermal resistance of ring-gate field effect transistor structureabA and b are the labels of the channel layers, the values of a and b are positive integers, the value range of a is 1-m-1, the value range of b is 2-m, m is the number of stacked channels, a is less than b, and the second type de-embedding structure Si-ChabThe material of the channel of the middle layer a and the layer b is the same as that of the ring grid field effect transistor channel stacked by the multiple layers of channels, and the materials of the channels of the other layers are insulators;
step five: calculating the coupling thermal resistance R between the channels of the a-th layer and the b-th layer according to the thermal linear superposition theory based on a finite element simulation toolcoabAnd RcobaWherein R iscoabCoupling thermal resistance R of the temperature rise of the channel of the layer a caused by the operation of the channel of the layer bcobaCoupling thermal resistance for the temperature rise of the channel of the layer b caused by the working of the channel of the layer a;
step six: structural thermal resistance R extracted from step threethaaAnd the coupling thermal resistance R extracted in the step fivecoabAnd RcobaAnd based on a thermal resistance matrix theory and a thermal linear superposition theory, predicting the working temperature of each layer of channel of the gate-all-around field effect transistor by using a Newton iterative algorithm.
The invention provides a multi-layer stacked ring gate field effect transistorMethod for predicting transistor channel temperature, structure thermal resistance R of a channel of the a-th layerthaaBy de-embedding structures of the first kind Si-chaThe peak temperature of the channel of the (a) th layer and the current flowing through the channel of the layer obtain:
Rthaa＝(Taa-a-Tamb)/(Ia-a×VDS)
wherein, Taa-aFor de-embedding structures Si-ch of the first kind obtained by finite element simulation toolsaPeak operating temperature, T, of the channel of the (a) th layerambFor reference to the temperature of the external environment, Ia-aIs the current flowing in the channel of the a-th layer, VDSIs the drain input voltage of the transistor.
The invention provides a method for predicting the channel temperature of a multilayer stacked gate-all-around field effect transistor, which is characterized in that the coupling thermal resistance R between the channels of the a-th layer and the b-th layercoabAnd RcobaBy de-embedding structures Si-ch of the second kindabThe peak temperature and the flowing current of the channel of the (a) th layer and the peak temperature and the flowing current of the channel of the (b) th layer are obtained as follows:
Rcoab＝(Taa-ab-Rthaa×Ia-ab×VDS-Tamb)/(Ib-ab×VDS)
Rcoba＝(Tbb-ab-Rthbb×Ib-ab×VDS-Tamb)/(Ia-ab×VDS)
wherein, Taa-abAnd Tbb-abRespectively, of a second type of de-embedding structure Si-ch obtained by means of finite element simulation toolsabPeak operating temperature, T, of the channel of the middle a-layer and the channel of the b-layerambFor reference to the temperature of the external environment, Ia-abIs the current flowing in the channel of the a-th layer, Ib-abIs the current flowing in the channel of the b-th layer, VDSIs the drain input voltage of the transistor.
The invention provides a method for predicting the channel temperature of a multilayer stacked gate-all-around field effect transistor, wherein the thermal resistance matrix theory and the thermal linear superposition theory are calculated by the following formula:
Figure BDA0002811647920000031
and T is the working temperature of the mth layer channel in the m layers of stacked gate-all-around field effect transistors, and P is the input power of the mth layer channel.
The invention provides a method for predicting the channel temperature of a multilayer stacked gate-all-around field effect transistor, wherein the Newton iteration algorithm flow comprises the following steps of firstly, inputting the initial temperature T of each channel layerchmAnd input power PmM is the number of stacked channels, the initial temperature and the external environment temperature TambEqual; secondly, calculating the structural thermal resistance and the coupling thermal resistance of the multi-layer stacked ring gate field effect transistor at the initial temperature, and calculating the temperature T of the channel at the mth layer according to the thermal resistance matrix theory and the thermal linear superposition theorychm1(ii) a Finally, T is judgedchm1And Tchm0Whether the difference values of (a) are all less than the set threshold value TthIf the difference is less than TthOutputting the final temperature T of each layer of channelchmAnd T ischm＝Tchm1If the difference is greater than TthThen respectively combine Tchm1Is given to the initial temperature Tchm0Continuing the above loop calculation until Tchm1And Tchm0Are all less than a threshold value TthOutputting the final temperature T of each channel layerchmAnd T ischm＝Tchm1。
The temperature prediction method provided by the invention incorporates the actual situation of thermal coupling among channels, and separates the material thermal resistance and the coupling thermal resistance of the multi-layer stacked gate-all-around field effect transistor, thereby accurately predicting the working temperature of each layer of channel.
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FIG. 1 is a schematic diagram of a three-layer stacked gate-all-around field effect transistor structure according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken at A-A in FIG. 1;
FIG. 3 shows a first type of de-embedding structure Si-ch according to an embodiment of the present invention1A schematic cross-sectional view;
FIG. 4 shows the present inventionEXAMPLES DeEmbedded Structure of the first kind Si-ch2A schematic cross-sectional view;
FIG. 5 shows a first type of de-embedding structure Si-ch according to an embodiment of the present invention3A schematic cross-sectional view;
FIG. 6 is a diagram illustrating the relationship between the structural thermal resistance and the operating temperature in the embodiment of the present invention;
FIG. 7 shows a second type of de-embedding structure Si-ch according to an embodiment of the present invention12A schematic cross-sectional view;
FIG. 8 shows a second type of de-embedding structure Si-ch according to an embodiment of the present invention23A schematic cross-sectional view;
FIG. 9 shows a second type of de-embedding structure Si-ch according to an embodiment of the present invention13A schematic cross-sectional view;
FIG. 10 is a diagram illustrating the relationship between the coupling thermal resistance and the operating temperature according to an embodiment of the present invention;
FIG. 11 is a flow chart of a Newton's iterative algorithm in accordance with the present invention;
fig. 12 is a schematic diagram of a relationship between a TCAD simulation result of the peak operating temperature of each layer of channel and a newton iteration calculation result of a temperature model in the embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and examples.
Examples
The present embodiment takes the case of vertically stacking three layers of nanosheet channels.
The invention provides a method for predicting the channel temperature of a multi-layer stacked gate-all-around field effect transistor, which comprises the following specific implementation steps of:
the method comprises the following steps: and acquiring structural parameters and thermal parameters of the multi-layer stacked gate-all-around field effect transistor. The basic structural parameters and the used thermal parameters of the multi-layer stacked gate-all-around field effect transistor are shown in the table 1 and the table 2, and the schematic diagram of the multi-layer stacked gate-all-around field effect transistor is shown in the attached figures 1 and 2;
table 1: basic structure parameter of multi-layer stacked gate-all-around field effect transistor
Parameter(s) Value of
Gate length LG 12nm
Nanosheet channel width WNS 40nm
Nanosheet channel thickness TNS 5nm
Side wall length LSP 5nm
Nanosheet spacing PITCH 10nm
Source/drain width LSD 13nm
Equivalent oxide thickness EOT 1nm
Number n of vertically stacked channels 3
Table 2: multilayer stacked gate-all-around field effect transistor thermal parameters
Figure BDA0002811647920000041
Figure BDA0002811647920000051
Step two: based on finite element simulation tool, building a first class of de-embedding structure Si-ch1、Si-ch2、Si-ch3As shown in fig. 3 to 5. In contrast to the multi-stacked gate-all-around field effect transistor, the first type of de-embedding structure replaces the material of some two channels in the multi-stacked gate-all-around field effect transistor with an insulator in order to eliminate the joule heating effect in the replaced channels.
Step three: based on finite element simulation tool, respectively extracting first class de-embedding structure Si-ch1、Si-ch2、Si-ch3Structural thermal resistance R of middle 1, 2 and 3 layer channelth11、Rth22、Rth33；
Based on the simulation result of the finite element tool, keeping the grid voltage unchanged, and respectively extracting the first class of de-embedding structures Si-ch under different drain VDS voltages1、Si-ch2、Si-ch3Current I of middle 1, 2, 3 layer channel1-1、I2-2、I3-3And operating temperature T11-1、T22-2、T33-3Calculating the structural thermal resistance R according to the following formula by taking the ambient temperature 300K as a reference valueth11、Rth22、Rth33The relationship with the operating temperature is such that,
Rth11＝(T11-1-300K)/(I1-1×VDS)
Rth22＝(T22-2-300K)/(I2-1×VDS)
Rth33＝(T33-3-300K)/(I3-1×VDS)
the relationship between the structural thermal resistance and the operating temperature is shown in fig. 6.
Step four: based on finite element simulation tool, building a second type de-embedding toolInto the structure Si-ch12、Si-ch23、Si-ch13As shown in fig. 7 to 9. Compared with the multi-layer stacked gate-all-around field effect transistor, the second kind of de-embedding structure replaces the material of a certain channel in the multi-layer stacked gate-all-around field effect transistor with an insulator, and aims to eliminate the joule heat effect in the replaced channel.
Step five: de-embedding structures Si-ch according to the second class based on finite element simulation tools12、Si-ch23、Si-ch13Respectively extracting the coupling thermal resistance R between the channels of each layerco12、Rco21、Rco23、Rco32、Rco13、Rco31；
Based on the simulation result of the finite element tool, the grid voltage is kept unchanged and different drain electrodes VDSExtracting the second kind of de-embedding structure Si-ch under voltage12Current I of middle 1 st layer and 2 nd layer channel1-12、I2-12And operating temperature T11-12、T22-12，Si-ch23Current I of middle 2 nd and 3 rd layer channels2-23、I3-23And operating temperature T22-23、T33-23And Si-ch13Current I of middle 1 st layer and 3 rd layer channel1-13、I3-13And operating temperature T11-13、T33-13Calculating the coupling thermal resistance R according to the following formula by taking the ambient temperature 300K as a reference valueco12、Rco21、Rco23、Rco32、Rco13、Rco31The relationship with the operating temperature is such that,
Rco12＝(T11-12-Rth11×I1-12×VDS-300K)/(I2-12×VDS)
Rco21＝(T22-12-Rth22×I2-12×VDS-300K)/(I1-12×VDS)
Rco23＝(T22-23-Rth22×I2-23×VDS-300K)/(I3-23×VDS)
Rco32＝(T33-23-Rth33×I3-23×VDS-300K)/(I2-23×VDS)
Rco13＝(T11-13-Rth11×I1-13×VDS-300K)/(I3-13×VDS)
Rco31＝(T33-13-Rth33×I3-13×VDS-300K)/(I1-13×VDS)
the coupling resistance versus operating temperature is shown in fig. 10.
Step six: based on the structural thermal resistance and the coupling thermal resistance obtained in the steps and based on a thermal resistance matrix theory and a thermal linear superposition theory, the temperature of each layer of channel of the gate-all-around field effect transistor can be calculated by the following formula:
Figure BDA0002811647920000061
because the structural thermal resistance and the coupling thermal resistance of the multi-layer stacked ring gate field effect transistor are closely related to the working temperature, in order to accurately predict the temperature of each layer of channel, the invention adopts a Newton iteration method to calculate the final peak temperature of each channel under specific input power.
The calculation method of Newton iteration is shown in FIG. 11, and first, the initial temperature T of each channel layer is inputch10、Tch20、Tch30And is equal to the external environment temperature of 300K; secondly, calculating the structural thermal resistance and the coupling thermal resistance of the multi-layer stacked ring gate field effect transistor at the initial temperature, and respectively calculating the input power P of the channels at the 1 st layer, the 2 nd layer and the 3 rd layer as the heat resistance matrix theory and the thermal linear superposition theory1、P2、P3Temperature T ofch11、Tch21、Tch31And determining Tch11And Tch10、Tch21And Tch20And Tch31And Tch30Whether the difference values of (a) are all less than the set threshold value TthThreshold value T set in the present embodimentth0.1K, and if the difference is less than 0.1K, outputting the final temperature T of each layer of channelch1、Tch2、Tch3And let Tch1＝Tch11、Tch2＝Tch21、Tch3＝Tch31(ii) a If the difference is greater than TthThen respectively combine Tch11、Tch21、Tch31Is given as Tch10、Tch20、Tch30Continuing the above loop calculation until Tch11And Tch10、Tch21And Tch20And Tch31And Tch30Are all less than the threshold value of 0.1K, and the final temperature T of each channel layer is outputch1、Tch2、Tch3And let Tch1＝Tch11、Tch2＝Tch21、Tch3＝Tch31。
The relationship between the TCAD simulation value of the final peak temperature of each layer channel of the stacked gate-all-around field effect transistor and the temperature model newton iteration calculation result is shown in fig. 12.

Claims (5)

1. A method for predicting channel temperature of a multi-layer stacked gate-all-around field effect transistor (MOSFET), comprising:
the method comprises the following steps: acquiring structural parameters and thermal parameters of a gate-all-around field effect transistor stacked by multiple layers of channels, wherein the structural parameters and the thermal parameters comprise the geometric size of each region of the transistor, the number of stacked channels, the thermal conductivity of materials of each region, the boundary thermal resistance among different materials and the thermal boundary conditions of the transistor;
step two: based on a finite element simulation tool, a first class de-embedding structure Si-Ch for extracting thermal resistance of a ring gate field effect transistor structure is establishedaA is the mark number of the channel layer, the value of a is a positive integer and ranges from 1 to m, m is the number of the stacked channels, and the first-class de-embedding structure Si-ChaThe material of the channel of the a-th layer is the same as that of the ring gate field effect transistor channel stacked by the multiple layers of channels, and the materials of the channels of the other layers are insulators;
step three: extracting a first class of de-embedding structure Si-ch based on a finite element simulation toolaStructural thermal resistance R of middle a layer channelthaa；
Step four: constructing a second class de-embedding structure Si-Ch for extracting thermal resistance of ring-gate field effect transistor structureabA and b are the labels of the channel layers, the values of a and b are positive integers, the value range of a is 1-m-1, the value range of b is 2-m, m is the number of stacked channels, a is less than b, and the second type de-embedding structure Si-ChabThe material of the channel of the middle layer a and the layer b is the same as that of the ring grid field effect transistor channel stacked by the multiple layers of channels, and the materials of the channels of the other layers are insulators;
step five: extracting the coupling thermal resistance R between the channels of the a-th layer and the b-th layer according to the thermal linear superposition theory based on a finite element simulation toolcoabAnd RcobaWherein R iscoabCoupling thermal resistance R of the temperature rise of the channel of the layer a caused by the operation of the channel of the layer bcobaCoupling thermal resistance for the temperature rise of the channel of the layer b caused by the working of the channel of the layer a;
step six: structural thermal resistance R extracted from step threethaaAnd the coupling thermal resistance R extracted in the step fivecoabAnd RcobaAnd based on a thermal resistance matrix theory and a thermal linear superposition theory, predicting the working temperature of each layer of channel of the gate-all-around field effect transistor by using a Newton iterative algorithm.
2. The method of claim 1, wherein the structural thermal resistance R of the channel of the a-th layer is higher than the structural thermal resistance R of the channel of the a-th layerthaaBy de-embedding structures of the first kind Si-chaThe peak temperature of the channel of the (a) th layer and the current flowing through the channel of the layer obtain:
Rthaa＝(Taa-a-Tamb)/(Ia-a×VDS)
wherein, Taa-aFor de-embedding structures Si-ch of the first kind obtained by finite element simulation toolsaPeak operating temperature, T, of the channel of the (a) th layerambFor reference to the temperature of the external environment, Ia-aIs the current flowing in the channel of the a-th layer, VDSIs the drain input voltage of the transistor.
3. The method of claim 1, wherein a thermal coupling resistance R between the channels of the a-th layer and the b-th layer is the same as the thermal coupling resistance RcoabAnd RcobaBy de-embedding structures Si-ch of the second kindabThe peak temperature and the flowing current of the channel of the (a) th layer and the peak temperature and the flowing current of the channel of the (b) th layer are obtained as follows:
Rcoab＝(Taa-ab-Rthaa×Ia-ab×VDS-Tamb)/(Ib-ab×VDS)
Rcoba＝(Tbb-ab-Rthbb×Ib-ab×VDS-Tamb)/(Ia-ab×VDS)
wherein, Taa-abAnd Tbb-abRespectively, of a second type of de-embedding structure Si-ch obtained by means of finite element simulation toolsabPeak operating temperature, T, of the channel of the middle a-layer and the channel of the b-layerambFor reference to the temperature of the external environment, Ia-abIs the current flowing in the channel of the a-th layer, Ib-abIs the current flowing in the channel of the b-th layer, VDSIs the drain input voltage of the transistor.
4. The method of claim 1, wherein the thermal resistance matrix theory and the thermal linear superposition theory are calculated as follows:
Figure FDA0002811647910000021
wherein, TmOperating temperature, P, of the mth layer channel in a gate-all-around field effect transistor stacked for m layersmIs the input power of the mth layer channel.
5. The method of claim 1, wherein the method comprises predicting the channel temperature of the gate-all-around MOSFETThe Newton iterative algorithm flow is that firstly, the initial temperature T of each channel layer is inputchmAnd input power PmM is the number of stacked channels, the initial temperature and the external environment temperature TambEqual; secondly, calculating the structural thermal resistance and the coupling thermal resistance of the multi-layer stacked ring gate field effect transistor at the initial temperature, and calculating the temperature T of the channel at the mth layer according to the thermal resistance matrix theory and the thermal linear superposition theorychm1(ii) a Finally, T is judgedchm1And Tchm0Whether the difference values of (a) are all less than the set threshold value TthIf the difference is less than TthOutputting the final temperature T of each layer of channelchmAnd T ischm＝Tchm1If the difference is greater than TthThen respectively combine Tchm1Is given to the initial temperature Tchm0Continuing the above loop calculation until Tchm1And Tchm0Are all less than a threshold value TthOutputting the final temperature T of each channel layerchmAnd T ischm＝Tchm1。
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