CN112614809A

CN112614809A - Phase change memory and manufacturing method thereof

Info

Publication number: CN112614809A
Application number: CN202011497011.7A
Authority: CN
Inventors: 刘峻; 高王荣; 徐陈林
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-12-17
Filing date: 2020-12-17
Publication date: 2021-04-06
Anticipated expiration: 2040-12-17
Also published as: CN112614809B

Abstract

The present disclosure provides a phase change memory and a method for manufacturing the same, the method including: providing a substrate; a first interconnection line, a first bit line connecting part, a first conductive line and a storage unit are formed in the first dielectric layer of the substrate device region in a stacking mode from bottom to top; a second interconnection line and a third interconnection line are also formed in the device region; forming a first groove which penetrates through the first dielectric layer and extends to the second interconnection line, and forming a second groove which penetrates through the first dielectric layer and extends to the third interconnection line; the opening size of the first groove is smaller than that of the second groove; depositing a first conductive material into the first and second grooves to form a first word line connection in the first groove, a second word line connection in the second groove, and a third groove based on a topography of the second groove; the top of the first word line connection is flush with the top surface of the first dielectric layer.

Description

Phase change memory and manufacturing method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, and in particular relates to a phase change memory and a manufacturing method thereof.

Background

The device region of the phase change memory is used to set the device structure. The device structure comprises a memory cell array and a peripheral circuit, wherein the memory cell array is mainly used for storing data, and the peripheral circuit is mainly used for realizing the function control of phase change memory operation (reading operation, writing operation and the like).

In the manufacturing process of the phase change memory, an alignment structure (alignment mark) is usually used for alignment control to ensure the alignment between the formed device structures.

Disclosure of Invention

The embodiment of the disclosure provides a phase change memory and a manufacturing method thereof, comprising the following steps:

according to a first aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a phase change memory, including:

providing a substrate; the first interconnection line, the first bit line connecting part, the first conductive line and the memory unit are sequentially stacked from bottom to top in the first dielectric layer of the substrate device region; in the device area, a second interconnection line and a third interconnection line are further formed on the substrate;

forming a first groove which penetrates through the first dielectric layer and extends to the second interconnection line, and forming a second groove which penetrates through the first dielectric layer and extends to the third interconnection line; wherein the opening size of the first groove is smaller than the opening size of the second groove;

depositing a first conductive material into the first and second grooves to form a first wordline connection in the first groove and a second wordline connection in the second groove, and forming a third groove based on a topography of the second groove; wherein the top of the first word line connection portion is flush with the top surface of the first dielectric layer.

In some embodiments, the substrate includes an alignment region juxtaposed with the device region, the method further comprising:

depositing a second conductive material on the first word line connecting part, the second word line connecting part and the surface of the memory cell to form a conductive layer; wherein the second conductive material deposited on the surface of the second word line connection portion forms a fourth groove based on the topography of the third groove;

forming a fifth groove penetrating through the first dielectric layer in the alignment region based on the fourth groove; the fifth groove is aligned with the fourth interconnecting line in the alignment area.

In some embodiments, prior to said depositing a second conductive material to said first word line connection, said second word line connection and said memory cell surface, said method further comprises:

forming a conductive adhesive layer covering the first word line connection portion, the second word line connection portion, and the memory cell;

depositing the second conductive material to the first word line connection portion, the second word line connection portion, and the memory cell surface after forming the adhesive layer;

the bonding layer is used for increasing the adhesive force between the conductive layer and the first word line connecting portion, between the conductive layer and the memory cell, between the conductive layer and the first dielectric layer, and between the conductive layer and the second word line connecting portion.

In some embodiments, the first interconnect lines, the second interconnect lines, the third interconnect lines, and the fourth interconnect lines are formed on a surface of a second dielectric layer, the method further comprising:

forming a third dielectric layer covering the first interconnection line, the second interconnection line, the third interconnection line and the fourth interconnection line; the third dielectric layer is positioned between the first dielectric layer and the second dielectric layer; and the hardness of the third dielectric layer is greater than that of the first dielectric layer.

In some embodiments, the first dielectric layer includes a first sub-layer and a second sub-layer stacked, the first recess includes a first sub-groove and a second sub-groove, and the method includes:

forming the first sub-trench extending through the first sub-layer and to the interconnect line;

filling the first subslot with the first conductive material to form a first conductive pillar in the first subslot;

forming the second sublayer over the first sublayer;

forming the second sub-trench penetrating through the second sub-layer and extending to the first conductive pillar; wherein the opening size of the second subslot is smaller than the opening size of the first subslot;

filling the second sub-grooves with the first conductive material to form second conductive pillars in the second sub-grooves; wherein the first word line connection portion includes the first conductive pillar and the second conductive pillar.

In some embodiments, the method further comprises:

forming a first barrier layer covering the first sub-trench before filling the first conductive material into the first sub-trench;

forming a second barrier layer covering the second sub-trench before filling the first conductive material into the second sub-trench;

the filling of the first subslot with a first conductive material includes: filling the first sub-groove with the first barrier layer;

the filling of the first conductive material into the second sub-slot includes: filling the second sub-groove with the second barrier layer with the first conductive material.

In some embodiments, the material of the first interconnect line, the second interconnect line, and the third interconnect line comprises copper;

the first and second conductive materials comprise tungsten;

the materials of the first barrier layer and the second barrier layer comprise tungsten nitride and/or titanium nitride.

In some embodiments, the opening size of the second groove is greater than 1 micron.

In some embodiments, the depth of the second recess is greater than or equal to 2000 angstroms.

According to a second aspect of the embodiments of the present disclosure, a phase change memory is provided, which is manufactured by applying the method provided in the first aspect of the embodiments of the present disclosure.

Since the conductive layer includes the first conductive material that is opaque, in order to align the interconnect on the substrate and the functional structure formed behind the conductive layer, in the related art, it is necessary to form a first alignment structure in the alignment region before forming the conductive layer, then form a second alignment structure in the alignment region by using the shape of the first alignment structure after forming the conductive layer, and then form the above-mentioned functional structure aligned with the corresponding interconnect in the device region by using the second alignment structure. That is, in order to align the interconnect and the functional structure in the related art, two alignment structures need to be formed in the alignment region in sequence, the occupied area in the alignment region is large, the number of process steps is large, and the process cost is high.

In the embodiment of the disclosure, since the opening size of the second groove is larger than the opening size of the first groove, the first word line connection portion is formed in the first groove, and after the second word line connection portion is formed in the second groove, the top of the first word line connection portion is flush with the top surface of the first dielectric layer, and the first conductive material deposited in the second groove forms the third groove based on the shape of the second groove, the third groove can be subsequently used as the first alignment structure, so as to form the second alignment structure in the alignment region.

It can be emphasized that, since the third recess is formed based on the profile of the second recess after the second word line connection portion is formed, it is not necessary to form a new recess exclusively in the alignment region as the first alignment structure, and thus, the process steps are reduced and the process cost is reduced.

Drawings

FIG. 1 is a three-dimensional view of a portion of a phase change memory shown in accordance with an exemplary embodiment;

FIGS. 2 a-2 c are schematic diagrams illustrating a method of fabricating a phase change memory according to an exemplary embodiment;

FIG. 3 is a flow chart illustrating a method of fabricating a phase change memory according to one exemplary embodiment;

fig. 4a to 4e are schematic diagrams illustrating a method of manufacturing a phase change memory according to an exemplary embodiment.

Fig. 5 is a schematic diagram illustrating a partial structure of a phase change memory according to an exemplary embodiment.

Detailed Description

The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

It is to be understood that the meaning of "on … …," "over … …," and "over … …" in this disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.

In the disclosed embodiment, the term "a is connected to B" includes A, B where a is connected to B in contact with each other, or A, B where a is connected to B in a non-contact manner with other components interposed between the two.

In the embodiments of the present disclosure, the terms "first" and "second", etc. are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers. For example, the interconnect layer may include one or more conductors and contact sub-layers (in which interconnect lines and/or via contacts are formed), and one or more dielectric sub-layers.

The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.

The phase change memory includes a memory cell Array (Array) and peripheral circuits. The memory cell array may be integrated on the same die of the peripheral circuit, which allows for a wider bus and higher operating speed. In practical applications, the memory cell array and the peripheral circuit may be formed in different regions on the same plane; or the memory cell array and the peripheral circuit may form a stacked structure, i.e., they are formed on different planes. For example, the memory cell array may be formed over peripheral circuits to reduce the chip size.

In some embodiments, the peripheral circuitry includes any suitable digital, analog, and/or mixed-signal circuitry for facilitating phase change memory operations. For example, the peripheral circuits may include control logic, data buffers, decoders (which may also be referred to as decoders), drivers, and read/write circuits, among others. When the control logic receives the read-write operation command and the address data, under the action of the control logic, the decoder can apply corresponding voltages generated by the driver to corresponding bit lines and word lines based on the decoded address so as to realize the read-write of the data, and the data interaction is carried out with the outside through the data buffer.

In some embodiments, the memory cell array is used primarily for storing data. In practical applications, the Memory cell array includes a plurality of Memory cells, and each Memory cell may include a stacked Phase Change Memory (PCM) layer 102, a gate layer 104, and a plurality of electrode layers 101, 103, and 105 (as shown in fig. 1). The PCM layer 102 may utilize the difference between the resistivity of the amorphous and crystalline phases in the phase change material based on the electro-thermal heating and quenching of the phase change material. A current may be applied to repeatedly switch the phase change material of the PCM layer 102 (or at least part of the current path it blocks) between the amorphous and crystalline phases to store data. A single bit of data can be stored in each memory cell and can be written or read by varying the voltage applied to the corresponding pass layer 104, which eliminates the need for transistors.

FIG. 1 is a three-dimensional view of a portion of a phase change memory shown in accordance with an exemplary embodiment. Referring to fig. 1, the memory cell array includes:

a plurality of top bit lines 13 in parallel and a plurality of bottom bit lines 14 in parallel;

there is an offset between the top bit line 13 and the corresponding bottom bit line 14 (one bottom bit line below the top bit line);

a top bit line connection portion 130, contacting the top bit line 13 and extending from between two adjacent bottom bit lines 14, for electrically connecting the top bit line 13 and peripheral circuits (here, the word "connection portion" may be Contact);

a bottom bit line connection portion 141 in contact with the bottom bit line 14 for electrically connecting the bottom bit line 14 with a peripheral circuit;

a plurality of word lines 15 between the top bit lines 13 and the bottom bit lines 14; a plurality of word lines 15 are in the same plane and are parallel to the top bit lines 13 and the bottom bit lines 14;

word line connection portions (not shown) contacting the word lines 15 for electrically connecting the word lines 15 with the relevant devices;

an upper memory cell 11 between the top bit line 13 and the word line 15 and connected to the corresponding top bit line 13 and the word line 15, the plurality of upper memory cells forming a top memory cell layer;

a lower memory cell 12, between the word line 15 and the bottom bit line 14, a plurality of lower memory cells forming a bottom memory cell layer.

It should be noted that, for the phase change memory shown in fig. 1, since the word lines are made of opaque materials, in order to form the top bit line connection portions 130 aligned with the corresponding interconnect lines 16, a first alignment structure is formed in the alignment region before the word lines are formed, then a second alignment structure is formed in the alignment region by using the morphology of the first alignment structure after the word lines are formed, and then the top bit line connection portions 130 aligned with the interconnect lines 16 are formed in the device region by using the second alignment structure. That is, in order to align the interconnect lines 16 and the top bit line connection portions 130 in the related art, two alignment structures need to be formed in the alignment regions in sequence, which not only increases the area of the alignment regions, but also increases the process steps and the cost.

Fig. 2a to 2c are schematic diagrams illustrating a method for fabricating a phase change memory according to an exemplary embodiment, the method including the steps of:

the method comprises the following steps: referring to fig. 2a, a substrate 110 including a device region 110a and an alignment region 110b is provided; the substrate 110 is formed with an interconnection line 120, a third dielectric layer 133 covering the interconnection line, and a first dielectric layer 131 covering the third dielectric layer 133; an interconnection line formed in the second dielectric layer 132 for connecting a peripheral circuit (not shown) of the phase change memory and an address line connection portion; in the device region 110a, a bottom bit line connection portion 141 penetrating the first dielectric layer and the third dielectric layer 133 is formed; forming a first alignment groove 150 vertical to the substrate 110 in the first dielectric layer in the alignment region 110 b; wherein, along the direction perpendicular to the plane of the substrate 110, the projection of the first alignment groove 150 overlaps the projection of the interconnect line 120 e.

Illustratively, the first alignment groove may be formed by a plasma etching process. As shown in fig. 2a, the depth of the first alignment groove is less than the thickness of the first dielectric layer. I.e., a first dielectric layer of a certain thickness exists between the bottom of the first alignment groove and the interconnect line 120 e.

In some embodiments, the depth of the first alignment groove may be equal to the thickness of the first dielectric layer. In other embodiments, over-etching may occur during the formation of the first alignment recess, i.e., etching a portion of the third dielectric layer 133, such that the depth of the first alignment recess is greater than the thickness of the first dielectric layer.

The address line connecting portion includes: a bit line connection portion and a word line connection portion. It will be appreciated that the top and bottom bit line connections are bit line connections.

Step two: forming a word line connection part 151 electrically connected to the interconnection line 120b in the first dielectric layer located in the device region 110a after forming the first alignment groove; depositing a word line material layer 152 on the surface of the first dielectric layer and in the first alignment groove; etching the word line material and the first dielectric layer in the alignment area to form a second alignment groove 160; wherein, along the direction perpendicular to the plane of the substrate 110, the projection of the second alignment groove 160 overlaps the projection of the interconnect line 120 d.

As shown in fig. 2b, a first dielectric layer of a certain thickness is present between the bottom of the second alignment groove and the interconnect line 120 d.

In some embodiments, the depth of the second alignment recess may be equal to the sum of the thicknesses of the first dielectric layer and the layer of word line material. In other embodiments, an over-etch may occur during the formation of the second alignment recess, i.e., etching a portion of the third dielectric layer 133, such that the bottom of the second alignment recess is located in the third dielectric layer 133.

Step three: referring to fig. 2c, a fourth dielectric layer 134 is formed overlying the layer of word line material and the second alignment recess.

Illustratively, the fourth dielectric layer may be formed by means of chemical vapor deposition. The composition material of the fourth dielectric layer may include: silicon nitride, silicon oxynitride, or the like.

It is emphasized that the fourth dielectric layer deposited in the second alignment groove can conformally cover the second alignment groove to form the alignment sub-groove based on the topography of the second alignment groove. Since the alignment sub-recess is aligned with the interconnect line 120d and the interconnect line 16 are parallel to the plane of the substrate 110, the top bit line connection 130 aligned with the interconnect line 16 can be formed in a subsequent process by aligning the alignment sub-recess according to the known relative position relationship between the interconnect line 120d and the interconnect line 16.

Note that the interconnect line 120a, the interconnect line 120b, the interconnect line 120d, the interconnect line 120e, and the interconnect line 16 are all interconnect lines. However, the different interconnect lines function differently. Specifically, as shown in fig. 1 and 2a in conjunction, the interconnect line 120a is used to electrically connect the bottom bit line connection 141 with the peripheral circuit, the interconnect line 120b is used to electrically connect the word line connection with the peripheral circuit, and the interconnect line 16 is used to electrically connect the top bit line connection 13 with the peripheral circuit. By providing interconnect line 120d and interconnect line 120e, a known relative positional relationship between interconnect line 16, interconnect line 120d, and interconnect line 120e is utilized to form a top bitline connection 130 aligned with interconnect line 16.

For the phase change memory shown in fig. 1, since the composition material of the word line is opaque, in order to form the top bit line connection portion 130 aligned with the interconnect line 16, it is necessary to form a first alignment recess 150 aligned with the interconnect line 120e as a first alignment structure in the alignment region before forming the word line, and then form a second alignment recess 160 aligned with the interconnect line 120d as a second alignment structure in the alignment region using the relative positional relationship between the first alignment structure and the interconnect line 120d after forming the word line material layer, and then form the top bit line connection portion 130 aligned with the interconnect line 16 in the device region using the relative positional relationship between the second alignment structure and the interconnect line 16.

That is, in order to form the top bit line connection portion 130 aligned with the interconnection line 16 in the related art, two alignment structures, i.e., the first alignment groove 150 and the second alignment groove 160, need to be formed in the alignment region in sequence, and the occupied area in the alignment region is large, and the number of process steps and the process cost are high.

Fig. 3 is a flow chart illustrating a method of manufacturing a phase change memory according to an example embodiment. Referring to fig. 3, the method includes the steps of:

s100: providing a substrate; the first interconnection line, the first bit line connecting part, the first conductive line and the memory unit are sequentially stacked from bottom to top in the first dielectric layer of the substrate device region; in the device area, a second interconnection line and a third interconnection line are further formed on the substrate;

s110: forming a first groove which penetrates through the first dielectric layer and extends to the second interconnection line, and forming a second groove which penetrates through the first dielectric layer and extends to the third interconnection line; the opening size of the first groove is smaller than that of the second groove;

s120: depositing a first conductive material into the first and second grooves to form a first word line connection portion in the first groove and a second word line connection portion in the second groove, and forming a third groove based on a topography of the second groove; the top of the first word line connecting part is flush with the top surface of the first dielectric layer.

Fig. 4a to 4c are schematic diagrams illustrating a method of manufacturing a phase change memory according to an exemplary embodiment. A method for manufacturing a phase change memory according to an embodiment of the present disclosure is described below with reference to fig. 3 and fig. 4a to 4 c.

Referring to fig. 4a, the substrate 110 provided in S100 may include a semiconductor material, such as silicon, germanium, or gallium arsenide. The substrate 110 may also include peripheral circuitry for phase change memory formed on the semiconductor material. It is understood that the peripheral circuit may be formed in a predetermined region of the surface of the semiconductor material by ion doping or the like.

A device region 110a of the substrate 110 for disposing a functional device of the phase change memory. The functional device may include: memory cells, interconnect lines, address lines, and address connections. The address lines may include word lines and bit lines. The address connection portion includes a word line connection portion and a bit line connection portion.

In the first dielectric layer 131 of the device region 110a of the substrate 110, a first interconnection line 120a, a first bit line connection portion 141, a first conductive line and a memory cell are formed in a stacked manner in sequence from bottom to top; in the device region 110a, second and

third interconnection lines

120b and 120c are also formed on the substrate 110.

Illustratively, the first dielectric layer 131 may be formed by chemical vapor deposition. The first dielectric layer 131 may be made of an insulating oxide such as silicon oxide.

In some embodiments, the phase change memory may further include a second dielectric layer 132 between the substrate 110 and the first dielectric layer 131. The second dielectric layer 132 may be formed by chemical vapor deposition. The second dielectric layer 132 may comprise silicon oxide.

Illustratively, the interconnection line 120 may be formed by physical vapor deposition or atomic layer vapor deposition, for example. The constituent materials of the interconnect line 120 may include: metal (e.g., tungsten or copper) or polysilicon.

It may be understood that the first interconnect lines 120a, the second interconnect lines 120b, and the third interconnect lines 120c are all interconnect lines. When the phase change memory includes the second dielectric layer 132, the first interconnection lines 120a, the second interconnection lines 120b, and the third interconnection lines 120c are located on a surface of the second dielectric layer 132 contacting the first dielectric layer 131.

Illustratively, the first bit line connection part 141 may be formed by physical vapor deposition, chemical vapor deposition, or the like. The composition material of the first bit line connection part 141 may include a conductive material, for example, a metal (e.g., tungsten, copper, or the like), polysilicon, or the like.

Referring to fig. 4b, in the device region 110a, a first groove 171 penetrating the first dielectric layer 131 and extending to the second interconnection line 120b may be formed by dry etching, and a second groove 172 penetrating the first dielectric layer 131 and extending to the third interconnection line 120c may be formed by dry etching in S110; wherein, the opening size of the first groove 171 is smaller than the opening size of the second groove 172.

For example, the first dielectric layer 131 is made of silicon dioxide, and Carbon Fluoride (CF) may be used₄) As an etching gas, the first and

second grooves

171 and 172 are formed using a plasma etching process.

For example, each of the first and

second grooves

171 and 172 may include: a cylindrical hole, or a rectangular parallelepiped channel, etc. Taking the first groove 171 and the second groove 172 as cylindrical holes as an example, the opening of the first groove 171 and the opening of the second groove 172 are both circular, and the opening size of the first groove 171 and the opening size of the second groove 172 may both include: opening radius, opening diameter, or opening area.

The opening diameter of the first groove 171 may be less than 1 micrometer. The opening diameter of the second groove 172 may be greater than 1 micron, for example, the opening diameter of the second groove 172 may comprise 1.6 microns.

It is noted that the depth of the first recess 171 is the same as the depth of the second recess 172 in a direction perpendicular to the plane of the substrate 110.

Referring to fig. 4c, in S120, a first conductive material is deposited into the first and

second grooves

171 and 172 to form a first word line connection portion 181 in the first groove 171 and a second word line connection portion 182 in the second groove 172, and a third groove 173 is formed based on the topography of the second groove 172; wherein the top of the first word line connection portion 181 is flush with the top surface of the first dielectric layer 131.

Illustratively, the first conductive material may be deposited into the first and

second grooves

171 and 172 by atomic layer vapor deposition or physical vapor deposition. The first conductive material may include: tungsten, copper, or polysilicon, etc.

It is noted that, since the opening size of the first recess 171 is smaller than the opening size of the second recess 172, when the depth of the first recess 171 is equal to the depth of the second recess 172 and the first recess 171 is filled with the first conductive material, the volume of the first conductive material filled in the second recess 172 is smaller than the volume of the second recess 172, i.e., the top of the second wordline connection portion 182 is lower than the top surface of the first dielectric layer 131.

The thickness of the second word line connection part 182 is less than the depth of the second recess 172. Illustratively, the depth of the second recess 172 may be greater than or equal to 2000 angstroms and the thickness of the second word line connection 182 may include 1000 angstroms.

In the embodiment of the disclosure, since the opening size of the second recess 172 is larger than the opening size of the first recess 171, the first word line connection portion 181 is formed in the first recess 171, and after the second word line connection portion 182 is formed in the second recess 172, the top of the first word line connection portion 181 is flush with the top surface of the first dielectric layer 131, the first conductive material deposited in the second recess 172 forms a third recess based on the topography of the second recess 172, and the third recess may be subsequently used as the first alignment structure to form the second alignment structure in the alignment region.

It can be emphasized that, since the third recess is formed based on the profile of the second recess 172 after the second word line connection portion 182 is formed, there is no need to specially form a new recess in the alignment region as the first alignment structure, which reduces the process steps and the process cost.

In some embodiments, the substrate 110 includes an alignment region 110b juxtaposed with the device region 110a, the method further comprising:

referring to fig. 4d, depositing a second conductive material on the first word line connection portion 181, the second word line connection portion 182, and the surface of the memory cell to form a conductive layer 161; wherein the second conductive material deposited on the surface of the second word line connection portion 182 forms a fourth recess 174 based on the topography of the third recess;

referring to fig. 4e, a fifth groove 175 is formed through the first dielectric layer 131 in the alignment region 110b based on the fourth groove; wherein the fifth recess is aligned with the fourth interconnecting lines 120d in the alignment area.

The alignment region 110b can be used for disposing an alignment structure. In some embodiments, a Scribe lane (Scribe lane) may also be included in alignment area 110 b.

Illustratively, the second conductive material may be deposited by chemical vapor deposition. The second conductive material may include: tungsten metal or polysilicon.

It is understood that, since the fourth recesses are aligned with the third interconnect lines 120c and the fourth interconnect lines are arranged in parallel on the surface of the substrate 110, although the second conductive material is opaque, the fifth recesses 175 aligned with the fourth interconnect lines can be formed according to the distance between the third interconnect lines 120c and the fourth interconnect lines in the direction parallel to the substrate 110, by using the concave feature of the fourth recesses toward the substrate 110 as an alignment structure.

In some embodiments, before depositing the second conductive material to the first word line connection 181, the second word line connection 182, and the memory cell surface, the method further comprises:

referring to fig. 4d, a conductive adhesive layer 190 is formed to cover the first word line connection portion 181, the second word line connection portion 182, and the memory cell;

after the adhesive layer 190 is formed, depositing a second conductive material on the first word line connection portion 181, the second word line connection portion 182, and the surface of the memory cell;

the adhesive layer 190 is used to increase adhesion between the conductive layer 161 and each of the first word line connection portion 181, the memory cell, the first dielectric layer 131, and the second word line connection portion 182.

Illustratively, the adhesive layer 190 may be formed by physical vapor deposition. When the first conductive material includes tungsten, a constituent material of the adhesive layer 190 may include tungsten nitride (WN). When the first conductive material includes copper, the constituent material of the adhesion layer 190 may include tantalum nitride.

The adhesive layer 190 may include: a first portion between the conductive layer 161 and the first word line connection portion 181, a second portion between the conductive layer 161 and the memory cell, a third portion between the conductive layer 161 and the first dielectric layer 131, and a fourth portion between the conductive layer 161 and the second word line connection portion 182.

It is understood that the first portion of the adhesive layer 190 serves to increase adhesion between the conductive layer 161 and the first word line connection portion 181. A second portion of the adhesive layer 190 for increasing adhesion between the conductive layer 161 and the memory cell. And a third portion of adhesive layer 190 to increase adhesion between conductive layer 161 and first dielectric layer 131. A fourth portion of the adhesive layer 190 for increasing adhesion between the conductive layer 161 and the second word line connection portion 182.

In some embodiments, the adhesive layer 190 may further be used to block interdiffusion between the conductive layer 161 and the first word line connection portion 181, the memory cell, the first dielectric layer 131, and the second word line connection portion 182, respectively, so as to ensure good quality of the phase change memory.

By arranging the adhesive layer 190, the embodiment of the disclosure is beneficial to increasing the adhesive force between the conductive layer 161 and the first word line connecting portion 181, the memory cell, the first dielectric layer 131 and the second word line connecting portion 182, reducing the risk that the conductive layer 161 is separated from the first word line connecting portion 181, the memory cell, the first dielectric layer 131 and the second word line connecting portion 182, improving the quality of the contact interface between the conductive layer 161 and the first word line connecting portion 181, the memory cell, the first dielectric layer 131 and the second word line connecting portion 182, and further improving the quality of the phase change memory.

In addition, compared with the insulating adhesive layer 190, the conductive adhesive layer 190 is provided in the embodiment of the disclosure, so that the conductive layer 161 and the first word line connection portion 181, the memory cell and the second word line connection portion 182 can still be electrically contacted through the conductive adhesive layer 190, and the normal performance of the phase change memory is ensured.

In practical applications, when the first recess 171 is formed by an etching process, the first recess 171 generally has a profile with a top opening size larger than a bottom opening size. Here, the top opening of the first groove 171 is an opening relatively far from the substrate 110, and the bottom opening of the first groove 171 is an opening relatively close to the substrate 110.

In order to increase the contact area of the first word line connection portion 181 and the second interconnect line 120b, a hole expansion process may be performed on the bottom of the first groove 171 to ensure good contact of the first word line connection portion 181 and the second interconnect line 120 b.

In some embodiments, referring to fig. 5, the first dielectric layer 131 includes a first sub-layer and a second sub-layer stacked, the first recess 171 includes a first sub-groove and a second sub-groove, and the method includes:

forming a first sub-trench penetrating the first sub-layer and extending to the interconnection line;

filling the first sub-trenches with a first conductive material to form first conductive pillars 1811 in the first sub-trenches;

forming a second sub-layer on the first sub-layer;

forming a second sub-trench that penetrates the second sub-layer and extends to the first conductive pillar 1811; the opening size of the second subslot is smaller than that of the first subslot;

filling the second sub-trenches with the first conductive material to form second conductive pillars 1812 in the second sub-trenches; the first word line connection portion 181 includes first conductive pillars 1811 and second conductive pillars 1812.

The constituent materials of the first and second sublayers may be the same. For example, the constituent materials of the first and second sublayers may include: silicon oxide, silicon oxynitride, or the like.

Illustratively, the first sub-groove and the second sub-groove may be formed by a dry etching process.

The first conductive material may include: tungsten or polysilicon, etc. The first conductive material may be filled by a deposition process, which may specifically include physical vapor deposition, chemical vapor deposition, atomic layer vapor deposition, or the like.

In the embodiment of the present disclosure, the first sub-groove is formed first, and then the second sub-groove is formed, and the opening size of the first sub-groove is larger than that of the second sub-groove, so that the first word line connection portion 181 is formed, the contact area between the first word line connection portion 181 and the second interconnection line 120b is increased, and it is beneficial to ensure that a good electrical contact is formed between the first word line connection portion 181 and the second interconnection line 120 b.

In some embodiments, similarly, in order to increase the contact area of the second word line connection part 182 and the third interconnect line 120c, the bottom of the second groove 172 may be subjected to a broaching process to ensure good contact of the second word line connection part 182 and the third interconnect line 120 c.

In some embodiments, the first and second

conductive pillars

1811 and 1812 may be formed at the same time as the first bit line connection part 141 is formed. Also, as shown in fig. 5, the first word line connection portion 181 may further include third conductive pillars 1813, and the third conductive pillars 1813 may be formed after the memory cell is formed.

In some embodiments, the method further comprises:

the filling of the first sub-groove with the first conductive material includes: filling a first conductive material into the first sub-groove with the first barrier layer;

the filling of the second subslot with the first conductive material includes: and filling the second sub-groove with the second barrier layer with a first conductive material.

Illustratively, the material of the first, second, and

third interconnect lines

120a, 120b, and 120c includes copper; the first and second conductive materials comprise tungsten; the material of the first barrier layer and the second barrier layer comprises tungsten nitride and/or titanium nitride.

Illustratively, the first barrier layer may be formed in the first sub-trench by chemical vapor deposition or atomic layer vapor deposition. The first barrier layer may cover sidewalls and a bottom of the first sub-trench. It is understood that the first barrier layer is located between the first conductive pillars 1811 and the first sub-layer.

The formation process of the second barrier layer and the first barrier layer may be the same. The second barrier layer may cover sidewalls and a bottom of the second sub-trench. It is understood that portions of the second barrier layer, between the second conductive pillars 1812 and the second sub-layer; also, portions of the second barrier layer are located between the bottom of the second conductive pillars 1812 and the tops of the first conductive pillars 1811.

According to the embodiment of the disclosure, the first blocking layer is formed, so that the conductive material which is filled in the first sub-groove later and is lower than the conductive material can be prevented from diffusing into the first sub-layer, and the adhesion between the first conductive material which is filled in the first sub-groove later and the first sub-layer can be improved.

Similarly, by forming the second barrier layer, the embodiment of the disclosure may block the first conductive material subsequently filled in the second sub-trench from diffusing into the second sub-layer, and may improve the adhesion between the first conductive material subsequently filled in the second sub-trench and the second sub-layer.

Therefore, the first barrier layer and the second barrier layer are formed, so that the quality and the stability of the memory are guaranteed.

In some embodiments, referring to fig. 4d, the first interconnect lines 120a, the second interconnect lines 120b, the third interconnect lines 120c, and the fourth interconnect lines are formed on the surface of the second dielectric layer 132, and the method further includes:

forming a third dielectric layer 133 covering the first, second, third and

fourth interconnection lines

120a, 120b, 120c and 120 d; the third dielectric layer 133 is located between the first dielectric layer 131 and the second dielectric layer 132; the hardness of the third dielectric layer 133 is greater than that of the first dielectric layer 131.

Illustratively, the third dielectric layer 133 may be formed by chemical vapor deposition, spin coating, or the like. The composition material of the third dielectric layer 133 may include at least one of: silicon nitride; silicon carbide; silicon oxycarbide; silicon carbonitride; nitrogen doped silicon carbide (NDC), and the like.

In the embodiment of the disclosure, the third dielectric layer 133 with hardness greater than that of the first dielectric layer 131 is formed, so that the third dielectric layer 133 can also serve as an etching barrier layer in the subsequent process of the first dielectric layer 131, so as to protect the morphology of the interconnection line formed on the surface of the second dielectric layer 132 from being damaged, and to ensure that the quality of the phase change memory is good.

It can be understood that the interconnect lines include at least a first interconnect line 120a, a second interconnect line 120b, a third interconnect line 120c, and a fourth interconnect line 120 d.

Fig. 5 is a partial structural schematic diagram illustrating a phase change memory 100 according to an example embodiment. The phase change memory 100 is fabricated using the methods provided by the embodiments of the present disclosure.

In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method of manufacturing a phase change memory, comprising:

2. The method of claim 1, wherein the substrate includes an alignment region juxtaposed to the device region, the method further comprising:

3. The method of claim 2,

prior to the depositing a second conductive material to the first word line connection, the second word line connection, and the memory cell surface, the method further comprises:

4. The method of claim 2, wherein the first interconnect lines, the second interconnect lines, the third interconnect lines, and the fourth interconnect lines are formed on a second dielectric layer surface, the method further comprising:

5. The method of claim 1, wherein the first dielectric layer comprises a first sub-layer and a second sub-layer arranged in a stack, wherein the first recess comprises a first sub-groove and a second sub-groove, and wherein the method comprises:

forming the second sublayer over the first sublayer;

6. The method of claim 5, further comprising:

7. The method of claim 6,

the material of the first interconnect line, the second interconnect line and the third interconnect line comprises copper;

the first and second conductive materials comprise tungsten;

8. The method of claim 1, wherein the opening size of the second groove is greater than 1 micron.

9. The method of claim 1, wherein the depth of the second recess is greater than or equal to 2000 angstroms.

10. A phase change memory fabricated by the method of any one of claims 1 to 9.