CN112613635A - Yield prediction method of chip product, storage medium and terminal - Google Patents

Yield prediction method of chip product, storage medium and terminal Download PDF

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CN112613635A
CN112613635A CN202011330990.7A CN202011330990A CN112613635A CN 112613635 A CN112613635 A CN 112613635A CN 202011330990 A CN202011330990 A CN 202011330990A CN 112613635 A CN112613635 A CN 112613635A
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不公告发明人
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Advanced Manufacturing EDA Co Ltd
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Abstract

A method for predicting yield of chip products, a storage medium and a terminal are provided, the method comprises the following steps: determining a target IP core and/or a target new circuit design module adopted by a chip product to be predicted, wherein the target new circuit design module occupies a preset area proportion on each chip product to be predicted; determining a first influence weight of the target IP core on the yield of the chip product to be predicted according to the historical shipment volume of the target IP core, and/or determining a second influence weight of the target new circuit design module on the yield of the chip product to be predicted according to the proportion of the area of the target new circuit design module in the area of the chip product to be predicted; and predicting the yield of the chip product to be predicted according to the first influence weight and/or the second influence weight. The invention can make the predicted yield more accurate.

Description

Yield prediction method of chip product, storage medium and terminal
Technical Field
The invention relates to the technical field of semiconductors, in particular to a yield prediction method of a chip product, a storage medium and a terminal.
Background
Currently, there are many Yield Management System (YMS) software tools from various companies in the semiconductor industry for Yield analysis and Yield Management of chip products. These YMS tools may import various manufacturing test data for interactive analysis, including: process History data (including Process steps, equipment, time, programs, etc.), on-line metrology data, off-line metrology data, defect data, wafer acceptance test data (WAT), pin-on-chip (Bin) data, chip test parameter value data, and in recent years some companies' YMS tools may even support large-scale data analysis of Process tool parameter defect analysis (FDC).
However, the yield obtained by the conventional yield prediction method is often low in accuracy. Specifically, current YMS tools are common to different products, and even different products of the same process technology may have very different yields in the same foundry, even from the same family of design companies.
There is a need for a method for predicting yield of chip products, which can improve the accuracy of yield prediction.
Disclosure of Invention
The invention aims to provide a method for predicting the yield of a chip product, a storage medium and a terminal, so that the predicted yield is more accurate.
In order to solve the above technical problem, an embodiment of the present invention provides a method for predicting yield of a chip product, including: determining a target IP core and/or a target new circuit design module adopted by a chip product to be predicted, wherein the target new circuit design module occupies a preset area proportion on each chip product to be predicted; determining a first influence weight of the target IP core on the yield of the chip product to be predicted according to the historical shipment volume of the target IP core, and/or determining a second influence weight of the target new circuit design module on the yield of the chip product to be predicted according to the proportion of the area of the target new circuit design module in the area of the chip product to be predicted; and predicting the yield of the chip product to be predicted according to the first influence weight and/or the second influence weight.
Optionally, determining, according to the historical shipment volume of the target IP core, a first influence weight of the target IP core on the yield of the chip product to be predicted includes: when the target IP core comprises at least one type of IP core, acquiring the historical shipment volume of the chip product of each type of IP core; for each class of IP core, determining the class of IP core according to the historical shipment volume of the chip product, and determining the IP weight value of the class of IP core based on the class of the IP core; and determining a first influence weight in the chip product to be predicted based on the obtained at least one IP weight value.
Optionally, for each class of IP core, determining a class to which the class of IP core belongs according to the historical shipment volume of the chip product, and determining an IP weight value of the class to which the class of IP core belongs based on the class to which the class belongs includes: obtaining effective chip products of the IP cores of each category, wherein the effective chip products are the chip products of which the historical shipment volume is greater than or equal to a preset shipment threshold value; determining the grade of the IP core of each category according to the total number of the effective chip products of the IP core of each category and the total number of the wafers of the effective chip products of the IP core of each category, and determining the IP weight value of the grade of the IP core of each category based on the grade.
Optionally, the formula adopted for determining the first influence weight in the chip product to be predicted is expressed as:
Figure BDA0002795810700000021
where W1 denotes a first impact weight, xiIndicates the total number of IP cores of the ith class, w1iAn IP weight value of an IP core of the ith class is represented, and n represents the number of classes of the IP core.
Optionally, the target new circuit design module includes multiple classes of new circuit design modules, each class of new circuit design module having a circuit weight value; determining a second influence weight in the chip product to be predicted according to the proportion of the area of the new circuit design module to the chip area by adopting the following formula:
Figure BDA0002795810700000022
wherein W2 is used to represent the second influence weight, yiFor indicating the proportion of the area of the ith new circuit design block to the chip area, w2iFor representing the circuit weight values of the ith new circuit design block.
Optionally, the target new circuit design module includes multiple classes of new circuit design modules, each class of new circuit design module having a circuit weight value; the circuit weight value satisfies one or more of: determining a circuit weight value of a new circuit design module in the chip product to be predicted based on a design range of a preset electrical parameter of the chip product to be predicted; determining a circuit weight value of the new circuit design module of the category based on the size of the metal wire in the new circuit design module and the weighted value of the metal wire of the layer; and determining a circuit weight value of the new circuit design module in the chip product to be predicted based on the area ratio of the new circuit design module in the chip product to be predicted.
Optionally, the new circuit design module includes a logic circuit, an analog circuit, and a pixel array capacitor circuit; the circuit weight value of the analog circuit is greater than that of the logic circuit, and the circuit weight value of the logic circuit is greater than that of the pixel array capacitor circuit.
Optionally, before predicting the yield of the chip product to be predicted according to the first influence weight and/or the second influence weight, the method further includes: calculating the initial yield of the chip product to be predicted by adopting a preset yield prediction formula; predicting the yield of the chip product to be predicted according to the first influence weight comprises the following steps: determining a first yield of the chip product to be predicted according to the product of the initial yield and the first influence weight; predicting the yield of the chip product to be predicted according to the second influence weight comprises the following steps: determining a second yield of the chip product to be predicted according to the ratio of the initial yield to the second influence weight; predicting the yield of the chip product to be predicted according to the first influence weight and the second influence weight comprises the following steps: and taking the product of the initial yield and the first influence weight as a first product, and taking the ratio of the first product to the second influence weight as a third yield of the chip product to be predicted.
Optionally, the preset yield prediction formula is selected from: bose einstein formula and Flop count yield prediction formula.
Optionally, before predicting the yield of the chip product to be predicted according to the first influence weight and/or the second influence weight, the method further includes: determining a third influence weight under the condition that the chip product to be predicted contains a preset transistor device; determining the first yield of the chip product to be predicted according to the product of the initial yield and the first influence weight comprises: taking the product of the initial yield and the first influence weight and the third influence weight as the first yield of the chip product to be predicted; determining a second yield of the chip product to be predicted according to a ratio of the initial yield to the second influence weight comprises: taking the ratio of the initial yield to the second influence weight as a first quotient; taking the product of the first quotient and the third influence weight as a second yield of the chip product to be predicted; determining a third yield of the chip product to be predicted according to the ratio of the first product to the second impact weight comprises: taking the quotient of the first product and the second impact weight as a second quotient value; and taking the product of the second quotient and the third influence weight as a third yield of the chip product to be predicted.
Optionally, before determining the IP core and/or the new circuit design module adopted by the chip product to be predicted, one or more of the following steps are further included: determining that the DRC check result of the chip product to be predicted does not contain a violation item; and determining that the layout graph of the chip product to be predicted does not contain a graph in a preset layout hot spot graph library, wherein the preset layout hot spot graph library contains a known failure graph.
To solve the above technical problem, an embodiment of the present invention provides an apparatus for predicting yield of a chip product, including: the device comprises a design block determining module, a target IP core and/or a target new circuit design module, wherein the target IP core and/or the target new circuit design module are/is used for determining a target IP core and/or a target new circuit design module adopted by a chip product to be predicted, and the target new circuit design module occupies a preset area proportion on each chip product to be predicted; the weight determining module is used for determining a first influence weight of the target IP core on the yield of the chip product to be predicted according to the historical shipment volume of the target IP core, and/or determining a second influence weight of the target new circuit design module on the yield of the chip product to be predicted according to the proportion of the area of the target new circuit design module in the area of the chip product to be predicted; and the yield prediction module is used for predicting the yield of the chip product to be predicted according to the first influence weight and/or the second influence weight.
To solve the above technical problem, an embodiment of the present invention provides a storage medium having a computer program stored thereon, where the computer program is executed by a processor to perform the steps of the yield prediction method for chip products.
In order to solve the above technical problem, an embodiment of the present invention provides a terminal, including a memory and a processor, where the memory stores a computer program capable of running on the processor, and the processor executes the computer program, and performs the steps of the yield prediction method for a chip product.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, by determining the first influence weight of the target IP core adopted by the chip product to be predicted and/or the second influence weight of the target new circuit design module, the actual condition that the target IP core and/or the target new circuit design module are/is produced in the current wafer factory can be fully considered in the process of predicting the yield of the chip product to be predicted, so that the predicted yield is more accurate.
Furthermore, the initial yield of the chip product to be predicted is calculated by adopting a preset yield prediction formula, and then the yield of the chip product to be predicted is determined according to the product of the initial yield and the first influence weight and the ratio of the initial yield to the second influence weight.
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FIG. 1 is a flow chart of a method for predicting yield of a chip product according to an embodiment of the present invention;
FIG. 2 is a flowchart of one embodiment of step S12 of FIG. 1;
FIG. 3 is a partial flow chart of another method for predicting yield of chip products according to another embodiment of the present invention;
fig. 4 is a schematic structural diagram of a yield prediction apparatus for a chip product according to an embodiment of the invention.
Detailed Description
As described above, the yield obtained by the conventional yield prediction method is often low in accuracy. Specifically, current YMS tools are common to different products, and even different products of the same process technology may have very different yields in the same foundry, even from the same family of design companies.
The inventor of the present invention has found through research that, in the existing yield prediction method, the difference of products is not considered, and the specific devices adopted in the specific chip products are not considered, for example, whether a pre-designed design module (IP Core, also called IP Core) is adopted, whether a new circuit design module obtained by new design is adopted for the chip product, and the like, but for the products with larger difference, the same yield prediction method is still adopted for prediction, which results in lower prediction accuracy.
In the embodiment of the invention, by determining the first influence weight of the target IP core adopted by the chip product to be predicted and/or the second influence weight of the target new circuit design module, the actual condition that the target IP core and/or the target new circuit design module are/is produced in the current wafer factory can be fully considered in the process of predicting the yield of the chip product to be predicted, so that the predicted yield is more accurate.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, fig. 1 is a flowchart illustrating a yield prediction method of a chip product according to an embodiment of the invention. The yield prediction method of the chip product may include steps S11 to S13:
step S11: determining a target IP core and/or a target new circuit design module adopted by a chip product to be predicted, wherein the target new circuit design module is applied to each chip product to be predicted;
step S12: determining a first influence weight of the target IP core on the yield of the chip product to be predicted according to the historical shipment volume of the target IP core, and/or determining a second influence weight of the target new circuit design module on the yield of the chip product to be predicted according to the proportion of the area of the target new circuit design module in the area of the chip product to be predicted;
step S13: and predicting the yield of the chip product to be predicted according to the first influence weight and/or the second influence weight.
In the specific implementation of step S11, after the chip product design is completed, the target IP core and/or the target new circuit design module adopted by the chip product may be determined, and the detailed data of the proportion of the area occupied by the target new circuit design module on each chip product to be predicted may be determined.
The IP core may be a design module with a specific function in a chip circuit design, may be designed in advance or even manufactured and applied before a current chip product is designed, and may be applied to different chip products according to requirements, such as an analog-to-digital converter (ADC/DAC), a Digital Signal Processor (DSP), a serializer/deserializer (SERDES), and the like.
The new circuit design module may be a newly designed circuit module according to the specific requirements of the chip, such as an analog circuit, a logic circuit, a Pixel (Pixel) array capacitor, and the like.
In a specific implementation of step S12, a first influence weight of the target IP core on the yield of the chip product to be predicted may be determined according to the historical shipment volume of the target IP core, and a second influence weight of the target new circuit design module on the yield of the chip product to be predicted may be determined according to a ratio of an area of the target new circuit design module to an area of the chip product to be predicted.
Specifically, only the first influence weight or the second influence weight may be determined according to the characteristics of the chip product, and both the first influence weight and the second influence weight may be determined, so as to predict the yield in the subsequent step according to the determined weights.
Referring to fig. 2, fig. 2 is a flowchart of an embodiment of step S12 in fig. 1. The step of determining the first influence weight of the target IP core on the yield of the chip product to be predicted according to the historical shipment volume of the target IP core may include steps S21 to S23, which are described below.
In step S21, when the target IP core includes at least one type of IP core, the historical shipment volume of the chip product of each type of IP core is acquired.
The target IP core includes at least one type of IP core, which may be a single type of IP core, or multiple types of IP cores.
In step S22, for each class of IP core, the class to which the class of IP core belongs is determined according to the historical shipment volume of the chip product, and based on the class to which the class belongs, the IP weight value of the class to which the class of IP core belongs is determined.
Further, for each class of IP core, determining a class to which the class of IP core belongs according to the historical shipment volume of the chip product, and based on the class to which the class belongs, determining an IP weight value of the class to which the class of IP core belongs may include: obtaining effective chip products of the IP cores of each category, wherein the effective chip products are the chip products of which the historical shipment volume is greater than or equal to a preset shipment threshold value; determining the grade of the IP core of each category according to the total number of the effective chip products of the IP core of each category and the total number of the wafers of the effective chip products of the IP core of each category, and determining the IP weight value of the grade of the IP core of each category based on the grade.
In step S23, a first influence weight in the chip product to be predicted is determined based on the obtained at least one IP weight value.
Further, the formula adopted for determining the first influence weight in the chip product to be predicted can be expressed as:
Figure BDA0002795810700000071
where W1 denotes a first impact weight, xiIndicates the total number of IP cores of the ith class, w1iAn IP weight value of an IP core of the ith class is represented, and n represents the number of classes of the IP core.
In a specific implementation manner of the embodiment of the present invention, the maturity of the IP core may be determined according to whether the IP core is already in multiple products and the condition of mass production verification, so as to perform level evaluation on the IP core.
For example, if there are 3 products (> 100 wafers per product), and electrical tests and shipments totaling over 1000 wafers, confirming the maturity of the IP, then the IP core is rated as a first class (e.g., platinum class); if the maturity of the IP is confirmed by electrical testing and shipment of 2 products (> 50 wafers per product), totaling over 500 wafers, the IP core is rated as a second level (e.g., gold); by analogy, there were 1 product that exceeded 100 validations, rated a third level (e.g., silver level); a fourth grade (e.g., bronze grade) was evaluated if 1 product exceeded 20 wafer validations. When n is 4. It is noted that the maturity may be quantified and characterized by a level, for example, the higher the maturity of the IP core is, the higher the level is, as set the level of the IP core with the highest maturity as the first level above.
In a specific implementation, the maturity of the IP core may be determined according to other parameters, for example, according to how long the IP core has been over-production verified in a product with a continuous production duration, and then the IP core is rated, where if the continuous production duration of the product in which the IP core is located is set to be longer, the maturity of the IP core is higher, and the rating is higher.
Specifically, the maturity of the IP core may be scored first, and then the score is used as a first influence weight, or the first influence weight may be determined according to the score, for example, different score ranges have corresponding first influence weight values.
More specifically, the design IP maturity score S1 ═ 100% to silver grade IP core count × 0.1% to bronze grade IP core count × 5% may be set.
In one implementation, each level has a pre-set IP weight value for each class of IP core in that level, e.g., in the second level, IP core a has a weight value of 0.2% and IP core B has a weight value of 0.1%. In the third level, the weight of IP core C is 3% and the weight of IP core D is 4%.
Therefore, it can be understood that the same IP core may be in different levels, and then the corresponding weight value in the level may be obtained, whereas for the total number of IP cores, if the second level only includes IP core a and IP core B, then the total number of IP cores is 2 for the second level and the third level. Then for W1, it is specifically calculated as:
W1＝1-(0.2％*2+0.1％*2+3％*2+4％*2)＝14.6％
the parameters such as the product number, the wafer number, and the weight value in the above formula may be adjusted according to specific situations, which is not limited in the embodiments of the present invention. In addition, it should be noted that when the IP core is applied to different products, the IP core may be located in different levels, and then the corresponding weight values of the IP core in the different levels may be different.
It can be understood that any IP is not robust enough in some way in design (for example, it is very sensitive to timing delay, and it may cause abnormal operation of the IP when the delay of the signal output to the IP by the previous stage circuit is slightly larger but still within the specification range of the specification), when it is applied to a certain product, because the timing delay of the product design is slightly longer (but still meets the specification requirement), there may be a case that the IP in all chips cannot operate normally, i.e. the yield is 0%; if the timing delay of some chips is long due to random floating differences in the chip production process, and the IP in these chips cannot operate normally, yield loss with different magnitudes occurs. Therefore, whether the IP has an inherent defect or not is a key factor which can reduce the yield from a very high number to 0%. The floating differences of a plurality of chips with different designs and a large number of wafers in the actual production process can cover the range of the whole design specification (namely, transistors in the chips are faster or slower than a target value due to random floating differences in the process, the time sequence delays of all the chips form a distribution which covers the labeling range in the whole design specification), and the weakness of the IP is revealed. On the contrary, if the actual verification of multiple products and thousands of wafers does not show related failure, it can be determined that the maturity of the IP is higher.
In the embodiment of the invention, by determining the first influence weight of the target IP core adopted by the chip product to be predicted, the actual condition that the target IP core is produced in the current wafer factory can be fully considered in the process of predicting the yield of the chip product, so that the predicted yield is more accurate.
In another specific implementation of the embodiment of the present invention, the target new circuit design module includes a plurality of classes of new circuit design modules, and each class of new circuit design module has a circuit weight value.
With continued reference to fig. 1, in a specific implementation of step S12, the following formula may be used to determine the second influence weight in the chip product to be predicted according to the ratio of the area of the new circuit design module to the chip area:
Figure BDA0002795810700000101
wherein W2 is used to represent the second influence weight, yiFor indicating the proportion of the area of the ith new circuit design block to the chip area, w2iFor representing the circuit weight values of the ith new circuit design block.
Further, the target new circuit design modules include multiple classes of new circuit design modules, each class of new circuit design module having a circuit weight value; the circuit weight values may satisfy one or more of: determining a circuit weight value of a new circuit design module in the chip product to be predicted based on a design range of a preset electrical parameter of the chip product to be predicted; determining a circuit weight value of the new circuit design module of the category based on the size of the metal wire in the new circuit design module and the weighted value of the metal wire of the layer; and determining a circuit weight value of the new circuit design module in the chip product to be predicted based on the area ratio of the new circuit design module in the chip product to be predicted.
Further, determining a circuit weight value of a new circuit design module in the chip product to be predicted based on the design range of the preset electrical parameter of the chip product to be predicted may include: the smaller the difference between the upper limit design value and the lower limit design value of the preset electrical parameter of the chip product to be predicted is, the larger the circuit weight value of each new circuit design module in the chip product to be predicted is.
Determining the circuit weight values for the class of new circuit design modules based on the metal line sizes in the new circuit design modules and the weight values for the layer of metal lines may include: the smaller the weighted calculation value of the metal wire size of one or more metal layers in each category of new circuit design module, the larger the circuit weight value of the category of new circuit design module.
Determining a circuit weight value of the new circuit design module in the chip product to be predicted based on the area ratio of the new circuit design module in the chip product to be predicted may include: the larger the area ratio of the new circuit design module in the chip product to be predicted is, the larger the circuit weight value of the new circuit design module in the chip product to be predicted is.
The design values of the upper limit and the lower limit of the preset electrical parameter may be design values of process specifications (spec) of the preselected electrical parameter (such as output voltage, output current, and the like), a difference value between the design values of the upper limit and the lower limit of the preset electrical parameter (that is, the upper limit design value and the lower limit design value) is a design range, and when the design range is smaller, the design range indicates that the process requirement of the chip product to be predicted is higher, and the circuit weight value of each new circuit design module in the chip product to be predicted may also be larger. It is understood that the design range of the preset electrical parameter can also be used to represent other suitable meanings such as the quotient of the upper design value and the lower design value.
In a specific implementation manner of the embodiment of the present invention, a difference between an upper limit design value and a lower limit design value of a preset electrical parameter of the chip product to be predicted and a circuit weight value of each new circuit design module in the chip product to be predicted may be in direct proportion, and specifically, a scaling coefficient may be set, which is not limited in the embodiment of the present invention.
The weighted operation value of the sizes of the metal lines of one or more metal layers in the new circuit design module may be a weighted sum value, a weighted average value, or a weighted median of the sizes of the metal lines of the multiple metal layers, and specifically, a weighting coefficient corresponding to each metal layer may be preset. Based on the same process platform, the smaller the size of a single metal wire is, the greater the process complexity is, the lower the process tolerance is, the higher the process requirement of the chip product to be predicted is, and the larger the circuit weight value of the new circuit design module may be.
In one implementation, a weighting coefficient may be set for the metal lines in each layer in the new circuit design module, and the total weighted sum may be the sum of the product of the metal line size and the weighting coefficient in each layer, or the sum of the product of the metal line size and the weighting coefficient in a certain type of metal line (the size of the metal line is the same when the metal line sizes are different, and the average value of the metal line may be calculated if the metal line sizes are different) and the weighting coefficient in the certain type of metal line multiplied by the metal line size, or the weighted average value or the weighted median value may be only able to reflect the sum of the product of the metal line size and the corresponding weighting coefficient.
In a specific implementation manner of the embodiment of the present invention, the weighted calculation value of the metal line size of the one or more metal layers in each kind of new circuit design module may be inversely proportional to the circuit weight value of the new circuit design module, and specifically, an inverse proportionality coefficient may be set, which is not limited in the embodiment of the present invention.
The larger the area ratio of the new circuit design module in the chip product to be predicted is, the larger the influence of the new circuit design module on the chip product to be predicted is, and the larger the circuit weight value of the new circuit design module is.
In a specific implementation manner of the embodiment of the present invention, an area ratio of the new circuit design module in the chip product to be predicted and a circuit weight value of the new circuit design module in the chip product to be predicted may be in a direct proportion, and specifically, a proportional coefficient may be set, which is not limited in the embodiment of the present invention.
It should be noted that, when the circuit weight values are required to simultaneously satisfy two or more items, a single circuit weight value may be determined according to each item, and then a weighting operation, such as weighted summation or weighted average, may be performed on the single circuit weight value to obtain the circuit weight value.
Further, the new circuit design module may include multiple categories of circuits, and preset differences between the circuit weight values of the different categories of circuits may be preset.
Specifically, the new circuit design module may include a logic circuit, an analog circuit, and a pixel array capacitance circuit; the circuit weight value of the analog circuit is greater than that of the logic circuit, and the circuit weight value of the logic circuit is greater than that of the pixel array capacitor circuit.
In a specific implementation manner of the embodiment of the present invention, the new circuit design module may be scored first, and then the score is used as the second influence weight, or the second influence weight is determined according to the score, for example, different scoring ranges have corresponding second influence weight values.
Specifically, the circuit type score S2 may be set to 1 × logic circuit area ratio +1.5 × analog circuit area ratio +0.75 × pixel array capacitor circuit area ratio.
It should be noted that the area ratio of the logic circuit is the area ratio of the logic circuit to the circuit corresponding to the new circuit design module; the area occupation ratio of the analog circuit is the area ratio of the analog circuit to the circuit corresponding to the new circuit design module; the area ratio of the pixel array capacitor circuit is the area ratio of the pixel array capacitor circuit to the circuit corresponding to the new circuit design module.
The 1, 1.5, and 0.75 in the above formula may be adjusted according to specific situations, which is not limited in this embodiment of the present invention.
In the embodiment of the invention, by determining the second influence weight of the new circuit design module adopted by the chip product to be predicted, the actual condition that the new circuit design module produces in the current wafer factory can be fully considered in the process of predicting the yield of the chip product, so that the predicted yield is more accurate.
In an implementation of step S13, the yield of the chip product is predicted according to the first influence weight and/or the second influence weight.
Referring to fig. 3, fig. 3 is a partial flowchart of another method for predicting yield of a chip product according to an embodiment of the invention. The other yield prediction method for chip products may include steps S11 to S13 shown in fig. 1, and may further include steps S31 to S34 before step S13, which are described below.
In step S31, an initial yield of the chip product to be predicted is calculated by using a predetermined yield prediction formula.
The preset yield prediction formula can be a Bose Einstein formula and can also be a Flop count yield prediction formula.
Specifically, the Bose Einstein formula is
Figure BDA0002795810700000131
Wherein, Y is used for representing the initial yield of the chip product, A is used for representing the chip area, D0 is used for representing the defect density, alpha is used for representing the process complexity, and k is used for representing the product of the area occupation ratio of the SRAM and the SRAM correction coefficient.
Specifically, the yield prediction formula of the trigger count (Flop count) may be g (Flop _ count), where g (Flop _ count) is a function of a conventional yield management tool correlation fitting formula, and a yield loss prediction formula based on the trigger count is obtained.
The memory cell circuit that can be operated when the clock signal is triggered is called a flip-flop, the flip-flop count is used for indicating the count value of the flip-flop, and a yield loss prediction formula based on the count value and based on the flip-flop count can be used as a reference formula of the embodiment of the invention and is improved on the basis.
In step S32, predicting the yield of the chip product to be predicted according to the first influence weight includes: and determining the first yield of the chip product to be predicted according to the product of the initial yield and the first influence weight.
Specifically, Yield 1 ═ W1 × Y;
yield 1 is used for representing the first Yield, W1 is used for representing the first influence weight, and Y is used for representing the initial Yield of the chip product.
In step S33, predicting the yield of the chip product to be predicted according to the second influence weight includes: and determining a second yield of the chip product to be predicted according to the ratio of the initial yield to the second influence weight.
Specifically, Yield 2 ═ Y ÷ W2;
yield 2 is used for representing the second Yield, W2 is used for representing the second influence weight, and Y is used for representing the initial Yield of the chip product.
In step S34, predicting the yield of the chip product to be predicted according to the first influence weight and the second influence weight includes: and taking the product of the initial yield and the first influence weight as a first product, and taking the ratio of the first product to the second influence weight as a third yield of the chip product to be predicted.
Specifically, Yield 3 ═ W1 × Y ÷ W2;
yield 3 is used for representing the third Yield, W1 is used for representing the first influence weight, W2 is used for representing the second influence weight, and Y is used for representing the initial Yield of the chip product.
In the embodiment of the invention, the initial yield of the chip product to be predicted is calculated by adopting a preset yield prediction formula, and then the yield of the chip product to be predicted is determined according to the product of the initial yield and the first influence weight and the ratio of the initial yield to the second influence weight.
Further, in another yield prediction method for chip products shown in fig. 3, another important parameter may also be introduced: and adopting a third influence weight of the transistor device on the yield of the chip product to be predicted.
Specifically, before step S13, the third influence weight may be determined in a case where a preset transistor device is included in the chip product to be predicted.
Wherein the step of determining the third impact weight may comprise: according to the historical yield of the chip product adopting each preset transistor device, fitting to obtain a yield loss formula f (x) of the chip product to be predicted; determining the third impact weight according to the yield loss formula f (x).
Further, each preset transistor device has a one-to-one correspondence of influencing parameters; obtaining a yield loss formula f (x) of the chip product to be predicted by fitting according to the historical yield loss of the chip product adopting each preset transistor device, wherein the yield loss formula f (x) comprises the following steps: determining historical yield loss of a chip product adopting the preset transistor device for each preset transistor device; determining the number c of the adopted preset transistor devices aiming at each chip product adopting the preset transistor devicesiAnd determining the mean value z of the influencing parameteri(ii) a Based on the number of transistor devices ciWith the mean value z of the corresponding influencing parameteriDetermines a dependency parameter of said predetermined transistor device, i.e. the sum of the products of (a) and (b), i.e. the threshold voltage
Figure BDA0002795810700000151
As for how many historical chip products adopting the preset transistor device, there are how many data on the correlation parameter and yield loss of the transistor device, and the corresponding relation formula f (x) between the correlation parameter and yield loss of the preset transistor device is obtained through the function of the conventional yield management tool correlation fitting formula, and the specific fitting process can refer to the conventional solving process of the correlation fitting formula, which is not described in detail in the embodiments of the present invention.
Further, according to the yield loss formula f (x), determining a third impact weight includes: determining the average value of the influence parameters of the trial run chip of the chip product to be predicted; determining a third impact weight according to the yield loss formula f (x) using the following formula:
Figure BDA0002795810700000152
wherein W3 is used to represent a third impact weight, ZiElectrical parameter values, C, of the i-th transistor device of a test run chip for representing said chip product to be predictediThe number of the preset ith transistor devices adopted in the chip product to be predicted is used for representing.
In a specific implementation manner of the embodiment of the present invention, Ioff is taken as an example to be described, and the product of Ioff of the i-th semiconductor device and the number of devices, that is, Ioffi×CountiAs a third influence weight of the i-th semiconductor device. It should be noted that at least one or more semiconductor devices may be selected from all the devices to obtain a device set, and the ith semiconductor device may be selected from the device set.
Then, carrying out weight summation on the semiconductor devices in the device set to obtain a weight summation value:
Figure BDA0002795810700000153
then, the weight summation value is used as a correlation (correlation) parameter, and a yield loss prediction formula f (x) based on the semiconductor device is obtained through the function of the conventional yield management tool correlation fitting formula, wherein the yield after the yield loss is deducted is 1-f (x), namely the yield is 1-f (x)
Figure BDA0002795810700000154
Similarly, other device electrical parameters (such as saturation operating current, threshold voltage, etc.) may also be obtained in the above manner.
In the embodiment of the invention, if the chip product to be predicted comprises the preset transistor devices, the yield loss formula f (x) of the chip product to be predicted is obtained by fitting according to the historical yield of the chip product adopting each preset transistor device, and the third influence weight is determined according to the yield loss formula f (x), so that the actual condition of the transistor device in the current wafer factory can be fully considered, and the yield obtained by prediction is more accurate.
In another specific implementation manner of the embodiment of the present invention, after determining the third impact weight, the third impact weight may be introduced to improve yield prediction under the foregoing three situations (three situations shown as steps S32 to S34 in fig. 3):
specifically, the determining the first yield of the chip product to be predicted based on the product of the initial yield and the first influence weight may include: and adopting the product of the initial yield and the first influence weight and the third influence weight as the first yield of the chip product to be predicted.
Specifically, Yield 1 ═ W1 × W3 × Y;
yield 1 is used for representing the first Yield, W1 is used for representing the first influence weight, Y is used for representing the initial Yield of the chip product, and W3 is used for representing the third influence weight.
Determining a second yield of the chip product to be predicted according to a ratio of the initial yield to the second influence weight comprises: taking the ratio of the initial yield to the second influence weight as a first quotient; and taking the product of the first quotient and the third influence weight as a second yield of the chip product to be predicted.
Specifically, Yield 2 ═ W3 × Y ÷ W2;
yield 2 is used for representing the second Yield, W2 is used for representing the second influence weight, Y is used for representing the initial Yield of the chip product, and W3 is used for representing the third influence weight.
Determining a third yield of the chip product to be predicted according to the ratio of the first product to the second impact weight comprises: taking the quotient of the first product and the second impact weight as a second quotient value; and taking the product of the second quotient and the third influence weight as a third yield of the chip product to be predicted.
Specifically, Yield 3 ═ W1 × W3 × Y ÷ W2;
yield 3 is used for representing the third Yield, W1 is used for representing the first influence weight, W2 is used for representing the second influence weight, Y is used for representing the initial Yield of the chip product, and W3 is used for representing the third influence weight.
In the embodiment of the invention, the initial yield of the chip product to be predicted is calculated by adopting a preset yield prediction formula, and then the yield of the chip product to be predicted is determined according to the product of the initial yield and the first influence weight as well as the third influence weight and the ratio of the product of the initial yield and the third influence weight to the second influence weight.
Further, before determining an IP core and/or a new circuit design module adopted by a chip product to be predicted, the yield prediction method of the chip product may further include one or more of the following: determining that a design rule Detection (DRC) check result of the chip product to be predicted does not contain a violation item; and determining that the layout graph of the chip product to be predicted does not contain a graph in a preset layout hot spot graph library, wherein the preset layout hot spot graph library contains a known failure graph.
Specifically, when a new product is subjected to layout hot spot inspection, a tool (such as pattern matching EDA) can find that a bad pattern similar to the layout hot spot pattern gallery appears in the layout, for example, the problem of plug false opening (Via Open) may occur in the local special plug (Via) layout.
In the embodiment of the present invention, the preset Layout hot spot graph gallery includes known failure graphs, which should be avoided as much as possible, violating terms in the DRC check result should be eliminated as much as possible, or an appropriate tool (such as Layout Replace) is used to Replace the violating terms with equivalent electrical Layout graphs, and by performing the above processing before determining the IP core and/or the new circuit design module adopted by the chip product to be predicted, the effectiveness and yield of the product can be effectively improved, and the effectiveness and accuracy of the yield prediction of the product can also be improved.
In the embodiment of the invention, by determining the first influence weight of the target IP core adopted by the chip product to be predicted and/or the second influence weight of the target new circuit design module, the actual condition that the target IP core and/or the target new circuit design module are/is produced in the current wafer factory can be fully considered in the process of predicting the yield of the chip product to be predicted, so that the predicted yield is more accurate.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a yield prediction apparatus for a chip product according to an embodiment of the present invention. The yield prediction device of the chip product can comprise:
a design block determining module 41, configured to determine a target IP core and/or a target new circuit design module adopted by a chip product to be predicted, where the target new circuit design module occupies a preset area ratio on each chip product to be predicted;
the weight determining module 42 is configured to determine a first influence weight of the target IP core on the yield of the chip product to be predicted according to the historical shipment volume of the target IP core, and/or determine a second influence weight of the target new circuit design module on the yield of the chip product to be predicted according to a ratio of an area of the target new circuit design module to an area of the chip product to be predicted;
a yield prediction module 43, configured to predict a yield of the chip product to be predicted according to the first influence weight and/or the second influence weight.
For the principle, specific implementation and beneficial effects of the yield prediction apparatus for chip products, please refer to the related description of the yield prediction method for chip products, which is described above, and further description is omitted here.
Embodiments of the present invention also provide a storage medium having a computer program stored thereon, where the computer program is executed by a processor to perform the steps of the above method. The storage medium may be a computer-readable storage medium, and may include, for example, a non-volatile (non-volatile) or non-transitory (non-transitory) memory, and may further include an optical disc, a mechanical hard disk, a solid state hard disk, and the like.
The embodiment of the invention also provides a terminal, which comprises a memory and a processor, wherein the memory is stored with a computer program capable of running on the processor, and the processor executes the steps of the method when running the computer program. The terminal includes, but is not limited to, a mobile phone, a computer, a tablet computer and other terminal devices.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. A method for predicting yield of chip products is characterized by comprising the following steps:
determining a target IP core and/or a target new circuit design module adopted by a chip product to be predicted, wherein the target new circuit design module occupies a preset area proportion on each chip product to be predicted;
determining a first influence weight of the target IP core on the yield of the chip product to be predicted according to the historical shipment volume of the target IP core, and/or determining a second influence weight of the target new circuit design module on the yield of the chip product to be predicted according to the proportion of the area of the target new circuit design module in the area of the chip product to be predicted;
and predicting the yield of the chip product to be predicted according to the first influence weight and/or the second influence weight.
2. The method of claim 1, wherein the step of predicting the yield of the chip product comprises,
determining a first influence weight of the target IP core on the yield of the chip product to be predicted according to the historical shipment volume of the target IP core comprises the following steps:
when the target IP core comprises at least one type of IP core, acquiring the historical shipment volume of the chip product of each type of IP core;
for each class of IP core, determining the class of IP core according to the historical shipment volume of the chip product, and determining the IP weight value of the class of IP core based on the class of the IP core;
and determining a first influence weight in the chip product to be predicted based on the obtained at least one IP weight value.
3. The method of claim 2, wherein the step of predicting the yield of the chip product comprises,
for each class of IP core, determining the class of IP core according to the historical shipment volume of the chip product, and determining the IP weight value of the class of the IP core based on the class of the IP core comprises the following steps:
obtaining effective chip products of the IP cores of each category, wherein the effective chip products are the chip products of which the historical shipment volume is greater than or equal to a preset shipment threshold value;
determining the grade of the IP core of each category according to the total number of the effective chip products of the IP core of each category and the total number of the wafers of the effective chip products of the IP core of each category, and determining the IP weight value of the grade of the IP core of each category based on the grade.
4. The method of claim 2, wherein the formula for determining the first impact weight in the chip product to be predicted is expressed as:
Figure FDA0002795810690000021
where W1 denotes a first impact weight, xiIndicates the total number of IP cores of the ith class, w1iAn IP weight value of an IP core of the ith class is represented, and n represents the number of classes of the IP core.
5. The method of claim 1, wherein the target new circuit design modules comprise a plurality of classes of new circuit design modules, each class of new circuit design module having a circuit weight value;
determining a second influence weight in the chip product to be predicted according to the proportion of the area of the new circuit design module to the chip area by adopting the following formula:
Figure FDA0002795810690000022
wherein W2 is used to represent the second influence weight, yiFor indicating the proportion of the area of the ith new circuit design block to the chip area, w2iFor representing the circuit weight values of the ith new circuit design block.
6. The method of claim 1, wherein the target new circuit design modules comprise a plurality of classes of new circuit design modules, each class of new circuit design module having a circuit weight value;
the circuit weight value satisfies one or more of:
determining a circuit weight value of a new circuit design module in the chip product to be predicted based on a design range of a preset electrical parameter of the chip product to be predicted;
determining a circuit weight value of the new circuit design module of the category based on the size of the metal wire in the new circuit design module and the weighted value of the metal wire of the layer;
and determining a circuit weight value of the new circuit design module in the chip product to be predicted based on the area ratio of the new circuit design module in the chip product to be predicted.
7. The method of claim 5 or 6, wherein the new circuit design module comprises a logic circuit, an analog circuit and a pixel array capacitor circuit;
the circuit weight value of the analog circuit is greater than that of the logic circuit, and the circuit weight value of the logic circuit is greater than that of the pixel array capacitor circuit.
8. The method of claim 1, wherein before predicting the yield of the chip product to be predicted according to the first and/or second impact weights, the method further comprises:
calculating the initial yield of the chip product to be predicted by adopting a preset yield prediction formula;
predicting the yield of the chip product to be predicted according to the first influence weight comprises the following steps: determining a first yield of the chip product to be predicted according to the product of the initial yield and the first influence weight; predicting the yield of the chip product to be predicted according to the second influence weight comprises the following steps: determining a second yield of the chip product to be predicted according to the ratio of the initial yield to the second influence weight;
predicting the yield of the chip product to be predicted according to the first influence weight and the second influence weight comprises the following steps: and taking the product of the initial yield and the first influence weight as a first product, and taking the ratio of the first product to the second influence weight as a third yield of the chip product to be predicted.
9. The method of claim 8, wherein the predetermined yield prediction formula is selected from the group consisting of: bose einstein formula and Flop count yield prediction formula.
10. The method of claim 8, wherein before predicting the yield of the chip product to be predicted according to the first and/or second impact weights, the method further comprises:
determining a third influence weight under the condition that the chip product to be predicted contains a preset transistor device;
determining the first yield of the chip product to be predicted according to the product of the initial yield and the first influence weight comprises: taking the product of the initial yield and the first influence weight and the third influence weight as the first yield of the chip product to be predicted;
determining a second yield of the chip product to be predicted according to a ratio of the initial yield to the second influence weight comprises:
taking the ratio of the initial yield to the second influence weight as a first quotient;
taking the product of the first quotient and the third influence weight as a second yield of the chip product to be predicted;
determining a third yield of the chip product to be predicted according to the ratio of the first product to the second impact weight comprises:
taking the quotient of the first product and the second impact weight as a second quotient value;
and taking the product of the second quotient and the third influence weight as a third yield of the chip product to be predicted.
11. A storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to perform the steps of the yield prediction method of the chip product according to any one of claims 1 to 10.
12. A terminal comprising a memory and a processor, the memory having stored thereon a computer program operable on the processor, wherein the processor executes the computer program to perform the steps of the yield prediction method of a chip product according to any one of claims 1 to 10.
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