CN112601255B

CN112601255B - MAC frame transmitting method and device, PHY frame aggregation method and device

Info

Publication number: CN112601255B
Application number: CN202011491677.1A
Authority: CN
Inventors: 周博; 闫海停
Original assignee: Beijing Yinmu Microelectronics Technology Co ltd
Current assignee: Beijing Yinmu Microelectronics Technology Co ltd
Priority date: 2020-12-16
Filing date: 2020-12-16
Publication date: 2023-05-26
Anticipated expiration: 2040-12-16
Also published as: CN112601255A

Abstract

The invention discloses a method and a device for sending MAC frames and a method and a device for aggregating PHY frames, wherein the method comprises the following steps: generating a MAC frame according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet transmitting address, a frame number control, an Ethernet destination address, an Ethernet source address, and an IP packet which are sequentially arranged; and sending the generated MAC frame to a physical layer PHY. The PHY receives a plurality of MAC frames and analyzes the MAC frames; according to the analysis result, the plurality of MAC frames are aggregated into PHY frames in a preset PHY frame format, so that the problems of low transmission efficiency and high power consumption in the prior art are solved.

Description

MAC frame transmitting method and device, PHY frame aggregation method and device

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and apparatus for transmitting a MAC frame, and a method and apparatus for aggregating PHY frames.

Background

The wireless self-organizing network adopts a distributed technology, does not have management of a central control node, has stronger self-organizing property and mobility, and is simple to establish. There are a number of applications for 802.11 protocol based WIFI modules in wireless ad hoc network communication systems. The 802.11 protocol adopts a CSMA/CA access technology, and the access technology has the advantages of no need of complex time synchronization and control scheduling algorithm, and has the disadvantages of high protocol overhead and high power consumption. As shown in fig. 1, the mapping of the standard ethernet frame to the physical layer frame format requires the addition of a MAC header and a PLCP header, and the actual data carried is only the content in the IP payload.

To optimize the problem of large protocol overhead, the 802.11 standard introduced the following a-MPDU aggregation technique. An a-MPDU is a relatively simple form of aggregation, where multiple frames are aggregated together and then transmitted as a single aggregate frame. In the transmission flow without aggregation in fig. 1, the MAC layer provides the IP Payload with the MAC Header and the CRC, and then delivers the IP Payload to the PHY layer, and after the PHY layer adds the PLCP Header, each IP packet has its own PLCP Header.

In the transmission process shown in the MPDU aggregation of FIG. 2, each IP Payload has its own MAC Header and CRC, but they share one PLCP Header, so that the waste of air interface resources is reduced. These separate MAC frames are put together in the aggregation process so they are referred to as a-MPDU sub-frames at this stage. The receive address and transmit address of all subframes in the a-MPDU must be the same.

Defect one: the transmission efficiency is low:

the MPDU reliimiter format is shown in FIG. 3, where MPDUlength is the MAC frame length in the current A-MPDU subframe and CRC is the check bit of the MPDU reliimiter. Delimiter Signature is a 1 byte separator identification.

The MAC Header format is shown in fig. 4, where RA is a 6 byte ethernet receive address and TA is a 6 byte ethernet transmit address. Duration indicates the Duration of the frame and Sequence control contains Sequence number information for the frame. DA is a 6 byte Ethernet destination address and SA is a 6 byte Ethernet source address. Frame ctrl contains information such as protocol type.

The PLCP Header format is shown in fig. 5, where the Preamble is used for receiving gain control, frequency offset correction, and synchronization. Control Information stores decoding parameters required by a receiver such as code modulation.

In summary, each IP packet in the A-MPDU requires an addition of a MAC header and MPDU reliqueter for a total of 34 bytes. Especially when the IP packets of the subframes in the a-MPDU are short, the resource waste is serious. It can be calculated that when N ethernet frames are aggregated, the transmission efficiency Te is as follows:

when N is large and the IP payload (i) lengths are both IP payload, equation (one) may be approximated as:

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defect two: the power consumption is large:

as shown in fig. 1 or fig. 2, the receiving address of the data packet is included in the MAC header, and whether the PHY payload decoding is completed for the data packet is determined, so that the receiver does not have a sleep process. The data processing flow is shown in fig. 6.

Disclosure of Invention

The invention aims to provide a method and a device for transmitting MAC frames and a method and a device for aggregating PHY frames, and aims to solve the defects of low transmission efficiency and high power consumption in the prior art.

The invention provides a method for transmitting a Media Access Control (MAC) frame, which comprises the following steps:

generating a MAC frame according to a predetermined MAC frame format, wherein the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet transmitting address, a frame number control, an Ethernet destination address, an Ethernet source address, and an IP packet which are sequentially arranged;

and sending the generated MAC frame to a physical layer PHY.

Preferably, the length of the ethernet receiving address is 6 bytes, the length of the ethernet transmitting address is 6 bytes, the length of the frame number control is 1 byte, the length of the ethernet destination address is 6 bytes, the length of the ethernet source address is 6 bytes, and the length of the IP packet is 48-1502 bytes.

Preferably, the method is implemented by a general purpose processor.

The invention provides a physical layer PHY frame aggregation method, which comprises the following steps:

receiving a plurality of MAC frames and analyzing the MAC frames;

according to the analysis result, the plurality of MAC frames are aggregated into PHY frames in a preset PHY frame format, wherein the preset PHY frame format comprises the following steps: the physical layer convergence protocol PLCP header, a plurality of PHY loads and cyclic redundancy check bits in the middle of each PHY load which are connected in sequence, wherein the PLCP header specifically comprises: the random access preamble, the control information, the frame type, the protocol data unit PDU number, the length information of each PHY load, the Ethernet receiving address and the Ethernet transmitting address which are common to a plurality of PHY loads are sequentially connected, and each PHY load specifically comprises: frame number control, ethernet destination address, ethernet source address, and IP packets.

Preferably, receiving the plurality of MAC frames specifically includes:

receiving a plurality of MAC frames generated according to a predetermined MAC frame format, wherein the predetermined MAC frame format comprises: an ethernet receiving address, an ethernet transmitting address, a frame number control, an ethernet destination address, an ethernet source address, and an IP packet are arranged in this order.

Preferably, the method further comprises:

step 1, receiving the PHY frame through an air interface;

step 2, synchronizing the physical layer random access preamble of the PHY frame, judging whether the synchronization is successful, if yes, executing step 3, otherwise, executing step 1;

step 3, decoding PHY PLCP, judging whether decoding is successful, if so, executing step 4, otherwise, executing step 1;

step 4, judging whether the data packet is a self data packet according to the Ethernet receiving address obtained by PHY PLCP decoding, if yes, executing step 6, otherwise, determining the sleep time according to each PHY load length information obtained by PHY PLCP decoding, closing the radio frequency receiver and entering the sleep mode, and executing step 5;

step 5, judging whether the sleep time is up, if so, exiting the sleep mode, executing the step 1, otherwise, continuing to keep the sleep mode;

step 6; and (3) decoding the PHY load, judging whether the decoding is successful, reporting the PHY frame to a higher layer if the decoding is successful, and executing the step (1) if the decoding is not successful.

Preferably, the method is implemented by a vector digital signal processor DSP.

The embodiment of the invention also provides a device for sending the Media Access Control (MAC) frame, which comprises the following steps:

the generating module is configured to generate a MAC frame according to a predetermined MAC frame format, where the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet transmitting address, a frame number control, an Ethernet destination address, an Ethernet source address, and an IP packet which are sequentially arranged;

and the sending module is used for sending the generated MAC frame to a physical layer PHY.

The embodiment of the invention also provides a device for aggregating the PHY frames of the physical layer, which comprises the following steps:

the receiving module is used for receiving a plurality of MAC frames and analyzing the MAC frames;

the aggregation module is configured to aggregate the plurality of MAC frames into PHY frames in a predetermined PHY frame format according to the parsing result, where the predetermined PHY frame format includes: the physical layer convergence protocol PLCP header, a plurality of PHY loads and cyclic redundancy check bits in the middle of each PHY load which are connected in sequence, wherein the PLCP header specifically comprises: the random access preamble, the control information, the frame type, the protocol data unit PDU number, the length information of each PHY load, the Ethernet receiving address and the Ethernet transmitting address which are common to a plurality of PHY loads are sequentially connected, and each PHY load specifically comprises: frame number control, ethernet destination address, ethernet source address, and IP packets.

Preferably, the receiving module is specifically configured to:

a plurality of MAC frames are generated according to a predetermined MAC frame format, wherein the predetermined MAC frame format comprises: an ethernet receiving address, an ethernet transmitting address, a frame number control, an ethernet destination address, an ethernet source address, and an IP packet are arranged in this order.

Preferably, the apparatus further comprises:

an air interface module for receiving the PHY frame through an air interface;

the synchronous module is used for synchronizing the physical layer random access preamble of the PHY frame, judging whether the synchronization is successful or not, if yes, calling the decoding module, and if not, calling the air interface module;

the decoding module is used for decoding the PHY PLCP and judging whether the decoding is successful or not, if so, the processing module is called, and if not, the air interface module is called;

the processing module is used for judging whether the data packet is a data packet of the user or not according to the Ethernet receiving address obtained by PHY PLCP decoding, if yes, the decoding module is called, otherwise, the sleep time is determined according to the length information of each PHY load obtained by PHY PLCP decoding, the radio frequency receiver is closed to enter a sleep mode, and the sleep module is called;

the sleep module is used for judging whether the sleep time is up, if so, exiting the sleep mode, calling the air interface module, and if not, continuing to keep the sleep mode;

and the decoding module is used for decoding the PHY load, judging whether the decoding is successful, reporting the PHY frame to a high layer if the decoding is successful, and calling the air interface module if the decoding is not successful.

The embodiment of the invention also provides a device for sending the Media Access Control (MAC) frame, which comprises the following steps: the method comprises the steps of a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the computer program is executed by the processor to realize the Medium Access Control (MAC) frame transmitting method.

The embodiment of the invention also provides a device for aggregating the PHY frames of the physical layer, which comprises the following steps: the system comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, wherein the computer program realizes the steps of the physical layer PHY frame aggregation method when being executed by the processor.

The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores an information transmission implementation program, and the program realizes the steps of the Medium Access Control (MAC) frame transmission method when being executed by a processor.

The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores an information transmission implementation program, and the program realizes the steps of the physical layer PHY frame aggregation method when being executed by a processor.

By adopting the embodiment of the invention, the format of the MAC frame is changed, a new PHY frame aggregation method is provided, the transmission efficiency is improved, whether the data packet matches the local MAC address can be judged in advance, if not, the receiver is closed to enter a power saving mode, and the energy is saved.

The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a conventional PHY frame generation process and associated frame formats of the prior art;

fig. 2 is a schematic diagram of a prior art MPDU aggregation process and PHY frame format;

fig. 3 is a schematic diagram of a prior art MPDU relimeter format;

FIG. 4 is a prior art MAC Header format diagram;

fig. 5 is a schematic diagram of a PLCP Header format of the related art;

FIG. 6 is a flow chart of a conventional decoding data processing of the prior art;

FIG. 7 is a diagram of an efficient MAC frame format of an efficient frame aggregation method according to an embodiment of the invention;

FIG. 8 is a PHY aggregation process and PHY frame format schematic diagram of a method of efficient frame aggregation according to an embodiment of the invention;

FIG. 9 is a flow chart of a decoding data processing with power saving function for a method of efficient frame aggregation according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a PHY aggregation implementation of a method of efficient frame aggregation in accordance with an embodiment of the invention;

fig. 11 is a flowchart of a medium access control MAC frame transmission method according to an embodiment of the present invention;

FIG. 12 is a flow chart of a physical layer PHY frame aggregation method according to an embodiment of the invention;

FIG. 13 is a schematic diagram of a physical layer PHY frame aggregation device module according to an embodiment of the invention;

fig. 14 is a schematic diagram of a medium access control MAC frame transmission device according to an embodiment of the present invention;

fig. 15 is a schematic diagram of a medium access control MAC frame transmission apparatus according to an embodiment of the present invention;

fig. 16 is a schematic diagram of a physical layer PHY frame aggregation apparatus according to an embodiment of the invention.

Reference numerals illustrate:

1000: a generating module; 1020: a transmitting module; 2000: a receiving module; 2020: an aggregation module; 1510: a memory; 1520: a processor; 1610: a memory; 1620: a processor.

Detailed Description

The technical solutions of the present invention will be clearly and completely described in connection with the embodiments, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. Furthermore, the terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

Method embodiment one

According to an embodiment of the invention, a method for transmitting a Medium Access Control (MAC) frame is provided. Fig. 11 is a flowchart of a method for transmitting a MAC frame for medium access control according to an embodiment of the present invention, as shown in fig. 11, specifically including the following processes:

step 101, generating a MAC frame according to a predetermined MAC frame format, where the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet transmitting address, a frame number control, an Ethernet destination address, an Ethernet source address, and an IP packet which are sequentially arranged; wherein the length of the Ethernet receiving address is 6 bytes, the length of the Ethernet transmitting address is 6 bytes, the length of the frame number control is 1 byte, the length of the Ethernet destination address is 6 bytes, the length of the Ethernet source address is 6 bytes, and the length of the IP packet is 48-1502 bytes.

Step 102, the generated MAC frame is sent to the physical layer PHY.

Specifically, the MAC frame is generated according to a predetermined MAC frame format, and the predetermined MAC frame needs to delete the useless fields in fig. 4, including Protocol, type, subtype, toDS, fromDS, morefrag, retry, pwrmgmt, moredata, protectedframe, order, duration in frame rl, and reduce the length of the sequence control to one byte, as shown in table 1.

TABLE 1

The predetermined MAC frame format includes, as shown in fig. 7: sequentially arranged Ethernet receiving addresses,

An ethernet transmit address, frame number control, ethernet destination address, ethernet source address, and IP packet; the generated MAC frame is transmitted to the physical layer PHY, the ethernet reception address is 6 bytes in length, the ethernet transmission address is 6 bytes in length, the frame number control is 1 byte in length, the ethernet destination address is 6 bytes in length, the ethernet source address is 6 bytes in length, and the IP packet is 48-1502 bytes in length. The method is implemented by a general purpose processor.

In the embodiment of the invention, the method is realized by a general-purpose processor.

Method embodiment II

According to an embodiment of the invention, a physical layer PHY frame aggregation method is provided. Fig. 12 is a flowchart of a physical layer PHY frame aggregation method according to an embodiment of the present invention, and as shown in fig. 12, specifically includes the following processing:

step 201, receiving a plurality of MAC frames and parsing the MAC frames;

step 202, according to the parsing result, aggregating the plurality of MAC frames into PHY frames in a predetermined PHY frame format, where the predetermined PHY frame format includes: the physical layer convergence protocol PLCP header, a plurality of PHY loads and cyclic redundancy check bits in the middle of each PHY load which are connected in sequence, wherein the PLCP header specifically comprises: the random access preamble, the control information, the frame type, the protocol data unit PDU number, the length information of each PHY load, the Ethernet receiving address and the Ethernet transmitting address which are common to a plurality of PHY loads are sequentially connected, and each PHY load specifically comprises: frame number control, ethernet destination address, ethernet source address, and IP packets.

In the embodiment of the invention, the PHY receives a plurality of MAC frames and analyzes the MAC frames; according to the parsing result, the plurality of MAC frames are aggregated into PHY frames in a predetermined PHY frame format, as shown in fig. 8, wherein the predetermined PHY frame format includes: the physical layer convergence protocol PLCP header, a plurality of PHY loads and cyclic redundancy check bits in the middle of each PHY load which are connected in sequence, wherein the PLCP header specifically comprises: the random access preamble, the control information, the frame type, the protocol data unit PDU number, the length information of each PHY load, the Ethernet receiving address and the Ethernet transmitting address which are common to a plurality of PHY loads are sequentially connected, and each PHY load specifically comprises: frame number control, ethernet destination address, ethernet source address, and IP packets.

The receiving the plurality of MAC frames specifically includes:

In the PHY aggregation process, the PLCPheader extended contains common RA and DA, each MAC packet can be directly aggregated to the PHY layer, so that waste of air interface resources is further reduced, LEN1, LEN2 and the like are utilized for end-to-end delimitation, resources occupied by MPDUdelimiter are reduced, and the rate is improved.

It can be calculated that when N ethernet frames are aggregated, the transmission efficiency Te is as follows:

when N is large and IPpayload (i) is of length IPpayload, equation (three) may be approximated as:

the efficiency of equation (four) is significantly improved compared to equation (two), especially when IPpayload is smaller.

Based on the aggregate frame, the invention discloses a data processing flow with a power saving function as shown in fig. 9, whether the data packet matches the local MAC address is judged in advance, and if the data packet does not match, the receiver is closed to enter a power saving mode. The method comprises the following specific steps:

step 1, receiving PHY frames through an air interface;

step 3, performing the decoding of the PHYPLCP, judging whether the decoding is successful, if so, executing step 4, otherwise, executing step 1;

step 4, judging whether the data packet is a data packet of the user or not according to the Ethernet receiving address obtained by the PHYPLP, if yes, executing step 6, otherwise, determining the sleep time according to each PHY load length information obtained by the PHYPLP, closing the radio frequency receiver, and entering a sleep mode, and executing step 5;

The method is realized by a vector digital signal processor DSP.

The embodiment of the invention optimizes the MACframe frame structure of FIG. 1, removes useless fields, shortens the MACheader by the MAC frame, integrates the fields which are meaningless for the transmission of the self-organizing network system in FIG. 4, improves the transmission efficiency, and extracts the RA/TA/data packet length/frame type in the MACheader into the PHYPLCPheader to form FIG. 7 by detailing the fields in Table 1, thereby improving the frame efficiency of the MAC.

The MAC in fig. 2 is aggregated into the PHY aggregation of fig. 8, so that PHY frame efficiency is improved.

Based on the new PHY frame format in fig. 8, adding a power saving function to the data reception processing flow of fig. 6 forms fig. 9, so that power consumption is reduced.

In both the above two method embodiments, the CSMA/CA scheme is implemented using a scheme of vector DSP (DigitalSignalProcessing) plus a general ARM processor, as shown in fig. 10, where CSMA/CA is implemented by a PHY layer (physical layer) and a MAC layer (media access control) together. Wherein the application layer runs on the general processor 1, the MAC layer runs on the general processor 0, and the PHY layer runs on the vector DSP. The application layer and the MAC layer are interacted by Ethernet frames, and the MAC layer and the PHY are interacted by MAC frames.

The MAC frame of fig. 7 is generated at the MAC layer, and the PHY frame aggregation of fig. 8 and the data reception process with the power saving function of fig. 9 are completed at the PHY layer.

Device embodiment 1

According to an embodiment of the present invention, there is provided a medium access control MAC frame transmission apparatus, and fig. 13 is a schematic diagram of the medium access control MAC frame transmission apparatus according to the embodiment of the present invention, as shown in fig. 13, including:

the generating module 1000 is configured to generate a MAC frame according to a predetermined MAC frame format, where the predetermined MAC frame format includes: an Ethernet receiving address, an Ethernet transmitting address, a frame number control, an Ethernet destination address, an Ethernet source address, and an IP packet which are sequentially arranged; the length of the Ethernet receiving address is 6 bytes, the length of the Ethernet transmitting address is 6 bytes, the length of the frame number control is 1 byte, the length of the Ethernet destination address is 6 bytes, the length of the Ethernet source address is 6 bytes, and the length of the IP packet is 48-1502 bytes.

A transmitting module 1020, configured to transmit the generated MAC frame to the physical layer PHY.

The apparatus may be implemented by a general purpose processor.

Device example two

According to an embodiment of the present invention, there is provided a physical layer PHY frame aggregation apparatus, and fig. 14 is a schematic diagram of the physical layer PHY frame aggregation apparatus according to the embodiment of the present invention, as shown in fig. 14, including:

a receiving module 2000, configured to receive a plurality of MAC frames and parse the MAC frames; the accepting module 2000 specifically is configured to:

The aggregation module 2020 is configured to aggregate the plurality of MAC frames into PHY frames in a predetermined PHY frame format according to the parsing result, where the predetermined PHY frame format includes: the physical layer convergence protocol PLCP header, a plurality of PHY loads and cyclic redundancy check bits in the middle of each PHY load which are connected in sequence, wherein the PLCP header specifically comprises: the random access preamble, the control information, the frame type, the protocol data unit PDU number, the length information of each PHY load, the Ethernet receiving address and the Ethernet transmitting address which are common to a plurality of PHY loads are sequentially connected, and each PHY load specifically comprises: frame number control, ethernet destination address, ethernet source address, and IP packets.

The apparatus further comprises:

the air interface module is used for receiving the PHY frame through an air interface;

The embodiment of the present invention is an embodiment of a device corresponding to the embodiment of the method, and specific operations of each module may be understood by referring to descriptions of the embodiment of the method, which are not repeated herein.

Device example III

The embodiment of the invention provides a Medium Access Control (MAC) frame transmitting device, which comprises the following steps as shown in fig. 15: a memory 1510, a processor 1520, and a computer program stored on the memory 1510 and executable on the processor 1520, which when executed by the processor, performs the steps of the medium access control MAC frame transmission method as in the first method embodiment described above.

Device example IV

An embodiment of the present invention provides a physical layer PHY frame aggregation apparatus, as shown in fig. 16, including: while memory 1610, processor 1620 and a computer program stored on memory 1610 and executable on processor 1620, the computer program when executed by the processor performs the steps of the physical layer PHY frame aggregation method in method embodiment two described above.

Device example five

An embodiment of the present invention provides a computer readable storage medium, where a program for implementing information transfer is stored, and when the program is executed by the processor 1520, the steps of the medium access control MAC frame transmission method in the first embodiment of the above method are implemented.

Device example six

The embodiment of the invention provides a computer readable storage medium, on which an information transfer implementation program is stored, which when executed by a processor 1620 implements the steps of the physical layer PHY frame aggregation method in the second method embodiment.

The computer-readable storage medium of the present embodiment includes, but is not limited to: ROM, RAM, magnetic or optical disks, etc.

It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may alternatively be implemented in program code executable by computing devices, so that they may be stored in a memory device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps within them may be fabricated into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A medium access control, MAC, frame transmission method, comprising:

and sending the generated MAC frame to a physical layer PHY.

2. The method of claim 1, wherein the ethernet receive address is 6 bytes in length, the ethernet transmit address is 6 bytes in length, the frame number control is 1 byte in length, the ethernet destination address is 6 bytes in length, the ethernet source address is 6 bytes in length, and the IP packet is 48-1502 bytes in length.

3. The method of claim 1, wherein the method is implemented by a general purpose processor.

4. A method for aggregation of physical layer PHY frames, comprising:

receiving a plurality of MAC frames and analyzing the MAC frames;

5. The method of claim 4, wherein receiving the plurality of MAC frames comprises:

6. The method according to claim 4, wherein the method further comprises:

step 1, receiving the PHY frame through an air interface;

7. The method of claim 4, wherein the method is implemented by a vector digital signal processor DSP.

8. A medium access control, MAC, frame transmitting apparatus, comprising:

9. A physical layer PHY frame aggregation apparatus, comprising:

10. The apparatus of claim 9, wherein the receiving module is specifically configured to:

11. The apparatus of claim 9, wherein the apparatus further comprises:

an air interface module for receiving the PHY frame through an air interface;

12. A medium access control, MAC, frame transmitting apparatus, comprising: a memory, a processor and a computer program stored on the memory and executable on the processor, which when executed by the processor, performs the steps of the medium access control, MAC, frame transmission method as claimed in any one of claims 1 to 3.

13. A physical layer PHY frame aggregation apparatus, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, which when executed by the processor, performs the steps of the physical layer PHY frame aggregation method of any one of claims 4 to 7.

14. A computer-readable storage medium, in which a program for realizing information transfer is stored, which program, when executed by a processor, realizes the steps of the medium access control MAC frame transmission method as claimed in any one of claims 1 to 3.

15. A computer-readable storage medium, wherein a program for implementing information transfer is stored on the computer-readable storage medium, the program implementing the steps of the physical layer PHY frame aggregation method of any one of claims 4 to 7 when executed by a processor.