CN112600402B - IGBT induction heating melting power supply digital control system - Google Patents
IGBT induction heating melting power supply digital control system Download PDFInfo
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- CN112600402B CN112600402B CN202011411349.6A CN202011411349A CN112600402B CN 112600402 B CN112600402 B CN 112600402B CN 202011411349 A CN202011411349 A CN 202011411349A CN 112600402 B CN112600402 B CN 112600402B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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Abstract
The invention discloses a digital control system of an IGBT induction heating smelting power supply, which relates to the technical field of power supply control and solves the technical problem of poor equipment running performance caused by instability of a power supply control system; the power supply main control unit is arranged, the control steps of the power supply main control unit are elaborated, and the arrangement can carry out early warning detection on the fault of the power supply and is beneficial to improving the working efficiency and robustness of the power supply control system; the invention sets a starting subunit, which initializes the zone bit and the control panel when receiving the starting operation signal; setting a starting zone bit to be 1 and clearing a stopping zone bit; setting the starting lamp to be in a light-on state and setting the stopping lamp to be in a light-off state; setting the main contactor to be closed, and setting the FPGA control signal to be high; the setting of the starting subunit lays a foundation for the efficient operation of the invention; the PID subunit is arranged, and the arrangement is favorable for improving the stability and the efficiency of the operation of the invention.
Description
Technical Field
The invention belongs to the technical field of power supply control, and particularly relates to a digital control system for an IGBT induction heating smelting power supply.
Background
The IGBT induction heating power supply is widely applied to occasions such as metal heat treatment, quenching, annealing, diathermy, smelting, welding, hot sheathing, semiconductor material refining, plastic heat sealing, baking, purification and the like; the induction current generated under the action of the high-frequency magnetic field is utilized to cause the conductor to generate heat to heat. Compared with furnace type heating, combustion heating or electric heating wire heating, the induction heating has the advantages of obvious energy saving, non-contact, high speed, simple working procedure, easy realization of automation and the like.
However, the IGBT induction heating power supply has many disadvantages, such as easy damage of the power element IGBT, low power factor, poor reliability and continuous operation performance of the device, etc.; a large part of the above drawbacks can be avoided by a digital control system that optimizes the power supply; therefore, a digital control system for an IGBT induction heating melting power supply is needed.
Disclosure of Invention
In order to solve the problems existing in the scheme, the invention provides a digital control system of an IGBT induction heating melting power supply.
The purpose of the invention can be realized by the following technical scheme: the IGBT induction heating smelting power supply digital control system comprises a DSP core board and a control module;
the DSP core board is provided with a communication interface; the communication interface comprises a panel parameter interface, a touch screen communication interface, a DSP core board power supply interface, a logic switch control interface, a signal output interface, a thyristor control interface, a level conversion interface, an expansion reservation interface and an A/D conversion interface;
the control module comprises a power supply main control unit and sub-units, wherein the sub-units comprise a timing interruption control sub-unit, a PID sub-unit, a DAC sub-unit, a starting sub-unit, a stopping sub-unit, an emergency stopping sub-unit and an ECAP IGBT overcurrent interruption sub-unit.
Preferably, the panel parameter interface comprises at least one SPI interface and three I/0 interfaces; the touch screen communication interface comprises at least one SCI (serial communication interface), and the SCI is communicated with the touch screen through an RS232 circuit; the DSP core board power supply interface is a double-pin interface, and the DSP core board is connected with a 5V power supply through double pins; the logic switch control interface comprises 7I/0 interfaces, and the DSP core board controls starting, stopping, emergency stopping, mode selection, temperature switching and fault alarming through the logic switch control interface; the DSP core board outputs an alarm signal, a main contactor and auxiliary contactor closing signal and a start and stop button lamp signal through the signal output interface; the thyristor control interface comprises 5I/0 interfaces, and the DSP core board controls the power of the thyristor through the thyristor control interface and the serial D/A circuit; the level conversion interface comprises at least one CAP interface and 2I/0 interfaces; the expansion reserved interface comprises 10I/0 interfaces; the A/D conversion interface comprises a sampling ADC interface and a reserved ADC interface, the sampling ADC interface comprises 6 ADC interfaces, the reserved ADC interface comprises 5 ADC interfaces, and the sampling ADC interface samples bus current, load current, inversion voltage and inversion current through a sampling conditioning circuit.
Preferably, the control step of the power main control unit includes:
step S1: initializing functions and variables; function and variable initialization settings refer to table 1;
step S2: acquiring a reset state of the potentiometer; when the potentiometer is not reset, jumping to step S21, when the potentiometer is reset, proceeding to step S3;
step S201: setting the unset flag bit to be 1, performing unset alarm operation, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to the step S2;
step S3: clearing the unset zone bit and clearing the unset alarm operation;
step S4: a nixie tube display subunit;
step S5: the touch screen is communicated with the subunit;
step S6: acquiring the state of an emergency stop button; when the scram button is pressed, jumping to step S61, and when the scram button is not pressed, performing step S7;
step S61: setting the scram flag bit to 1, performing scram alarm, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to step S6; the emergency stop alarm comprises a buzzer alarm;
step S7: clearing the sudden stop flag bit;
step S8: the touch screen is communicated with the subunit;
step S9: acquiring an operation state; the operating state comprises a manual state and an automatic state; when the operation state is the automatic state, the process goes to step S91, and when the operation state is the manual state, the process goes to step S10;
step S91: clearing the manual zone bit, and setting the automatic zone bit to be 1; the display subunit is displayed through the nixie tube, the communication with the subunit is carried out through the touch screen, and the step S9 is skipped to;
step S10: acquiring the state of a starting button; when the start button is not pressed, the display subunit of the nixie tube is communicated with the subunit through the touch screen, and the step S9 is skipped; when the start button is pressed, the next step is carried out;
step S11: jumping to a starting subunit;
step S12: acquiring the state of a sweep frequency starting flag bit; when the sweep start flag bit is 1, jumping to step S15, otherwise outputting a small voltage through the DAC subunit, and switching to the phase-locked loop unit;
step S13: when the sweep frequency is successfully started, the next step is carried out; when the sweep frequency is failed to start, jumping to the step S23;
step S14: setting the output of the DAC subunit to be 0, and setting the sweep frequency starting flag bit to be 1;
step S15: when the potentiometer has a value, setting the switching signal of the FPGA phase-locked loop to be 1, and jumping to the step S17; when the potentiometer has no value, the next step is carried out;
step S16: clearing a switching signal of the FPGA phase-locked loop;
step S17: acquiring the state of a stop button; when the stop button is pressed, jumping to the stop subunit, communicating with the subunit through the touch screen, and jumping to step S2; when the stop button is not pressed, the next step is carried out;
step S18: displaying the subunit through a nixie tube;
step S19: acquiring the state of an emergency stop button; when the emergency stop button is pressed, jumping to the emergency stop subunit, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to step S23; when the emergency stop button is not pressed, the next step is carried out;
step S20: communicating with the subunit through the touch screen;
step S21: detecting faults; the fault detection is to perform protection detection on over-temperature, over-current and over-voltage of the induction heating power supply; when the fault is detected, jumping to a stopping subunit and carrying out the next step; when the failure detection does not detect a failure, the process proceeds to step S15;
step S22: jumping to a stopping subunit;
step S23: displaying the subunit through a nixie tube;
step S24: and communicating with the subunit through the touch screen, and jumping to step S23.
Preferably, the starting subunit initializes the flag bit and the control panel when receiving the start operation signal, and includes:
setting a starting zone bit to be 1 and clearing a stopping zone bit;
setting the starting lamp to be in a light-on state and setting the stopping lamp to be in a light-off state;
and setting the main contactor to be closed, and setting the FPGA control signal to be high.
Preferably, the stopping subunit, when receiving the power-off signal, operates the control panel and the flag bit by the digital quantity a, and includes:
step Z1: closing the PIE interrupt;
step Z2: acquiring a digital quantity a through a DAC subunit;
step Z3: when the digital quantity a satisfies a >10, assigning the digital quantity a to be a-10, inputting the digital quantity a after assignment to the DAC subunit, and jumping to step Z2; when the number a satisfies a is less than or equal to 10, the next step is carried out;
step Z4: setting the running lamp to be in a light-off state, and setting the stop lamp to be in a light-on state; setting the manual flag bit and the automatic flag bit to 0; setting the FPGA control signal to be low; setting the stop flag bit to 1 and the start flag bit to 0; disconnecting the main contactor;
step Z5: the PIE interrupt is turned on.
Preferably, the DAC subunit is configured to control the phase of the three-phase rectified start pulse, and includes:
step X1: setting the loading pin LD high;
step X2: the chip selection pin CS is put low;
step X3: encoding and outputting a digital quantity a;
step X4: the clock pin CLK is set low and ready to start a transition;
step X5: delaying for 10us, and outputting stable analog voltage;
step X6: the reload pin LD is set high.
Preferably, the PID subunit is used to improve the stability and efficiency of the system.
Preferably, the timed interrupt control subunit performs sampling analysis on power data, where the power data includes a bus voltage, a bus current, an inverter voltage, and an inverter current, and includes:
step C1: carrying out interrupt response, setting an interrupt flag bit to be 1, and reloading the timer;
step C2: acquiring a conversion state; when the conversion is over, the next step is carried out, otherwise, the step C2 is repeated;
step C3: reading sampling values of a given quantity and an output feedback quantity;
step C4: carrying out moving average filtering on the sampling values of the given quantity and the output feedback quantity;
step C5: when the load is in overcurrent or rectification overvoltage, setting the overcurrent/overvoltage flag bit to be 1, and finishing the analysis; when the load overcurrent and the rectification overvoltage are not both satisfied, the next step is carried out;
step C6: clearing the over-current/over-voltage flag bit;
step C7: obtaining the difference value between the given quantity and the output feedback quantity and marking the absolute value of the difference value as an analysis result;
step C8: judging whether the state is stopped or not according to the analysis result; when stopping, assigning the DAC subunit digital quantity a to 0, and jumping to step C10; when the operation is not stopped, the next step is carried out;
step C9: assigning the DAC subunit digital quantity a as a given quantity;
step C10: when the digital quantity a exceeds the limit value, setting the digital quantity a as the limit value; when the number a does not exceed the limit value, the next step is carried out;
step C11: acquiring a sweep frequency starting flag bit; when the sweep frequency starting flag bit is 1, the analysis is finished, and when the sweep frequency starting flag bit is 0, the next step is carried out;
step C12: the DAC subunit outputs the result.
Preferably, when the emergency stop subunit receives the emergency power-off signal, the emergency stop subunit operates the control panel and the flag bit, including:
step V1: closing the PIE interrupt;
step V2: acquiring a digital quantity a through a DAC subunit; when the digital quantity a is greater than 30, assigning the digital quantity a to be a-30, inputting the digital quantity a after assignment to the DAC subunit, and repeating the step Z2;
step V3: the output result of the DAC subunit is 0;
step V4: setting the running lamp to be in a light-off state, and setting the stop lamp to be in a light-on state; setting the FPGA control signal to be low; setting the stop flag bit to 1 and the start flag bit to 0; the main contactor is opened.
Preferably, when the ECAP IGBT overcurrent interruption subunit receives the overcurrent fault signal, the ECAP IGBT overcurrent interruption subunit communicates with the FPGA to control the inverter driving signal output by the FPGA, and sets the IGBT overcurrent fault flag bit to 1.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention is provided with a power supply main control unit and elaborates the control steps of the power supply main control unit in detail; the fault detection of the starting part is to detect whether the starting functional circuit is normal or not, and the fault detection after the operation is to perform protection detection on over-temperature, over-current and over-voltage of the induction heating power supply; if the sweep frequency is successfully started, sending a signal to the FPGA, and starting a phase-locked loop program to ensure that a power supply works stably; if the frequency sweep fails, cutting off the power supply, and displaying and alarming faults; the power supply main control unit can perform early warning detection on the fault of the power supply, and is beneficial to improving the working efficiency and robustness of the invention;
2. the invention sets a starting subunit, which initializes the zone bit and the control panel when receiving the starting operation signal; setting a starting zone bit to be 1 and clearing a stopping zone bit; setting the starting lamp to be in a light-on state and setting the stopping lamp to be in a light-off state; setting the main contactor to be closed, and setting the FPGA control signal to be high; the setting of the starting subunit lays a foundation for the efficient operation of the invention;
3. the PID subunit is arranged, and the arrangement of the PID subunit is beneficial to improving the working stability and efficiency of the invention.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a design block diagram of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the following embodiments, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the IGBT induction heating melting power supply digital control system includes a DSP core board and a control module;
the DSP core board is provided with a communication interface; the communication interface comprises a panel parameter interface, a touch screen communication interface, a DSP core board power supply interface, a logic switch control interface, a signal output interface, a thyristor control interface, a level conversion interface, an expansion reservation interface and an A/D conversion interface;
the control module comprises a power supply main control unit and sub-units, wherein the sub-units comprise a timing interruption control sub-unit, a PID sub-unit, a DAC sub-unit, a starting sub-unit, a stopping sub-unit, an emergency stopping sub-unit and an ECAP IGBT overcurrent interruption sub-unit.
Further, the panel parameter interface comprises at least one SPI interface and three I/0 interfaces; the touch screen communication interface comprises at least one SCI (serial communication interface), and the SCI is communicated with the touch screen through an RS232 circuit; the power supply interface of the DSP core board is a double-row pin interface, and the DSP core board is connected with the 5V power supply through double-row pins; the logic switch control interface comprises 7I/0 interfaces, and the DSP core board controls starting, stopping, emergency stopping, mode selection, temperature switching and fault alarming through the logic switch control interface; the signal output interface comprises 5I/0 interfaces, and the DSP core board outputs an alarm signal, a main contactor and auxiliary contactor closing signal and a start and stop button lamp signal through the signal output interface; the thyristor control interface comprises 5I/0 interfaces, and the DSP core board controls the power of the thyristor through the thyristor control interface and the serial D/A circuit; the level conversion interface comprises at least one CAP interface and 2I/0 interfaces; the expansion reserved interface comprises 10I/0 interfaces; the A/D conversion interface comprises a sampling ADC interface and a reserved ADC interface, the sampling ADC interface comprises 6 ADC interfaces, the reserved ADC interface comprises 5 ADC interfaces, and the sampling ADC interface samples bus current, load current, inversion voltage and inversion current through a sampling conditioning circuit.
Further, the control step of the power main control unit includes:
step S1: initializing functions and variables; function and variable initialization settings refer to table 1;
step S2: acquiring a reset state of the potentiometer; when the potentiometer is not reset, jumping to step S21, when the potentiometer is reset, proceeding to step S3;
step S201: setting the unset flag bit to be 1, performing unset alarm operation, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to the step S2;
step S3: clearing the unset zone bit and clearing the unset alarm operation;
step S4: a nixie tube display subunit;
step S5: the touch screen is communicated with the subunit;
step S6: acquiring the state of an emergency stop button; when the scram button is pressed, jumping to step S61, and when the scram button is not pressed, performing step S7;
step S61: setting the scram flag bit to 1, performing scram alarm, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to step S6; the emergency stop alarm comprises a buzzer alarm;
step S7: clearing the sudden stop flag bit;
step S8: the touch screen is communicated with the subunit;
step S9: acquiring an operation state; the operation state comprises a manual state and an automatic state; when the operation state is the automatic state, the process goes to step S91, and when the operation state is the manual state, the process goes to step S10;
step S91: clearing the manual zone bit, and setting the automatic zone bit to be 1; the display subunit is displayed through the nixie tube, the communication with the subunit is carried out through the touch screen, and the step S9 is skipped to;
step S10: acquiring the state of a starting button; when the start button is not pressed, the display subunit of the nixie tube is communicated with the subunit through the touch screen, and the step S9 is skipped; when the start button is pressed, the next step is carried out;
step S11: jumping to a starting subunit;
step S12: acquiring the state of a sweep frequency starting flag bit; when the sweep start flag bit is 1, jumping to step S15, otherwise outputting a small voltage through the DAC subunit, and switching to the phase-locked loop unit;
step S13: when the sweep frequency is successfully started, the next step is carried out; when the sweep frequency is failed to start, jumping to the step S23;
step S14: setting the output of the DAC subunit to be 0, and setting the sweep frequency starting flag bit to be 1;
step S15: when the potentiometer has a value, setting the switching signal of the FPGA phase-locked loop to be 1, and jumping to the step S17; when the potentiometer has no value, the next step is carried out;
step S16: clearing a switching signal of the FPGA phase-locked loop;
step S17: acquiring the state of a stop button; when the stop button is pressed, jumping to the stop subunit, communicating with the subunit through the touch screen, and jumping to step S2; when the stop button is not pressed, the next step is carried out;
step S18: displaying the subunit through a nixie tube;
step S19: acquiring the state of an emergency stop button; when the emergency stop button is pressed, jumping to the emergency stop subunit, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to step S23; when the emergency stop button is not pressed, the next step is carried out;
step S20: communicating with the subunit through the touch screen;
step S21: detecting faults; the fault detection is to carry out protection detection on the over-temperature, over-current and over-voltage of the induction heating power supply; when the fault is detected, jumping to a stopping subunit and carrying out the next step; when the failure detection does not detect a failure, the process proceeds to step S15;
step S22: jumping to a stopping subunit;
step S23: displaying the subunit through a nixie tube;
step S24: and communicating with the subunit through the touch screen, and jumping to step S23.
Further, the starting subunit initializes the flag bit and the control panel when receiving the start operation signal, including:
setting a starting zone bit to be 1 and clearing a stopping zone bit;
setting the starting lamp to be in a light-on state and setting the stopping lamp to be in a light-off state;
and setting the main contactor to be closed, and setting the FPGA control signal to be high.
Further, the stop subunit operates the control panel and the flag bit by the digital quantity a when receiving the power-off signal, and includes:
step Z1: closing the PIE interrupt;
step Z2: acquiring a digital quantity a through a DAC subunit;
step Z3: when the digital quantity a satisfies a >10, assigning the digital quantity a to be a-10, inputting the digital quantity a after assignment to the DAC subunit, and jumping to step Z2; when the number a satisfies a is less than or equal to 10, the next step is carried out;
step Z4: setting the running lamp to be in a light-off state, and setting the stop lamp to be in a light-on state; setting the manual flag bit and the automatic flag bit to 0; setting the FPGA control signal to be low; setting the stop flag bit to 1 and the start flag bit to 0; disconnecting the main contactor;
step Z5: the PIE interrupt is turned on.
Further, the DAC subunit is configured to control the phase of the three-phase rectified outgoing pulse, and includes:
step X1: setting the loading pin LD high;
step X2: the chip selection pin CS is put low;
step X3: encoding and outputting a digital quantity a;
step X4: the clock pin CLK is set low and ready to start a transition;
step X5: delaying for 10us, and outputting stable analog voltage;
step X6: the reload pin LD is set high.
Further, the PID subunit is used to improve the stability and efficiency of the system.
Further, the timed interruption control subunit performs sampling analysis on the power data, where the power data includes bus voltage, bus current, inversion voltage and inversion current, and includes:
step C1: carrying out interrupt response, setting an interrupt flag bit to be 1, and reloading the timer;
step C2: acquiring a conversion state; when the conversion is over, the next step is carried out, otherwise, the step C2 is repeated;
step C3: reading sampling values of a given quantity and an output feedback quantity;
step C4: carrying out moving average filtering on the sampling values of the given quantity and the output feedback quantity;
step C5: when the load is in overcurrent or rectification overvoltage, setting the overcurrent/overvoltage flag bit to be 1, and finishing the analysis; when the load overcurrent and the rectification overvoltage are not both satisfied, the next step is carried out;
step C6: clearing the over-current/over-voltage flag bit;
step C7: obtaining the difference value between the given quantity and the output feedback quantity and marking the absolute value of the difference value as an analysis result;
step C8: judging whether the state is stopped or not according to the analysis result; when stopping, assigning the DAC subunit digital quantity a to 0, and jumping to step C10; when the operation is not stopped, the next step is carried out;
step C9: assigning the DAC subunit digital quantity a as a given quantity;
step C10: when the digital quantity a exceeds the limit value, setting the digital quantity a as the limit value; when the number a does not exceed the limit value, the next step is carried out;
step C11: acquiring a sweep frequency starting flag bit; when the sweep frequency starting flag bit is 1, the analysis is finished, and when the sweep frequency starting flag bit is 0, the next step is carried out;
step C12: the DAC subunit outputs the result.
Further, when the scram subunit receives the emergency power-off signal, the control panel and the flag bit are operated, including:
step V1: closing the PIE interrupt;
step V2: acquiring a digital quantity a through a DAC subunit; when the digital quantity a is greater than 30, assigning the digital quantity a to be a-30, inputting the digital quantity a after assignment to the DAC subunit, and repeating the step Z2;
step V3: the output result of the DAC subunit is 0;
step V4: setting the running lamp to be in a light-off state, and setting the stop lamp to be in a light-on state; setting the FPGA control signal to be low; setting the stop flag bit to 1 and the start flag bit to 0; the main contactor is opened.
Further, when the ECAP IGBT overcurrent interruption subunit receives the overcurrent fault signal, the ECAP IGBT overcurrent interruption subunit communicates with the FPGA to control an inversion driving signal output by the FPGA, and the IGBT overcurrent fault flag bit is set to be 1.
Further, the unset alarm operation includes: the fault lamp is on, the buzzer sounds and the touch screen displays the alarm content; the alarm content is that the potentiometer is not reset.
Table 1 function and variable initialization setting table
TABLE 2 flag bit operation reference table
The above formulas are all calculated by removing dimensions and taking values thereof, the formula is one closest to the real situation obtained by collecting a large amount of data and performing software simulation, and the preset parameters in the formula are set by the technical personnel in the field according to the actual situation.
The working principle of the invention is as follows:
step S1: initializing functions and variables;
step S2: acquiring a reset state of the potentiometer; when the potentiometer is not reset, jumping to step S21, when the potentiometer is reset, proceeding to step S3;
step S201: setting the unset flag bit to be 1, performing unset alarm operation, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to the step S2;
step S3: clearing the unset zone bit and clearing the unset alarm operation;
step S4: a nixie tube display subunit;
step S5: the touch screen is communicated with the subunit;
step S6: acquiring the state of an emergency stop button; when the scram button is pressed, jumping to step S61, and when the scram button is not pressed, performing step S7;
step S61: setting the scram flag bit to 1, performing scram alarm, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to step S6; the emergency stop alarm comprises a buzzer alarm;
step S7: clearing the sudden stop flag bit;
step S8: the touch screen is communicated with the subunit;
step S9: acquiring an operation state; the operating state comprises a manual state and an automatic state; when the operation state is the automatic state, the process goes to step S91, and when the operation state is the manual state, the process goes to step S10;
step S91: clearing the manual zone bit, and setting the automatic zone bit to be 1; the display subunit is displayed through the nixie tube, the communication with the subunit is carried out through the touch screen, and the step S9 is skipped to;
step S10: acquiring the state of a starting button; when the start button is not pressed, the display subunit of the nixie tube is communicated with the subunit through the touch screen, and the step S9 is skipped; when the start button is pressed, the next step is carried out;
step S11: jumping to a starting subunit;
step S12: acquiring the state of a sweep frequency starting flag bit; when the sweep start flag bit is 1, jumping to step S15, otherwise outputting a small voltage through the DAC subunit, and switching to the phase-locked loop unit;
step S13: when the sweep frequency is successfully started, the next step is carried out; when the sweep frequency is failed to start, jumping to the step S23;
step S14: setting the output of the DAC subunit to be 0, and setting the sweep frequency starting flag bit to be 1;
step S15: when the potentiometer has a value, setting the switching signal of the FPGA phase-locked loop to be 1, and jumping to the step S17; when the potentiometer has no value, the next step is carried out;
step S16: clearing a switching signal of the FPGA phase-locked loop;
step S17: acquiring the state of a stop button; when the stop button is pressed, jumping to the stop subunit, communicating with the subunit through the touch screen, and jumping to step S2; when the stop button is not pressed, the next step is carried out;
step S18: displaying the subunit through a nixie tube;
step S19: acquiring the state of an emergency stop button; when the emergency stop button is pressed, jumping to the emergency stop subunit, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to step S23; when the emergency stop button is not pressed, the next step is carried out;
step S20: communicating with the subunit through the touch screen;
step S21: detecting faults; the fault detection is to perform protection detection on over-temperature, over-current and over-voltage of the induction heating power supply; when the fault is detected, jumping to a stopping subunit and carrying out the next step; when the failure detection does not detect a failure, the process proceeds to step S15;
step S22: jumping to a stopping subunit;
step S23: displaying the subunit through a nixie tube;
step S24: and communicating with the subunit through the touch screen, and jumping to step S23.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is merely exemplary and illustrative of the present invention and various modifications, additions and substitutions may be made by those skilled in the art to the specific embodiments described without departing from the scope of the invention as defined in the following claims.
Claims (8)
- The IGBT induction heating smelting power supply digital control system is characterized by comprising a DSP core board and a control module;the DSP core board is provided with a communication interface; the communication interface comprises a panel parameter interface, a touch screen communication interface, a DSP core board power supply interface, a logic switch control interface, a signal output interface, a thyristor control interface, a level conversion interface, an expansion reservation interface and an A/D conversion interface;the control module comprises a power supply main control unit and sub-units, wherein the sub-units comprise a timing interruption control sub-unit, a PID sub-unit, a DAC sub-unit, a starting sub-unit, a stopping sub-unit, an emergency stopping sub-unit and an ECAP IGBT overcurrent interruption sub-unit;the control step of the power main control unit comprises the following steps:step S1: initializing functions and variables;step S2: acquiring a reset state of the potentiometer; when the potentiometer is not reset, jumping to step S21, when the potentiometer is reset, proceeding to step S3;step S201: setting the unset flag bit to be 1, performing unset alarm operation, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to the step S2;step S3: clearing the unset zone bit and clearing the unset alarm operation;step S4: a nixie tube display subunit;step S5: the touch screen is communicated with the subunit;step S6: acquiring the state of an emergency stop button; when the scram button is pressed, jumping to step S61, and when the scram button is not pressed, performing step S7;step S61: setting the scram flag bit to 1, performing scram alarm, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to step S6; the emergency stop alarm comprises a buzzer alarm;step S7: clearing the sudden stop flag bit;step S8: the touch screen is communicated with the subunit;step S9: acquiring an operation state; the operating state comprises a manual state and an automatic state; when the operation state is the automatic state, the process goes to step S91, and when the operation state is the manual state, the process goes to step S10;step S91: clearing the manual zone bit, and setting the automatic zone bit to be 1; the display subunit is displayed through the nixie tube, the communication with the subunit is carried out through the touch screen, and the step S9 is skipped to;step S10: acquiring the state of a starting button; when the start button is not pressed, the display subunit of the nixie tube is communicated with the subunit through the touch screen, and the step S9 is skipped; when the start button is pressed, the next step is carried out;step S11: jumping to a starting subunit;step S12: acquiring the state of a sweep frequency starting flag bit; when the sweep start flag bit is 1, jumping to step S15, otherwise outputting a small voltage through the DAC subunit, and switching to the phase-locked loop unit;step S13: when the sweep frequency is successfully started, the next step is carried out; when the sweep frequency is failed to start, jumping to the step S23;step S14: setting the output of the DAC subunit to be 0, and setting the sweep frequency starting flag bit to be 1;step S15: when the potentiometer has a value, setting the switching signal of the FPGA phase-locked loop to be 1, and jumping to the step S17; when the potentiometer has no value, the next step is carried out;step S16: clearing a switching signal of the FPGA phase-locked loop;step S17: acquiring the state of a stop button; when the stop button is pressed, jumping to the stop subunit, communicating with the subunit through the touch screen, and jumping to step S2; when the stop button is not pressed, the next step is carried out;step S18: displaying the subunit through a nixie tube;step S19: acquiring the state of an emergency stop button; when the emergency stop button is pressed, jumping to the emergency stop subunit, displaying the subunit through a nixie tube, communicating with the subunit through a touch screen, and jumping to step S23; when the emergency stop button is not pressed, the next step is carried out;step S20: communicating with the subunit through the touch screen;step S21: detecting faults; the fault detection is to perform protection detection on over-temperature, over-current and over-voltage of the induction heating power supply; when the fault is detected, jumping to a stopping subunit and carrying out the next step; when the failure detection does not detect a failure, the process proceeds to step S15;step S22: jumping to a stopping subunit;step S23: displaying the subunit through a nixie tube;step S24: and communicating with the subunit through the touch screen, and jumping to step S23.
- 2. The IGBT induction heating melting power supply digital control system of claim 1, wherein the panel parameter interfaces include at least one SPI interface and three I/0 interfaces; the touch screen communication interface comprises at least one SCI interface; the DSP core board power supply interface is a double-pin interface, and the DSP core board is connected with a 5V power supply through double pins; the logic switch control interface comprises 7I/0 interfaces; the signal output interface comprises 5I/0 interfaces; the thyristor control interface comprises 5I/0 interfaces; the level conversion interface comprises at least one CAP interface and 2I/0 interfaces; the expansion reserved interface comprises 10I/0 interfaces; the A/D conversion interface comprises a sampling ADC interface and a reserved ADC interface, the sampling ADC interface comprises 6 ADC interfaces, the reserved ADC interface comprises 5 ADC interfaces, and the sampling ADC interface samples bus current, load current, inversion voltage and inversion current through a sampling conditioning circuit.
- 3. The IGBT induction heating melting power supply digital control system of claim 1, wherein the start subunit, upon receiving a start operation signal, initializes a flag and a control panel, comprising:setting a starting zone bit to be 1 and clearing a stopping zone bit;setting the starting lamp to be in a light-on state and setting the stopping lamp to be in a light-off state;and setting the main contactor to be closed, and setting the FPGA control signal to be high.
- 4. The IGBT induction heating melting power supply digital control system of claim 1, wherein the stop subunit operates the control panel and flag bit by a digital quantity a upon receiving a power-off signal, comprising:step Z1: closing the PIE interrupt;step Z2: acquiring a digital quantity a through a DAC subunit;step Z3: when the digital quantity a satisfies a >10, assigning the digital quantity a to be a-10, inputting the digital quantity a after assignment to the DAC subunit, and jumping to step Z2; when the number a satisfies a is less than or equal to 10, the next step is carried out;step Z4: setting the running lamp to be in a light-off state, and setting the stop lamp to be in a light-on state; setting the manual flag bit and the automatic flag bit to 0; setting the FPGA control signal to be low; setting the stop flag bit to 1 and the start flag bit to 0; disconnecting the main contactor;step Z5: the PIE interrupt is turned on.
- 5. The IGBT induction heating melting power supply digital control system of claim 1, wherein the DAC subunit is configured to control a three-phase rectified outgoing pulse phase, comprising:step X1: setting the loading pin LD high;step X2: the chip selection pin CS is put low;step X3: encoding and outputting a digital quantity a;step X4: the clock pin CLK is set low and ready to start a transition;step X5: delaying for 10us, and outputting stable analog voltage;step X6: the reload pin LD is set high.
- 6. The IGBT induction heating melting power supply digital control system of claim 1, wherein the timed interrupt control subunit performs sampling analysis on power data, the power data including bus voltage, bus current, inverter voltage, and inverter current, comprising:step C1: carrying out interrupt response, setting an interrupt flag bit to be 1, and reloading the timer;step C2: acquiring a conversion state; when the conversion is over, the next step is carried out, otherwise, the step C2 is repeated;step C3: reading sampling values of a given quantity and an output feedback quantity;step C4: carrying out moving average filtering on the sampling values of the given quantity and the output feedback quantity;step C5: when the load is in overcurrent or rectification overvoltage, setting the overcurrent/overvoltage flag bit to be 1, and finishing the analysis; when the load overcurrent and the rectification overvoltage are not both satisfied, the next step is carried out;step C6: clearing the over-current/over-voltage flag bit;step C7: obtaining the difference value between the given quantity and the output feedback quantity and marking the absolute value of the difference value as an analysis result;step C8: judging whether the state is stopped or not according to the analysis result; when stopping, assigning the DAC subunit digital quantity a to 0, and jumping to step C10; when the operation is not stopped, the next step is carried out;step C9: assigning the DAC subunit digital quantity a as a given quantity;step C10: when the digital quantity a exceeds the limit value, setting the digital quantity a as the limit value; when the number a does not exceed the limit value, the next step is carried out;step C11: acquiring a sweep frequency starting flag bit; when the sweep frequency starting flag bit is 1, the analysis is finished, and when the sweep frequency starting flag bit is 0, the next step is carried out;step C12: the DAC subunit outputs the result.
- 7. The IGBT induction heating melting power supply digital control system of claim 1, wherein the scram subunit operates the control panel and flag bits upon receiving an emergency power off signal, comprising:step V1: closing the PIE interrupt;step V2: acquiring a digital quantity a through a DAC subunit; when the digital quantity a is greater than 30, assigning the digital quantity a to be a-30, inputting the digital quantity a after assignment to the DAC subunit, and repeating the step Z2;step V3: the output result of the DAC subunit is 0;step V4: setting the running lamp to be in a light-off state, and setting the stop lamp to be in a light-on state; setting the FPGA control signal to be low; setting the stop flag bit to 1 and the start flag bit to 0; the main contactor is opened.
- 8. The IGBT induction heating melting power supply digital control system of claim 1, wherein the ECAP IGBT overcurrent interruption subunit controls an inversion driving signal output by the FPGA by communicating with the FPGA when receiving the overcurrent fault signal, and sets an IGBT overcurrent fault flag bit to 1.
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| CN104244479B (en) * | 2014-10-10 | 2016-05-04 | 北京金风科创风电设备有限公司 | Flexible induction heating power supply for assembling and disassembling fan bearing and control method thereof |
| CN204217148U (en) * | 2014-11-20 | 2015-03-18 | 郑州科创电子有限公司 | A kind of novel intelligent IGBT induction heating power |
| CN105472803B (en) * | 2015-12-11 | 2018-10-16 | 洛阳理工学院 | Digital parallel induction heating power supply dual-DSP + FPGA system structure and method |
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