CN112599166B - High reliability programmable replica bit line clocking system for high speed SRAM - Google Patents

High reliability programmable replica bit line clocking system for high speed SRAM Download PDF

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CN112599166B
CN112599166B CN202011519716.4A CN202011519716A CN112599166B CN 112599166 B CN112599166 B CN 112599166B CN 202011519716 A CN202011519716 A CN 202011519716A CN 112599166 B CN112599166 B CN 112599166B
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gate
word line
signal
inverter
replica bit
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CN112599166A (en
Inventor
胡春艳
陆时进
陈雷
李建成
马浩
刘琳
任荣康
刘晨静
赵佳
刘劭璠
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

The invention discloses a high-reliability programmable replica bit line clock control system for a high-speed SRAM, comprising: a clock control circuit for generating a word line strobe signal SWL according to an external read word line control signal RWL, and generating a sense amplifier enable signal SAE according to a replica bit line potential RBL; the programmable replica bit line is used for cooperatively controlling a pre-charge tube and a discharge unit in the programmable replica bit line according to a word line strobe signal SWL and outputting a real-time replica bit line potential RBL; and a memory cell array for performing a read operation according to the sense amplifier enable signal SAE. The invention solves the problem of the conventional replica bit line control circuit, eliminates unnecessary power loss and abnormal read control time sequence caused by special read word line input conditions, greatly improves the operation reliability of the programmable replica bit line structure, and reduces the power consumption overhead under each working condition.

Description

High reliability programmable replica bit line clocking system for high speed SRAM
Technical Field
The invention belongs to the technical field of digital integrated circuit design, and particularly relates to a high-reliability programmable replica bit line clock control system for a high-speed SRAM.
Background
The bit line copying technology is an important technology for realizing accurate read-write time sequence control of the high-speed SRAM, a row of copying units and discharging units are added at the edge of the SRAM memory cell array, and the discharging units are used for discharging to simulate the read operation discharging process of the memory cell array, so that the effects of accurately controlling the bit line precharge of the memory cell array and the starting of a sense amplifier are achieved.
The programmable replica bit line technology discharges the replica bit line by programming and selecting different discharge paths, so that the discharge current of the replica bit line can be flexibly controlled under different working environments, and the highest reading speed can be realized by searching the optimal starting time of the sense amplifier in a configurable range.
In programmable replica bit line structures, read word lines are typically employed as the word line on and bit line precharge control terminals for the discharge cells. If the read word line is a level signal, the precharge is turned off each time the read word line is active, the discharge cell will continue to discharge until the read word line is inactive, closing the discharge tube and opening the precharge tube, precharging the bit line to a high level, which can create unnecessary power consumption overhead. If the read word line is a pulse signal, the read word line must ensure a sufficient pulse width to ensure that the replica bit line is fully discharged to the sense amplifier enable on in all programming ranges, otherwise, under the slowest discharge condition, the problem of read timing error caused by insufficient discharge of the read enable is generated. For a reliable programmable replica bit line structure, even when the read word line pulse width is satisfied under the slowest discharge condition, unnecessary power consumption loss still occurs under the corresponding fastest discharge condition, and therefore, how to reduce the unnecessary power consumption loss is one of the technical problems to be solved in the art.
The programmable replica bit line structure may cause erroneous read timing in practical applications. For example, in a circuit of a high-speed SRAM, especially a 4-time rate synchronous SRAM, a word line pulse is used to trigger a read operation, the read word line pulse is obtained by decoding an address pulse, the pulse width is very easy to be narrowed due to inconsistent address pulse signal delay, and the problem of unstable word line pulse width is uncontrollable and can change along with the change of environment, so that the problem of error of read time sequence caused by unstable read word line pulse width is one of technical problems to be solved in the application field.
Disclosure of Invention
The technical solution of the invention is as follows: the high-reliability programmable replica bit line clock control system for the high-speed SRAM overcomes the defects of a conventional replica bit line control circuit, eliminates unnecessary power loss and read control time sequence abnormality caused under special read word line input conditions, greatly improves the operation reliability of the programmable replica bit line structure and reduces the power consumption expense under each working condition.
In order to solve the above technical problems, the present invention discloses a highly reliable programmable replica bit line clock control system for a high-speed SRAM, comprising: a clock control circuit, a programmable replica bit line, and a memory cell array;
The clock control circuit is used for receiving an external read word line control signal RWL and generating a word line gating signal SWL according to the external read word line control signal RWL; and receiving a replica bit line potential RBL output by the programmable replica bit line, and generating a sense amplifier enable signal SAE according to the replica bit line potential RBL; wherein, when the external read word line control signal RWL is inactive, a word line strobe signal SWL of low level is generated; when the external read word line control signal RWL is changed from inactive to active, a word line strobe signal SWL of a high level is generated;
the programmable replica bit line is used for receiving a word line gating signal SWL output by the clock control circuit and cooperatively controlling a pre-charge tube and a discharge unit in the programmable replica bit line according to the word line gating signal SWL; and outputting a real-time replica bit line potential RBL; when the received word line strobe signal SWL is at a low level, the discharge unit is controlled to stop discharging, and the precharge tube is controlled to precharge the discharge unit until the replica bit line potential RBL meets a preset potential; when the received word line strobe signal SWL is at a high level, the pre-charge tube is controlled to be closed, and the discharging unit is controlled to discharge until the replica bit line potential RBL output by the programmable replica bit line meets a preset potential;
And the memory cell array is used for performing read operation according to the sense amplifier enable signal SAE output by the clock control circuit.
In the above-described highly reliable programmable replica bit line clocking system for high speed SRAM, the clocking circuit comprises: an edge detection circuit, a precharge recovery circuit and a feedback control logic circuit;
the edge detection circuit is used for receiving an external read word line control signal RWL, detecting an effective jump edge of the external read word line control signal RWL and outputting a pulse signal REN;
the precharge recovery circuit is used for receiving the pulse signal REN output by the edge detection circuit and the precharge enable feedback signal PCHRGEN output by the feedback control logic circuit and generating a word line strobe signal SWL;
the feedback control logic circuit is used for receiving the copy bit line potential RBL output by the programmable copy bit line and the word line strobe signal SWL output by the precharge recovery circuit; generating a sense amplifier enable signal SAE according to the replica bit line potential RBL, and outputting the sense amplifier enable signal SAE to the memory cell array; the precharge enable feedback signal PCHRGEN is generated according to the sense amplifier enable signal SAE and the word line gate signal SWL, and is output to the precharge recovery circuit.
In the above-described highly reliable programmable replica bit line clocking system for high speed SRAM, an edge detection circuit comprises: a first inverter and a first or gate;
the first inverter is used for receiving an external read word line control signal RWL and obtaining a delayed RWL inverse signal; the output end of the first inverter circuit is connected with the second input end of the first OR gate;
a first OR gate for performing OR operation on the external read word line control signal RWL and the delayed RWL inverse signal, and generating a negative pulse signal REN at the falling edge of the external read word line control signal RWL - And outputting; wherein a first input terminal of the first or gate receives an external read word line control signal RWL; first oneThe second input end of the OR gate is connected with the output end of the first inverter circuit and receives the delayed RWL inverse signal output by the first inverter circuit; the output end of the first OR gate is connected to the precharge recovery circuit.
In the above-described highly reliable programmable replica bit line clocking system for high speed SRAM, a precharge recovery circuit comprising: a first NAND gate and a second NAND gate;
a first input end of the first NAND gate is connected with the output end of the first OR gate and receives the negative pulse signal REN output by the first OR gate - The method comprises the steps of carrying out a first treatment on the surface of the The second input end of the first NAND gate is connected with the output end of the second NAND gate; the output end of the first NAND gate is connected with the first input end of the second NAND gate and is used as the output end of the precharge recovery circuit to be connected to the feedback control logic circuit and the precharge tube;
the first input end of the second NAND gate is connected with the output end of the first NAND gate; the second input end of the second NAND gate is connected with the output end of the feedback control logic circuit and receives a precharge enable feedback signal PCHRGEN output by the feedback control logic circuit; the output end of the second NAND gate is connected with the second input end of the first NAND gate.
In the above-described highly reliable programmable replica bit line clocking system for high speed SRAM, the feedback control logic circuit comprises: a second inverter and a third NAND gate;
a second inverter for receiving a replica bit line potential RBL outputted from the programmable replica bit line, generating a sense amplifier enable signal SAE according to the replica bit line potential RBL, and outputting; the output end of the second inverter outputs a sense amplifier enable signal SAE and is connected with the first input end of the third NAND gate;
a third NAND gate for receiving the sense amplifier enable signal SAE output from the output terminal of the second inverter and the word line strobe signal SWL output from the precharge recovery circuit; performing NAND operation on the sense amplifier enable signal SAE and the word line strobe signal SWL to obtain a precharge enable feedback signal PCHRGEN, and outputting the precharge enable feedback signal PCHRGEN to a precharge recovery circuit; wherein, the first input end of the third NAND gate is connected with the output end of the second inverter, receive the sense amplifier enabling signal SAE; the second input end of the third NAND gate is connected with the output end of the first NAND gate and receives the word line strobe signal SWL.
In the highly reliable programmable replica bit line clocking system for high speed SRAM described above, the switching threshold of the second inverter is less than the maximum offset voltage of the sense amplifier in the memory cell array.
In the above-described highly reliable programmable replica bit line clocking system for high speed SRAM, an edge detection circuit comprises: a third inverter and a first nor gate;
the third inverter is used for receiving an external read word line control signal RWL and obtaining a delayed RWL inverse signal; the output end of the third inverter is connected with the second input end of the first NOR gate;
a first NOR gate for performing NOR operation on the external read word line control signal RWL and the delayed RWL inverse signal, and generating a positive pulse signal REN at the falling edge of the external read word line control signal RWL + And outputting; wherein, the first input end of the first NOR gate receives an external read word line control signal RWL; the second input end of the first NOR gate is connected with the output end of the third inverter, and receives the delayed RWL inverse signal output by the third inverter; the output end of the first NOR gate is connected to the pre-charge recovery circuit.
In the above-described highly reliable programmable replica bit line clocking system for high speed SRAM, a precharge recovery circuit comprising: a second nor gate, a third nor gate, and a fourth inverter;
The first input end of the second NOR gate is connected with the output end of the first NOR gate and receives the positive pulse signal REN output by the first NOR gate + The method comprises the steps of carrying out a first treatment on the surface of the The second input end of the second NOR gate is connected with the output end of the third NOR gate; the output end of the second NOR gate is connected with the first input end of the third NOR gate and the input end of the fourth inverter, and is used as the first output end of the precharge recovery circuit to be connected to the feedback control logic circuit;
the first input end of the third NOR gate is connected with the output end of the second NOR gate; the second input end of the third NOR gate is connected with the output end of the feedback control logic circuit and receives a precharge enable feedback signal PCHRGEN output by the feedback control logic circuit; the output end of the third NOR gate is connected with the second input end of the second NOR gate;
the input end of the fourth inverter is connected with the output end of the second NOR gate, and the output end of the fourth inverter is used as the second output end of the pre-charge recovery circuit and is connected to the pre-charge tube.
In the above-described highly reliable programmable replica bit line clocking system for high speed SRAM, the feedback control logic circuit comprises: a fifth inverter, a sixth inverter, and a fourth nor gate;
a fifth inverter for receiving a replica bit line potential RBL outputted from the programmable replica bit line, generating a sense amplifier enable signal SAE according to the replica bit line potential RBL, and outputting; wherein the output end of the fifth inverter outputs a sense amplifier enable signal SAE and is connected with the input end of the sixth inverter;
A sixth inverter for receiving the sense amplifier enable signal SAE output from the output terminal of the fifth inverter, inverting the sense amplifier enable signal SAE, and outputting; the output end of the sixth inverter is connected with the first input end of the fourth NOR gate;
a fourth NOR gate for receiving the inverted sense amplifier enable signal SAE outputted from the output terminal of the sixth inverter Reverse-rotation And a word line strobe signal SWL output from the precharge recovery circuit; the inverted sense amplifier enable signal SAE Reverse-rotation Performing NOR operation with the word line strobe signal SWL to obtain a precharge enable feedback signal PCHRGEN, and outputting the precharge enable feedback signal PCHRGEN to a precharge recovery circuit; wherein the first input end of the fourth NOR gate is connected with the output end of the sixth inverter, and receives the sense amplifier enable signal SAE after inversion Reverse-rotation The method comprises the steps of carrying out a first treatment on the surface of the The second input end of the fourth nor gate is connected with the output end of the second nor gate, and receives the word line strobe signal SWL.
In the highly reliable programmable replica bit line clocking system for high speed SRAM described above, the switching threshold of the fifth inverter is less than the maximum offset voltage of the sense amplifier in the memory cell array.
The invention has the following advantages:
(1) The invention discloses a high-reliability programmable replica bit line clock control system for a high-speed SRAM, which utilizes the edge of an external read word line control signal RWL to trigger the discharge of a discharge unit in a programmable replica bit line and feeds back to obtain a word line strobe signal SWL, uses the word line strobe signal SWL to replace the external read word line control signal RWL in a traditional control circuit to directly control the precharge and discharge of the programmable replica bit line, and only when the read operation is finished, the word line strobe signal SWL is restored to an initial state, any fluctuation and interference of the word line strobe signal SWL can not influence the time sequence of the programmable replica bit line, thereby improving the anti-interference capability of the read time sequence of the programmable replica bit line and providing accurate and reliable charge and discharge time sequence.
(2) The invention discloses a high-reliability programmable replica bit line clock control system for a high-speed SRAM, which can realize self-timing bit line pair pre-charge and discharge of a programmable replica bit line to a clock control logic under the condition of programming to slowest discharge, can effectively solve the problems of insufficient discharge caused by smaller pulse width of an external read word line control signal RWL and error read time sequence caused by incapability of starting a sense amplifier enable signal SAE, and improves the reliability of the programmable replica bit line read-write time sequence.
(3) The invention discloses a high-reliability programmable replica bit line clock control system for a high-speed SRAM, which only utilizes the edge of a read word line to trigger a programmable replica bit line discharge unit to discharge, self-adjusts and generates a discharge enabling pulse width, the read word line pulse width has corresponding adjustable capacity, and can be adjusted according to the discharge speeds under different programming conditions so as to achieve the maximum performance, thereby ensuring the stable and reliable operation of a circuit.
(4) The invention discloses a high-reliability programmable replica bit line clock control system for a high-speed SRAM, which adopts a word line strobe signal SWL to replace an external read word line control signal RWL in a traditional control circuit to directly control the pre-charge and discharge of a programmable replica bit line, and the word line strobe signal SWL is turned off in time after a sense amplifier enabling signal is valid, thereby overcoming the problem that the traditional replica bit line control circuit still continuously discharges after the sense amplifier is enabled, reducing unnecessary discharge of the programmable replica bit line and reducing the charge and discharge power consumption overhead of the replica bit line.
Drawings
FIG. 1 is a schematic diagram of a high-reliability programmable replica bit line clocking system for a high-speed SRAM in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of a clock control circuit according to an embodiment of the present invention;
FIG. 3 is a schematic waveform diagram of the circuit operation under a triggering condition in an embodiment of the present invention;
FIG. 4 is a schematic waveform diagram of the circuit operation under yet another trigger condition in an embodiment of the invention;
fig. 5 is a schematic diagram of a clock control circuit according to another embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention disclosed herein will be described in further detail with reference to the accompanying drawings.
The invention discloses a high-reliability programmable replica bit line clock control system for a high-speed SRAM, one of the core ideas is as follows: the active transition edge of the external read word line control signal RWL generates a series of self-adjusting timing control signals for memory cell array read operations: generating a dedicated word line strobe signal SWL at the falling edge of the external read word line control signal RWL; when the word line strobe signal SWL is at a high level, the discharge enable of the programmable replica bit line is used for controlling the pre-charge tube to be closed and the discharge unit to discharge; then, the replica bit line potential RBL outputted by the programmable replica bit line is discharged to a certain potential, and then a sense amplifier enable signal SAE is generated for controlling the read operation of the memory cell array, and at the same time, a precharge enable feedback signal PCHRGEN is fed back, the discharge enable of the word line strobe signal SWL is closed, the discharge cell stops discharging, and the precharge tube is opened to precharge the discharge cell, so that the replica bit line potential RBL is restored to a high level.
As shown in fig. 1, in the present embodiment, the high-reliability programmable replica bit line clocking system for a high-speed SRAM includes: clock control circuitry, programmable replica bit lines, and memory cell arrays.
The clock control circuit is used for receiving an external read word line control signal RWL and generating a word line gating signal SWL according to the external read word line control signal RWL; and receiving a replica bit line potential RBL output by the programmable replica bit line, and generating a sense amplifier enable signal SAE according to the replica bit line potential RBL. Wherein, when the external read word line control signal RWL is inactive, a word line strobe signal SWL of low level is generated; when the external read word line control signal RWL is changed from inactive to active, a word line strobe signal SWL of a high level is generated.
The programmable replica bit line is used for receiving a word line gating signal SWL output by the clock control circuit and cooperatively controlling a pre-charge tube and a discharge unit in the programmable replica bit line according to the word line gating signal SWL; and outputs a real-time replica bit line potential RBL. When the received word line strobe signal SWL is at a low level, the discharge unit is controlled to stop discharging, and the precharge tube is controlled to precharge the discharge unit until the replica bit line potential RBL meets a preset potential; when the received word line strobe signal SWL is at a high level, the pre-charge tube is controlled to be closed, and the discharging unit is controlled to discharge until the replica bit line potential RBL output by the programmable replica bit line meets the preset potential.
And the memory cell array is used for performing read operation according to the sense amplifier enable signal SAE output by the clock control circuit.
As can be seen from the above, in the present embodiment, the two input terminals of the clock control circuit are respectively used for receiving the external read word line control signal RWL and the replica bit line potential RBL outputted by the programmable replica bit line; the two output terminals of the clock control circuit output the word line strobe signal SWL and the sense amplifier enable signal SAE, respectively. Wherein when the external read word line control signal RWL is inactive, the programmable replica bit line is in an initial state, the word line strobe signal SWL is low (at this time, the word line strobe signal SWL is regarded as the precharge enable signal SWL 0 ) The replica bit line potential RBL is high and the sense amplifier enable signal SAE is low. When the external read word line control signal RWL is changed from inactive to active, the word output by the clock control circuitThe line strobe signal SWL is high (at this time, the word line strobe signal SWL is regarded as the read enable signal SWL 1 ) After receiving the word line strobe signal SWL of high level, the programmable replica bit line controls the pre-charge tube to be closed, the discharge unit starts discharging until the replica bit line potential RBL drops to a preset potential, the clock control circuit outputs the sense amplifier enable signal SAE of high level, then the word line strobe signal SWL becomes low level, the discharge unit stops discharging, the pre-charge tube is started, the discharge unit is pre-charged until the replica bit line potential RBL is restored to the preset potential, the sense amplifier enable signal SAE becomes low level, and the circuit is finally restored to an initial state.
In this embodiment, the clock control circuit may specifically include: an edge detection circuit 100, a precharge recovery circuit 200, and a feedback control logic circuit 300.
The edge detection circuit 100 is configured to receive the external read word line control signal RWL, detect an active transition edge of the external read word line control signal RWL, and output a pulse signal REN.
The precharge recovery circuit 200 is configured to receive the pulse signal REN output from the edge detection circuit 100 and the precharge enable feedback signal PCHRGEN output from the feedback control logic circuit 300, and generate the word line strobe signal SWL.
A feedback control logic circuit 300 for receiving the replica bit line potential RBL output by the programmable replica bit line and the word line strobe signal SWL output by the precharge recovery circuit 200; generating a sense amplifier enable signal SAE according to the replica bit line potential RBL, and outputting the sense amplifier enable signal SAE to the memory cell array; the precharge enable feedback signal PCHRGEN is generated according to the sense amplifier enable signal SAE and the word line strobe signal SWL, and is output to the precharge recovery circuit 200.
It can be seen that in the present embodiment, the edge detection circuit 100 receives the external word line control signal RWL with the active low input end, and outputs a negative pulse signal REN when the external word line control signal RWL changes from high to low - . The precharge recovery circuit 200 is a latch module that latches the negative pulse signal REN - During generation, precharge recoveryThe precharge enable feedback signal PCHRGEN received at the other input end of the circuit 200 is always at the initial high level, the precharge recovery circuit 200 outputs the word line strobe signal SWL to be changed from the low level to the high level, so that the discharge unit of the programmable replica bit line is turned on, after the replica bit line potential RBL is discharged to the lower level, the sense amplifier enable signal SAE output by the feedback control logic circuit 300 is changed from the low level to the high level, and at the same time, the precharge enable feedback signal PCHRGEN is changed from the initial high level to the low level, at this time, the word line strobe signal SWL output by the precharge recovery circuit 200 is changed to the low level, so that the discharge unit of the programmable replica bit line is turned off, the precharge tube is turned on, and the replica bit line potential RBL is recovered to the high level. The above procedure can duplicate the bit line once complete read control timing generation principle. The pulse signal REN output by the edge detection circuit 100 is a pulse signal with a narrow pulse width, and is used for setting the word line strobe signal SWL output by the precharge recovery circuit 200 by using the pulse level of the pulse signal REN, and when the word line strobe signal SWL is set, the pulse signal REN can be recovered to an initial state, and at this time, the latch structure built in the precharge recovery circuit 200 is in a hold state until the precharge enable feedback signal PCHRGEN input by the other input terminal thereof becomes a low level to reset the same.
In a preferred embodiment of the present invention, a specific circuit configuration of the possible edge detection circuit 100, precharge recovery circuit 200, and feedback control logic circuit 300 is given.
As shown in fig. 2, the edge detection circuit 100 may specifically include: a first inverter 101 and a first or gate 102.
A first inverter 101 for receiving an external read word line control signal RWL to obtain a delayed RWL inversion signal, the delay time of the delayed RWL inversion signal determining a negative pulse signal REN - Is a pulse width of (a) a pulse width of (b). Wherein the output terminal of the first inverter circuit 101 is connected to the second input terminal of the first or gate 102.
A first OR gate 102 for performing OR operation on the external read word line control signal RWL and the delayed RWL inverse signal, and generating a primary negative pulse signal REN at the falling edge of the external read word line control signal RWL - And output. Wherein, the firstA first input terminal of an or gate 102 receives an external read word line control signal RWL; a second input end of the first or gate 102 is connected with an output end of the first inverter circuit 101, and receives the delayed RWL inverted signal output by the first inverter circuit 101; the output of the first or gate 102 is connected to the precharge recovery circuit 200.
It should be noted that, the edge detection circuit 100 generates a negative pulse signal REN with a fixed pulse width only at the active transition edge of the external read word line control signal RWL - Whether the external read word line control signal RWL is a level signal or a pulse signal, the edge detection circuit 100 does not care about the level active duration of the external read word line control signal RWL. In addition, the undershoot signal REN - Pulse width setting t of (2) - The conditions are as follows: less than the delay t from the word line strobe signal SWL being high to the sense amplifier enable signal SAE under any programming conditions sae_delay This condition ensures that the negative pulse signal REN does not appear in the timing relationship of the clock control circuit - And a case where the precharge enable feedback signal PCHRGEN is simultaneously low.
As shown in fig. 2, the precharge recovery circuit 200 may specifically include: a first nand gate 201 and a second nand gate 202.
A first input end of the first NAND gate 201 is connected with the output end of the first OR gate 102 and receives the negative pulse signal REN output by the first OR gate 102 - The method comprises the steps of carrying out a first treatment on the surface of the A second input of the first nand gate 201 is connected to an output of the second nand gate 202; the output of the first nand gate 201 is connected to the first input of the second nand gate 202 and is connected as an output of the precharge recovery circuit 200 to the feedback control logic circuit 300 and the precharge tube 400.
A first input of the second nand gate 202 is connected to an output of the first nand gate 201; a second input end of the second nand gate 202 is connected to an output end of the feedback control logic circuit 300, and receives a precharge enable feedback signal PCHRGEN output by the feedback control logic circuit 300; an output of the second nand gate 202 is connected to a second input of the first nand gate 201.
Note that the first nand gate 201 and the second nand gate 202 have the same element structure, and are two elementsTogether forming an RS latch. When the negative pulse signal REN - When the precharge enable feedback signal PCHRGEN is at a low level, the RS latch is set, and the output word line strobe signal SWL is at a high level. When the negative pulse signal REN - When the precharge enable feedback signal PCHRGEN is at a low level, the RS latch is in a reset state, and the output word line strobe signal SWL is at a low level. When the negative pulse signal REN - And when the precharge enable feedback signal PCHRGEN is at a high level, the RS latch is in a hold state, and the output word line strobe signal SWL keeps the last state potential unchanged. When the negative pulse signal REN - And when the precharge enable feedback signal PCHRGEN is low level, the RS latch is in an inactive state, and the output word line strobe signal SWL is high level.
As shown in fig. 2, the feedback control logic 300 may specifically include: a second inverter 301 and a third nand gate 302.
The second inverter 301 receives the replica bit line potential RBL outputted from the programmable replica bit line, generates a sense amplifier enable signal SAE based on the replica bit line potential RBL, and outputs the sense amplifier enable signal SAE. Wherein the output terminal of the second inverter 301 outputs the sense amplifier enable signal SAE while being connected to the first input terminal of the third nand gate 302. Further, the pull-up threshold of the second inverter 301 (i.e., the voltage difference at which the RBL is discharged when the inverter changes from low to high) should be greater than the maximum offset voltage of the sense amplifier, so that the sense amplifier can achieve a correct amplification function when the sense amplifier enable signal SAE changes to high.
A third nand gate 302 for receiving the sense amplifier enable signal SAE output from the output terminal of the second inverter 301 and the word line strobe signal SWL output from the precharge recovery circuit 200; the sense amplifier enable signal SAE and the word line gate signal SWL are nand-operated to obtain a precharge enable feedback signal PCHRGEN, which is output to the precharge recovery circuit 200. Wherein a first input terminal of the third nand gate 302 is connected to an output terminal of the second inverter 301, and receives the sense amplifier enable signal SAE; a second input terminal of the third nand gate 302 is connected to the output terminal of the first nand gate 201, and receives the word line gate signal SWL.
It should be noted that, when the word line strobe signal SWL is at a high level and the discharge unit completes the discharge to generate the sense amplifier enable signal SAE at a high level, the precharge enable feedback signal PCHRGEN is outputted at a low level, the precharge tube is turned on by the logic operation of the precharge recovery circuit 200, and the discharge of the unit is ended. Further, after the sense amplifier enable signal SAE outputted from the feedback control logic circuit 300 becomes high level, the word line strobe signal SWL outputted from the precharge recovery circuit 200 becomes low level via the third nand gate 302, and the precharge tube is turned on to a logic delay t where the sense amplifier enable signal SAE finally becomes low level sa Is the time of the sense amplifier enable signal SAE.
In the present embodiment, as shown in fig. 3, fig. 3 (a) shows: when the external read word line control signal RWL is a level signal, the working time sequence schematic diagram of the high-reliability programmable replica bit line clock control system is provided; fig. 3 (b) shows: when the external read word line control signal RWL is a level signal, the working timing diagram of the bit line control circuit is duplicated conventionally. As can be seen, the conventional replica bit line control circuit directly controls the discharge enable and precharge enable of the discharge cells using the external read word line control signal RWL, such that after the sense amplifier enable signal SAE becomes active and the read operation is completed, the discharge enable is still turned on, which results in the programmable replica bit line to continue discharging until the external read word line control signal RWL is inactive, which may result in unnecessary power consumption. The high-reliability programmable replica bit line clock control system can realize the precharge and discharge of the self-timing bit line pair, and particularly can be applied to the programmable replica bit line to turn off the discharge unit in time after the read operation is finished, thereby avoiding unnecessary continuous discharge and reducing the power consumption.
In the present embodiment, as shown in fig. 4, fig. 4 (a) shows: when the pulse width of the external read word line control signal RWL is smaller, the working time sequence schematic diagram of the high-reliability programmable replica bit line clock control system is provided; fig. 4 (b) shows: when the pulse width of the external read word line control signal RWL is smaller, the working timing diagram of the conventional replica bit line control circuit is shown. As can be seen, in the conventional replica bit line control circuit, when the read word line has a narrower fixed pulse width and the programmable replica bit line discharges at the slowest speed, the RBL discharge is insufficient, which is insufficient to enable the logic of the next inverter to be inverted, the precharge tube is started in advance to charge the RBL to a high level, and in this case, the sense amplifier enable signal SAE of a high level cannot be generated, resulting in an erroneous read control timing of the circuit. To avoid this problem it is generally required that the RBL pulse width is large enough to allow sufficient discharge of the RBL for each programming condition, but this in turn causes the aforementioned loss of power consumption. The high-reliability programmable replica bit line clock control system adopts the special word line strobe signal SWL to replace an external read word line control signal RWL as a control signal, and obtains the word line strobe signals SWL with different pulse widths according to the discharge speed feedback of the programmable replica bit line under each programming condition, thereby being capable of accurately controlling the discharge and the pre-charge of the programmable replica bit line, realizing high-reliability time sequence control and effectively solving the problems.
In a preferred embodiment of the present invention, a specific circuit configuration of a further possible edge detection circuit 100, precharge recovery circuit 200 and feedback control logic circuit 300 is given.
As shown in fig. 5, the edge detection circuit 100 may specifically include: a third inverter 103 and a first nor gate 104.
A third inverter 103 for receiving the external read word line control signal RWL to obtain a delayed RWL inverse signal, the delay time of the delayed RWL inverse signal determining the positive pulse signal REN + Is a pulse width of (a) a pulse width of (b). The output terminal of the third inverter 103 is connected to the second input terminal of the first nor gate 104.
A first NOR gate 104 for performing NOR operation on the external read word line control signal RWL and the delayed RWL inverse signal, and generating a positive pulse signal REN at the falling edge of the external read word line control signal RWL + And output. Wherein a first input terminal of the first nor gate 104 receives an external read word line control signal RWL; the second input end of the first nor gate 104 is connected with the output end of the third inverter 103, and receives the delayed RWL inverted signal output by the third inverter 103; the output of the first nor gate 104 is connected to the precharge recovery circuit 200.
It should be noted that, the edge detection circuit 100 generates a positive pulse signal REN with a fixed pulse width only at the active transition edge of the external read word line control signal RWL + Whether the external read word line control signal RWL is a level signal or a pulse signal, the edge detection circuit 100 does not care about the level active duration of the external read word line control signal RWL. In addition, the positive pulse signal REN + Pulse width setting t of (2) + The conditions are as follows: less than the delay t from the word line strobe signal SWL being high to the sense amplifier enable signal SAE under any programming conditions sae_delay This condition ensures that the negative pulse signal REN does not appear in the timing relationship of the clock control circuit - And a case where the precharge enable feedback signal PCHRGEN is at a high level at the same time.
As shown in fig. 5, the precharge recovery circuit 200 may specifically include: a second nor gate 203, a third nor gate 204 and a fourth inverter 205.
A first input terminal of the second nor gate 203 is connected to the output terminal of the first nor gate 104, and receives the positive pulse signal REN output by the first nor gate 104 + The method comprises the steps of carrying out a first treatment on the surface of the A second input of the second nor gate 203 is connected to an output of the third nor gate 204; an output terminal of the second nor gate 203 is connected to a first input terminal of the third nor gate 204 and an input terminal of the fourth inverter 205, and is connected to the feedback control logic circuit 300 as a first output terminal of the precharge recovery circuit 200.
A first input of the third nor gate 204 is connected to an output of the second nor gate 203; a second input terminal of the third nor gate 204 is connected to an output terminal of the feedback control logic circuit 300, and receives the precharge enable feedback signal PCHRGEN output by the feedback control logic circuit 300; an output of the third nor gate 204 is connected to a second input of the second nor gate 203.
An input terminal of the fourth inverter 205 is connected to an output terminal of the second nor gate 203, and an output terminal of the fourth inverter 205 is connected to the precharge pipe 400 as a second output terminal of the precharge recovery circuit 200.
It should be noted that the second nor gate 203 and the third nor gate 204 have the same element structure, and form a common structureAnd RS latches. When the pulse signal REN is positive + When the precharge enable feedback signal PCHRGEN is at a low level, the RS latch is in a reset state, and the output word line strobe signal SWL is at a high level. When the pulse signal REN is positive + When the precharge enable feedback signal PCHRGEN is at a low level, the RS latch is set, and the output word line strobe signal SWL is at a low level. When the pulse signal REN is positive + And when the precharge enable feedback signal PCHRGEN is low level, the RS latch is in a hold state, and the output word line strobe signal SWL keeps the previous state potential unchanged. When the pulse signal REN is positive + And when the precharge enable feedback signal PCHRGEN is at a high level, the RS latch is in an inactive state, and the output word line strobe signal SWL is at a high level.
As shown in fig. 5, the feedback control logic 300 may specifically include: a fifth inverter 303, a sixth inverter 304, and a fourth nor gate 305.
The fifth inverter 303 receives the replica bit line potential RBL outputted from the programmable replica bit line, generates a sense amplifier enable signal SAE based on the replica bit line potential RBL, and outputs the sense amplifier enable signal SAE. Wherein the output terminal of the fifth inverter 303 outputs the sense amplifier enable signal SAE while being connected to the input terminal of the sixth inverter 304. Further, the pull-up threshold of the fifth inverter 303 (i.e., the voltage difference at which the RBL is discharged when the inverter goes from low to high) should be greater than the maximum offset voltage of the sense amplifier, so that the sense amplifier can implement the correct amplification function when the sense amplifier enable signal SAE goes to high.
A sixth inverter 304 for receiving the sense amplifier enable signal SAE output from the output terminal of the fifth inverter 303, and inverting the sense amplifier enable signal SAE and outputting it. The output terminal of the sixth inverter 304 is connected to the first input terminal of the fourth nor gate 305.
A fourth NOR gate 305 for receiving the inverted sense amplifier enable signal SAE outputted from the output terminal of the sixth inverter 304 Reverse-rotation And a word line gate signal SWL output from the precharge recovery circuit 200; the inverted sense amplifier enable signal SAE Reverse-rotation Nor operation with word line strobe signal SWLThe precharge enable feedback signal PCHRGEN is obtained, and the precharge enable feedback signal PCHRGEN is output to the precharge recovery circuit 200. Wherein a first input terminal of the fourth NOR gate 305 is connected with the output terminal of the sixth inverter 304, and receives the inverted sense amplifier enable signal SAE Reverse-rotation The method comprises the steps of carrying out a first treatment on the surface of the A second input terminal of the fourth nor gate 305 is connected to the output terminal of the second nor gate 203, and receives the word line gate signal SWL.
After the word line strobe signal SWL goes high, the precharge recovery circuit 200 outputs a logic delay t after the word line strobe signal SWL goes low and the precharge tube is turned on to the sense amplifier enable signal SAE finally goes low through the sixth inverter 304 sa Is the time of the sense amplifier enable signal SAE.
In summary, in the highly reliable programmable replica bit line clock control system for a high-speed SRAM according to the embodiments of the present invention, under the condition of programming to the slowest discharge, the replica bit line pair clock control circuit can implement self-timing bit line pair precharge and discharge, so that the problem that the external read word line control signal RWL is insufficient in pulse width, and the sense amplifier enable signal SAE cannot be turned on to cause an erroneous read timing can be effectively solved, the reliability of the replica bit line pair read/write timing is improved, and the trouble that the circuit needs to have the adjustable external read word line control signal RWL due to the reliability problem can be effectively avoided. Meanwhile, the special word line control signal SWL is turned off in time after the sense amplifier enable signal SAE is effective, so that the problem that the conventional replica bit line control circuit still continuously discharges after the sense amplifier is enabled is solved, unnecessary discharge of the replica bit line pair is reduced, and the power consumption is effectively reduced.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.
What is not described in detail in the present specification belongs to the known technology of those skilled in the art.

Claims (10)

1. A high reliability programmable replica bit line clocking system for a high speed SRAM, comprising: a clock control circuit, a programmable replica bit line, and a memory cell array;
the clock control circuit is used for receiving an external read word line control signal RWL and generating a word line gating signal SWL according to the external read word line control signal RWL; and receiving a replica bit line potential RBL output by the programmable replica bit line, and generating a sense amplifier enable signal SAE according to the replica bit line potential RBL; wherein, when the external read word line control signal RWL is inactive, a word line strobe signal SWL of low level is generated; when the external read word line control signal RWL is changed from inactive to active, a word line strobe signal SWL of a high level is generated;
The programmable replica bit line is used for receiving a word line gating signal SWL output by the clock control circuit and cooperatively controlling a pre-charge tube and a discharge unit in the programmable replica bit line according to the word line gating signal SWL; and outputting a real-time replica bit line potential RBL; when the received word line strobe signal SWL is at a low level, the discharge unit is controlled to stop discharging, and the precharge tube is controlled to precharge the discharge unit until the replica bit line potential RBL meets a preset potential; when the received word line strobe signal SWL is at a high level, the pre-charge tube is controlled to be closed, and the discharging unit is controlled to discharge until the replica bit line potential RBL output by the programmable replica bit line meets a preset potential;
and the memory cell array is used for performing read operation according to the sense amplifier enable signal SAE output by the clock control circuit.
2. The high-reliability programmable replica bit-line clocking system for high-speed SRAM of claim 1, wherein the clocking circuit comprises: an edge detection circuit (100), a precharge recovery circuit (200), and a feedback control logic circuit (300);
an edge detection circuit (100) for receiving an external read word line control signal RWL, detecting an effective transition edge of the external read word line control signal RWL, and outputting a pulse signal REN;
A precharge recovery circuit (200) for receiving the pulse signal REN outputted from the edge detection circuit (100) and the precharge enable feedback signal PCHRGEN outputted from the feedback control logic circuit (300) to generate a word line strobe signal SWL;
a feedback control logic circuit (300) for receiving a replica bit line potential RBL outputted from the programmable replica bit line and a word line strobe signal SWL outputted from the precharge recovery circuit (200); generating a sense amplifier enable signal SAE according to the replica bit line potential RBL, and outputting the sense amplifier enable signal SAE to the memory cell array; a precharge enable feedback signal PCHRGEN is generated based on a sense amplifier enable signal SAE and a word line strobe signal SWL, and is outputted to a precharge recovery circuit (200).
3. The high-reliability programmable replica bit-line clocking system for high-speed SRAM of claim 2, wherein the edge detection circuit (100) comprises: a first inverter (101) and a first OR gate (102);
a first inverter (101) for receiving an external read word line control signal RWL to obtain a delayed RWL inverted signal; wherein the output end of the first inverter (101) is connected with the second input end of the first OR gate (102);
A first OR gate (102) for performing OR operation on the external read word line control signal RWL and the delayed RWL inverse signal, and generating a primary negative pulse signal REN at the falling edge of the external read word line control signal RWL - And outputting; wherein a first input terminal of the first or gate (102) receives an external read word line control signal RWL; the second input end of the first OR gate (102) is connected with the output end of the first inverter (101) and receives the delayed RWL inverse signal output by the first inverter (101); an output of the first or gate (102) is connected to a precharge recovery circuit (200).
4. A high reliability programmable replica bit line clocking system for a high speed SRAM according to claim 3, wherein the precharge restore circuit (200) comprises: a first NAND gate (201) and a second NAND gate (202);
a first input end of the first NAND gate (201) is connected with an output end of the first OR gate (102) and receives a negative pulse signal REN output by the first OR gate (102) - The method comprises the steps of carrying out a first treatment on the surface of the A second input end of the first NAND gate (201) is connected with an output end of the second NAND gate (202); the output end of the first NAND gate (201) is connected with the first input end of the second NAND gate (202) and is used as the output end of the pre-charge recovery circuit (200) to be connected to the feedback control logic circuit (300) and the pre-charge tube;
A first input end of the second NAND gate (202) is connected with an output end of the first NAND gate (201); a second input end of the second NAND gate (202) is connected with an output end of the feedback control logic circuit (300) and receives a precharge enable feedback signal PCHRGEN output by the feedback control logic circuit (300); an output of the second NAND gate (202) is connected to a second input of the first NAND gate (201).
5. The high-reliability programmable replica bit-line clocking system for high-speed SRAM of claim 4, wherein the feedback control logic circuit (300) comprises: a second inverter (301) and a third NAND gate (302);
a second inverter (301) for receiving a replica bit line potential RBL outputted from the programmable replica bit line, generating a sense amplifier enable signal SAE based on the replica bit line potential RBL, and outputting; wherein the output end of the second inverter (301) outputs a sense amplifier enable signal SAE and is connected with the first input end of the third NAND gate (302);
a third NAND gate (302) for receiving the sense amplifier enable signal SAE outputted from the output terminal of the second inverter (301) and the word line strobe signal SWL outputted from the precharge recovery circuit (200); performing NAND operation on the sense amplifier enable signal SAE and the word line strobe signal SWL to obtain a precharge enable feedback signal PCHRGEN, and outputting the precharge enable feedback signal PCHRGEN to a precharge recovery circuit (200); wherein a first input terminal of the third NAND gate (302) is connected with an output terminal of the second inverter (301), receiving the sense amplifier enable signal SAE; a second input end of the third NAND gate (302) is connected with an output end of the first NAND gate (201) and receives a word line strobe signal SWL.
6. The high-reliability programmable replica bit-line clocking system for high-speed SRAM of claim 5, wherein the switching threshold of the second inverter (301) is less than the maximum offset voltage of the sense amplifier in the memory cell array.
7. The high-reliability programmable replica bit-line clocking system for high-speed SRAM of claim 2, wherein the edge detection circuit (100) comprises: a third inverter (103) and a first nor gate (104);
a third inverter (103) for receiving the external read word line control signal RWL to obtain a delayed RWL inverted signal; the output end of the third inverter (103) is connected with the second input end of the first NOR gate (104);
a first NOR gate (104) for performing NOR operation on the external read word line control signal RWL and the delayed RWL inverse signal, and generating a positive pulse signal REN once at the falling edge of the external read word line control signal RWL + And outputting; wherein a first input of the first nor gate (104) receives an external read word line control signal RWL; the second input end of the first NOR gate (104) is connected with the output end of the third inverter (103) and receives the delayed RWL inverse signal output by the third inverter (103); an output of the first nor gate (104) is connected to a precharge recovery circuit (200).
8. The high-reliability programmable replica bit-line clocking system for high-speed SRAM of claim 7, wherein the precharge recovery circuit (200) comprises: a second nor gate (203), a third nor gate (204) and a fourth inverter (205);
a first input end of the second NOR gate (203) is connected with the output end of the first NOR gate (104) and receives the positive pulse signal REN output by the first NOR gate (104) + The method comprises the steps of carrying out a first treatment on the surface of the A second NOR gate (203)The input end is connected with the output end of the third NOR gate (204); the output end of the second NOR gate (203) is connected with the first input end of the third NOR gate (204) and the input end of the fourth inverter (205), and is connected to the feedback control logic circuit (300) as the first output end of the pre-charge recovery circuit (200);
a first input end of the third nor gate (204) is connected with an output end of the second nor gate (203); a second input end of the third nor gate (204) is connected with an output end of the feedback control logic circuit (300) and receives a precharge enable feedback signal PCHRGEN output by the feedback control logic circuit (300); the output end of the third NOR gate (204) is connected with the second input end of the second NOR gate (203);
an input end of the fourth inverter (205) is connected with an output end of the second NOR gate (203), and an output end of the fourth inverter (205) is used as a second output end of the pre-charge recovery circuit (200) to be connected to a pre-charge tube.
9. The high-reliability programmable replica bit-line clocking system for high-speed SRAM of claim 8, wherein the feedback control logic circuit (300) comprises: a fifth inverter (303), a sixth inverter (304), and a fourth nor gate (305);
a fifth inverter (303) for receiving a replica bit line potential RBL outputted from the programmable replica bit line, generating a sense amplifier enable signal SAE based on the replica bit line potential RBL, and outputting; wherein the output end of the fifth inverter (303) outputs a sense amplifier enable signal SAE and is connected with the input end of the sixth inverter (304);
a sixth inverter (304) for receiving the sense amplifier enable signal SAE output from the output terminal of the fifth inverter (303), inverting the sense amplifier enable signal SAE, and outputting the inverted sense amplifier enable signal SAE; wherein the output of the sixth inverter (304) is connected to the first input of the fourth nor gate (305);
a fourth NOR gate (305) for receiving the negated sense amplifier enable signal SAE outputted from the output end of the sixth inverter (304) Reverse-rotation And a word line strobe signal SWL outputted from the precharge recovery circuit (200); the inverted sense amplifier enable signal SAE Reverse-rotation Performing NOR operation with the word line strobe signal SWL to obtain a precharge enable feedback signal PCHRGEN, and outputting the precharge enable feedback signal PCHRGEN to a precharge recovery circuit (200); wherein a first input end of the fourth NOR gate (305) is connected with an output end of the sixth inverter (304) and receives the inverted sense amplifier enable signal SAE Reverse-rotation The method comprises the steps of carrying out a first treatment on the surface of the A second input terminal of the fourth nor gate (305) is connected to the output terminal of the second nor gate (203), and receives the word line strobe signal SWL.
10. The high-reliability programmable replica bit-line clocking system for high-speed SRAM of claim 9, wherein the switching threshold of the fifth inverter (303) is less than the maximum offset voltage of the sense amplifier in the memory cell array.
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