CN112596943A - Hardware implementation method based on USB3.1 protocol 16-bit cyclic redundancy check - Google Patents
Hardware implementation method based on USB3.1 protocol 16-bit cyclic redundancy check Download PDFInfo
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Abstract
The invention discloses a hardware implementation method based on 16-bit cyclic redundancy check of a USB3.1 protocol, which is characterized by being applied to USB3.1 equipment, wherein the USB3.1 equipment comprises a host, a hub and slave equipment, and the method comprises a CRC-16 calculation method in a sending end-to-end packet and a CRC-16 calculation method in a receiving end-to-end packet.
Description
Technical Field
The invention relates to the field of USB transmission, in particular to a hardware implementation method based on 16-bit cyclic redundancy check of a USB3.1 protocol.
Background
USB is an abbreviation for Universal Serial Bus (USB), an external Bus standard used to standardize the connection and communication between computers and external devices. The USB interface supports plug and play and hot plug functions of the device. The USB standard was proposed by a combination of companies such as intel, compaq, IBM, Microsoft and the like in the end of 1994, and has been widely used in various electronic devices such as computers, mobile phones, digital cameras and the like.
The USB standard is established and maintained by USB official organization USB-IF, seven versions of USB1.0, USB1.1, USB2.0, USB3.0, USB3.1, USB3.2 and USB4 are released in sequence from the beginning to the present, and a new version is forward compatible with an old version. The maximum transmission rate distribution supported by each version is:
USB1.0： 1.5Mbps；
USB1.1： 12Mbps；
USB2.0：480Mbps；
USB3.0：5Gbps；
USB3.1：10Gbps；
USB3.2：20Gbps；
USB4：40Gbps。
the maximum transmission rate supported by the USB3.1 standard protocol is 10Gbps, and two working modes, namely Gen2 (10 Gbps) and Gen1 (5 Gbps), are mainly adopted. In terms of encoding mode, the USB3.1 adopts the encoding mode of 128B/132B in the Gen2 mode, and compared with the encoding mode of 8B/10B used in the USB3.0 protocol, the bandwidth utilization rate is effectively improved.
The system architecture of USB3.1 is shown in fig. 1, and includes two parts, SuperSpeedPlus (Gen2) and SuperSpeed (Gen1), each of which includes a Device layer (Device/Host), a protocol layer (protocol layer), a link layer (link layer), and a physical layer (physical layer).
Cyclic Redundancy Check (CRC) is one of the most commonly used error checking codes in the field of data communications, and is characterized in that the lengths of the information field and the Check field can be arbitrarily selected. Cyclic Redundancy Check (CRC) is a data transmission error detection function that performs polynomial calculations on data and attaches the resulting data to the data, and the receiving device uses the same algorithm to calculate the received data and compare the result with the received cyclic redundancy check code to determine the correctness and integrity of the data transmission.
The header packet (HeaderPacket) in the USB3.1 protocol uses CRC-16 to protect the data content.
The header packet (HeaderPacket) has 12 bytes (96 bits) in total, and mainly has 4 types, which are respectively:
link Management Packet (Link Management Packet)
Transmission packet (Transactionpacket)
Data Packet (Data Packet)
A synchronous Timestamp Packet (Isochronous Timestamp Packet).
The specific definition of the header packet is shown in fig. 1.
The header packet (HeaderPacket) has 16 bytes, and mainly comprises: type (Type), routing information (Route String), device address (DeviceAddress), subtype (Sub Type), retransmission (Rty), Direction (Direction), endpoint number (EptNum), stream number (streamID), 16-bit cyclic redundancy check value (CRC-16), link control word (LinkControlWord), and the like.
According to the definition of the USB3.1 protocol, a 16-bit cyclic redundancy check value (CRC-16) is used for protecting all fields in the 12-byte control information (DWORD 0, DWORD1, DWORD 2) in the header packet, and the protection range of the CRC-16 of the USB3.1 protocol is shown in FIG. 2.
The CRC-16 implementation scheme provided by the USB3.1 protocol is based on single-bit operation and bit-by-bit iteration according to bit width, and has the defects of more iteration times, long time consumption and larger hardware delay of redundant check code generation and result check in each period, thereby limiting the working frequency and the overall performance of a hardware system.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide a hardware implementation method based on 16-bit cyclic redundancy check of a USB3.1 protocol, which shortens the hardware delay during data generation and improves the working frequency of a system by expanding an algorithm according to the data bit width and eliminating redundant items.
In order to achieve the above object, the present invention adopts the following technical solutions:
a hardware implementation method based on a 16-bit cyclic redundancy check of a USB3.1 protocol is characterized by being applied to a USB3.1 device, wherein the USB3.1 device comprises a host, a hub and a slave device, and the method comprises a CRC-16 calculation method in a sending end-to-end header packet and a CRC-16 calculation method in a receiving end-to-end header packet.
As a further preferred embodiment of the present invention, the method for calculating CRC-16 in the end-to-end header packet by the sending end includes the following steps:
s1, the initial value of the CRC-16 register of the first effective data period is hexadecimal FFFF, which is marked as CRC16[15:0], and the initial values from high order to low order are CRC16[15], CRC16[14], CRC16[13] … … CRC16[1], and CRC16[0 ];
s2, taking a value that CRC-16 register iterates n times CRC16(n), a value that CRC-16 register iterates n +1 times CRC16(n +1) is a value that CRC-16 register iterates n +1 times CRC16(n) [ m ] represents a value that CRC-16 register iterates n times mth bit (m takes a value from 0 to 15), an initial value of CRC-16 register is CRC16(0) [15:0], a current data input bit din is based on a single step iteration formula;
s3, expanding after iteration according to the number of times corresponding to the data bit width iteration;
s4, according to the fact that a ^ a ^ b = b, wherein a and b are both 2-system variables, redundant items are eliminated, and the value of the CRC-16 register of the current period is obtained;
and S5, repeating the steps S2-S4 until the CRC-16 calculation of all the head packet control information is completed, setting the value of the CRC-16 register at the moment to be inverted, reversing the order of the 0-7 bits and the 8-15 bits from the high bit to the low bit, and then reversing the order of the high 8 bits and the low 8 bits to obtain the final calculation result of the CRC-16.
As a further preferred embodiment of the present invention, the method for calculating CRC-16 in the receiving end packet includes the following steps:
s1, the initial value of the CRC-16 register of the first effective data period is hexadecimal FFFF, which is marked as CRC16[15:0], and the initial values from high order to low order are CRC16[15], CRC16[14], CRC16[13] … … CRC16[1], and CRC16[0 ];
s2, taking a value CRC16(n) representing the CRC-16 register after iteration for n times, CRC16(n +1) representing the value of the CRC-16 register after iteration for n +1 times, CRC16(n) [ m ] representing the value of the mth bit after the CRC-16 register iterates for n times, wherein m takes a value from 0 to 15, the initial value of the CRC-16 register is CRC16(0) [15:0], and the current data input bit din is substituted into a single-step iteration formula;
s3, iterating for corresponding times according to the data bit width, and then expanding;
s4, according to the fact that a ^ a ^ b = b, wherein a and b are both 2-system variables, redundant items are eliminated, and the value of the CRC-16 register of the current period is obtained;
s5, repeating S2-S4 until CRC-16 calculation of all header packet control information is completed;
and S6, the final check calculation result of the CRC-16 is F6AA in hexadecimal, and if not, the CRC-16 check failure is reported.
As a further preferred aspect of the present invention, in step S2, the one-step iterative formula of the CRC-16 calculation method in the sending end header packet and in step S2, the one-step iterative formula of the CRC-16 calculation method in the receiving end header packet are both:
crc16(n+1)[0] = din ^ crc16(n) [15]；
crc16(n+1) [1] = din ^ crc16(n) [15] ^ crc16(n) [0]；
crc16(n+1) [2] = crc16(n) [1]；
crc16(n+1) [3] = din ^ crc16(n) [15] ^ crc16(n) [2]；
crc16(n+1) [4] = crc16(n) [3]；
crc16(n+1) [5] = crc16(n) [4]；
crc16(n+1) [6] = crc16(n) [5]；
crc16(n+1) [7] = crc16(n) [6]；
crc16(n+1) [8] = crc16(n) [7]；
crc16(n+1) [9] = crc16(n) [8]；
crc16(n+1) [10] = crc16(n) [9]；
crc16(n+1) [11] = crc16(n) [10]；
crc16(n+1) [12] = din ^ crc16(n) [15] ^ crc16(n) [11]；
crc16(n+1) [13] = crc16(n) [12]；
crc16(n+1) [14] = crc16(n) [13]；
crc16(n+1) [15] = crc16(n) [14]。
as a further preferable feature of the present invention, the data bit width in the CRC-16 calculation method step S3 in the sending peer packet and the data bit width in the CRC-16 calculation method step S3 in the receiving peer packet are both 32 bits or 64 bits.
The hardware of the USB3.1 protocol 16-bit cyclic redundancy check based on data bit width expansion and redundancy elimination is characterized by being applied to a USB3.1 device, wherein the USB3.1 device comprises a host, a hub and a slave device, the hardware comprises a CRC-16 calculation logic unit and related registers, the CRC-16 calculation logic unit and related registers comprise a sending module and a receiving module, the sending module is used for carrying out CRC-16 calculation on the original content of header packet control information at the sending end, reversing the order of 0-7 bits and 8-15 bits from high bits to low bits, then reversing the order of the high 8 bits and the low 8 bits to obtain the final calculation result of the CRC-16, and finally sending out the complete 16-bit CRC-16 check value according to the order from low bits to high bits, and the receiving module is used for receiving the CRC-16 check value sent by the sending module, and performing CRC-16 calculation on the head packet at the receiving end, judging whether the CRC-16 calculation result is F6AA, if not, indicating that the data has errors in the transmission process, and reporting that the CRC-16 check fails.
The invention has the advantages that: the invention expands the algorithm according to the data bit width and eliminates redundant items, thereby shortening the hardware delay in data generation and improving the working frequency of the system.
Drawings
FIG. 1 is a system architecture diagram of USB 3.1;
FIG. 2 is a definition of a USB3.1 protocol header packet;
FIG. 3 is the protection scope of the USB3.1 protocol CRC-16;
FIG. 4 is a schematic diagram of the position of the calculation result after the calculation by the transmitting end;
FIG. 5 is a diagram of a hardware implementation of CRC-16 in the USB3.1 protocol of the present invention;
fig. 6 is a hardware block diagram of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and the embodiments.
With reference to fig. 4, in the prior art, the CRC-16 hardware implementation provided in the USB3.1 protocol is as follows:
the sender comprises the following specific steps:
the specific requirements for CRC-16 computation in the header packet at the sending end are as follows:
1. the polynomial value of CRC-16 is hexadecimal 100B;
2. the initial value of the CRC-16 register of the first valid data period is hexadecimal FFFF, which is marked as CRC16[15:0], and is CRC16[15], CRC16[14], CRC16[13] … … CRC16[1] and CRC16[0] from high order to low order;
3. the calculation of CRC-16 should cover all 12 bytes of header packet control information;
4. CRC-16 is calculated from bit 0 of byte 0 of the header packet control information up to bit 7 of byte 12;
5. XOR the current compute input bit (control information in the header packet) with the value of the highest bit of the current CRC-16 register, CRC16[15], and stores the result in the lowest bit of the CRC-16 register, CRC16[0 ];
6. the value of the highest bit of the current CRC-16 register, CRC16[15], is XOR'd with the current calculation input bit (control information in the header packet), then XOR'd with the lowest bit of the previous CRC-16 register, CRC16[0], and the result is stored in the first bit, CRC16[1 ];
7. the value of the first bit of the current CRC-16 register, CRC16[1], is stored into the second bit, CRC16[2 ];
8. the value of the highest bit of the current CRC-16 register, CRC16[15], is XOR'd with the current calculation input bit (control information in the header packet), then XOR'd with the second bit of the previous CRC-16 register, CRC16[2], and the result is stored in the third bit, CRC16[3 ];
9. the values CRC16[3] -CRC16[10] of the third bit to the tenth bit of the current CRC-16 register are stored into the fourth bit to the eleventh bit CRC16[4] -CRC16[11] in sequence;
10. the value of the highest bit CRC16[15] of the current CRC-16 register is XOR-ed with the current calculation input bit (control information in the header packet), then XOR-ed with the eleventh bit CRC16[11] of the previous CRC-16 register, and the result is stored in the twelfth bit CRC16[12 ];
11. the values CRC16[12] -CRC16[14] of the twelfth bit to the fourteenth bit of the current CRC-16 register are sequentially stored into the eleventh bit to the fifteenth bit CRC16[13] -CRC16[15 ];
12. repeating the steps 5 to 11, and sequentially operating all the input bits of the current operation period bit by bit to obtain the final CRC-16 register value of the current period;
13. repeating the steps 2 to 12 until the CRC-16 calculation of all the head packet control information is completed, inverting the value of the CRC-16 register according to the bits, inverting the sequence of the 0-7 bits and the 8-15 bits from the high bit to the low bit according to the bits, and inverting the sequence of the high 8 bits and the low 8 bits to obtain the final CRC-16 calculation result, as shown in FIG. 4;
14. transmitting the complete 16-bit CRC-16 check value according to the sequence from the lower bit to the upper bit;
the specific requirements for CRC-16 computation in the header packet at the receiving end are as follows:
1. the polynomial value of CRC-16 is hexadecimal 100B;
2. the initial value of the CRC-16 register of the first valid data period is hexadecimal FFFF, which is marked as CRC16[15:0], and is CRC16[15], CRC16[14], CRC16[13] … … CRC16[1] and CRC16[0] from high order to low order;
3. the calculation of CRC-16 should cover all 12 bytes of header packet control information;
4. CRC-16 is calculated from bit 0 of byte 0 of the header packet control information up to bit 7 of byte 12;
5. XOR the current compute input bit (control information in the header packet) with the value of the highest bit of the current CRC-16 register, CRC16[15], and stores the result in the lowest bit of the CRC-16 register, CRC16[0 ];
6. the value of the highest bit of the current CRC-16 register, CRC16[15], is XOR'd with the current calculation input bit (control information in the header packet), then XOR'd with the lowest bit of the previous CRC-16 register, CRC16[0], and the result is stored in the first bit, CRC16[1 ];
7. the value of the first bit of the current CRC-16 register, CRC16[1], is stored into the second bit, CRC16[2 ];
8. the value of the highest bit of the current CRC-16 register, CRC16[15], is XOR'd with the current calculation input bit (control information in the header packet), then XOR'd with the second bit of the previous CRC-16 register, CRC16[2], and the result is stored in the third bit, CRC16[3 ];
9. the values CRC16[3] -CRC16[10] of the third bit to the tenth bit of the current CRC-16 register are stored into the fourth bit to the eleventh bit CRC16[4] -CRC16[11] in sequence;
10. the value of the highest bit CRC16[15] of the current CRC-16 register is XOR-ed with the current calculation input bit (control information in the header packet), then XOR-ed with the eleventh bit CRC16[11] of the previous CRC-16 register, and the result is stored in the twelfth bit CRC16[12 ];
11. the values CRC16[12] -CRC16[14] of the twelfth bit to the fourteenth bit of the current CRC-16 register are sequentially stored into the eleventh bit to the fifteenth bit CRC16[13] -CRC16[15 ];
12. repeating the steps 5 to 11, and sequentially operating all the input bits of the current operation period bit by bit to obtain the final CRC-16 register value of the current period;
13. and repeating the steps 2 to 12 until the CRC-16 calculation of all the received header packet control information is completely finished, and finally, the check calculation result of the CRC-16 is F6AA in hexadecimal, otherwise, reporting that the CRC-16 check fails.
The invention provides a USB3.1 protocol CRC-16 hardware implementation scheme based on data bit width expansion, redundant item elimination is carried out after expansion, and the operation result of the current operation cycle CRC-16 is calculated at one time, and the specific scheme process is as follows:
the sender comprises the following specific steps:
1. the initial value of the CRC-16 register of the first valid data period is hexadecimal FFFF, which is marked as CRC16[15:0], and is CRC16[15], CRC16[14], CRC16[13] … … CRC16[1] and CRC16[0] from high order to low order;
2. taking CRC16(n) as the value after n iterations of the CRC-16 register, CRC16(n +1) as the value after n +1 iterations of the CRC-16 register, CRC16(n) [ m ] as the value of the mth bit after n iterations of the CRC-16 register (m ranges from 0 to 15), the initial value of the CRC-16 register is CRC16(0) [15:0], the current data input bit din, based on the single step iteration formula:
crc16(n+1)[0] = din ^ crc16(n) [15]；
crc16(n+1) [1] = din ^ crc16(n) [15] ^ crc16(n) [0]；
crc16(n+1) [2] = crc16(n) [1]；
crc16(n+1) [3] = din ^ crc16(n) [15] ^ crc16(n) [2]；
crc16(n+1) [4] = crc16(n) [3]；
crc16(n+1) [5] = crc16(n) [4]；
crc16(n+1) [6] = crc16(n) [5]；
crc16(n+1) [7] = crc16(n) [6]；
crc16(n+1) [8] = crc16(n) [7]；
crc16(n+1) [9] = crc16(n) [8]；
crc16(n+1) [10] = crc16(n) [9]；
crc16(n+1) [11] = crc16(n) [10]；
crc16(n+1) [12] = din ^ crc16(n) [15] ^ crc16(n) [11]；
crc16(n+1) [13] = crc16(n) [12]；
crc16(n+1) [14] = crc16(n) [13]；
crc16(n+1) [15] = crc16(n) [14]；
and according to the actual data bit width (such as 32 bits, 64 bits or other bit widths), expanding after iterating the corresponding times (32 times, 64 times or other bit width corresponding times), and according to a ^ a ^ b = b (a and b are 2-system variables), eliminating redundant items to obtain the value of the CRC-16 register of the current period.
For typical 32-bit data bit widths in USB3.1 hardware implementations, the simplified result is as follows (crc 16[ n is abbreviated as c [ n ], din [ n is abbreviated as d [ n ]):
crc16(32)[0] = c[12] ^ d[19] ^ c[15] ^ c[4] ^ d[27] ^ c[13] ^ c[10] ^ d[5] ^ d[8] ^ d[10] ^ d[16] ^ c[5] ^ d[3] ^ d[23] ^ c[7] ^ d[31] ^ d[11] ^ d[2] ^ d[18] ^ d[0]；
crc16(32)[1] = c[12] ^ d[19] ^ c[11] ^ c[15] ^ c[4] ^ d[27] ^ d[4] ^ d[17] ^ d[26] ^ c[14] ^ c[10] ^ d[5] ^ d[8] ^ c[8] ^ d[16] ^ d[9] ^ c[0] ^ d[1] ^ d[30] ^ d[3] ^ d[23] ^ c[6] ^ c[7] ^ d[15] ^ d[22] ^ d[7] ^ d[31] ^ d[11] ^ d[0]；
crc16(32)[2] = c[12] ^ c[11] ^ c[1] ^ d[25] ^ c[15] ^ c[9] ^ d[4] ^ c[13] ^ d[26] ^ d[8] ^ c[8] ^ d[10] ^ d[16] ^ d[6] ^ c[0] ^ c[5] ^ d[30] ^ d[3] ^ c[7] ^ d[15] ^ d[22] ^ d[7] ^ d[21] ^ d[2] ^ d[29] ^ d[18] ^ d[14] ^ d[0]；
crc16(32)[3] = d[19] ^ c[1] ^ d[25] ^ c[15] ^ c[9] ^ c[4] ^ d[27] ^ d[13] ^ d[17] ^ c[14] ^ d[24] ^ d[8] ^ c[8] ^ d[10] ^ d[16] ^ d[6] ^ d[9] ^ d[20] ^ c[0] ^ c[5] ^ d[1] ^ c[2] ^ d[23] ^ c[6] ^ c[7] ^ d[15] ^ d[28] ^ d[7] ^ d[21] ^ d[31] ^ d[11] ^ d[29] ^ d[18] ^ d[14] ^ d[0]；
crc16(32)[4] = d[19] ^ c[1] ^ c[3] ^ c[15] ^ c[9] ^ d[27] ^ d[13] ^ d[17] ^ d[26] ^ d[24] ^ c[10] ^ d[5] ^ d[8] ^ c[8] ^ d[10] ^ d[16] ^ d[6] ^ d[9] ^ d[20] ^ c[0] ^ c[5] ^ d[30] ^ d[23] ^ c[2] ^ c[6] ^ c[7] ^ d[15] ^ d[22] ^ d[28] ^ d[7] ^ d[12] ^ d[18] ^ d[14] ^ d[0]；
crc16(32)[5] = d[19] ^ c[1] ^ c[11] ^ d[25] ^ c[3] ^ c[9] ^ c[4] ^ d[27] ^ d[4] ^ d[13] ^ d[17] ^ d[26] ^ c[10] ^ d[5] ^ c[8] ^ d[8] ^ d[16] ^ d[6] ^ d[9] ^ c[0] ^ d[23] ^ c[2] ^ c[6] ^ d[15] ^ c[7] ^ d[22] ^ d[7] ^ d[21] ^ d[12] ^ d[11] ^ d[29] ^ d[18] ^ d[14]；
crc16(32)[6] = c[12] ^ c[1] ^ c[11] ^ d[25] ^ c[3] ^ c[9] ^ c[4] ^ d[4] ^ d[13] ^ d[17] ^ d[26] ^ c[10] ^ d[24] ^ d[5] ^ c[8] ^ d[8] ^ d[10] ^ d[16] ^ d[6] ^ d[20] ^ c[0] ^ c[5] ^ d[3] ^ c[2] ^ d[15] ^ c[7] ^ d[22] ^ d[7] ^ d[28] ^ d[21] ^ d[12] ^ d[11] ^ d[18] ^ d[14]；
crc16(32)[7] = c[12] ^ d[19] ^ c[1] ^ c[11] ^ d[25] ^ c[3] ^ c[9] ^ c[4] ^ d[27] ^ d[4] ^ c[13] ^ d[13] ^ d[17] ^ d[24] ^ c[10] ^ d[5] ^ c[8] ^ d[10] ^ d[16] ^ d[6] ^ d[9] ^ d[20] ^ c[0] ^ c[5] ^ d[3] ^ c[2] ^ d[23] ^ c[6] ^ d[15] ^ d[7] ^ d[21] ^ d[12] ^ d[11] ^ d[2] ^ d[14]；
crc16(32)[8] = c[12] ^ d[19] ^ c[11] ^ c[1] ^ c[3] ^ c[9] ^ c[4] ^ d[4] ^ c[13] ^ d[13] ^ c[14] ^ d[26] ^ d[24] ^ c[10] ^ d[5] ^ d[8] ^ d[10] ^ d[16] ^ d[6] ^ d[9] ^ d[20] ^ c[0] ^ c[5] ^ d[1] ^ d[3] ^ d[23] ^ c[2] ^ c[6] ^ d[15] ^ c[7] ^ d[22] ^ d[12] ^ d[11] ^ d[2] ^ d[18] ^ d[14]；
crc16(32)[9] = c[12] ^ d[19] ^ c[1] ^ c[11] ^ d[25] ^ c[3] ^ c[15] ^ c[4] ^ c[13] ^ d[4] ^ d[13] ^ d[17] ^ c[14] ^ c[10] ^ d[5] ^ c[8] ^ d[8] ^ d[10] ^ d[9] ^ c[0] ^ c[5] ^ d[1] ^ d[3] ^ d[23] ^ c[2] ^ c[6] ^ d[15] ^ c[7] ^ d[22] ^ d[7] ^ d[21] ^ d[12] ^ d[11] ^ d[2] ^ d[18] ^ d[14] ^ d[0]；
crc16(32)[10] = c[12] ^ c[1] ^ c[11] ^ c[3] ^ c[15] ^ c[9] ^ c[4] ^ c[13] ^ d[4] ^ d[13] ^ d[17] ^ c[14] ^ d[24] ^ c[8] ^ d[8] ^ d[10] ^ d[16] ^ d[6] ^ d[9] ^ d[20] ^ c[5] ^ d[1] ^ d[3] ^ c[2] ^ c[6] ^ c[7] ^ d[22] ^ d[7] ^ d[21] ^ d[12] ^ d[11] ^ d[2] ^ d[18] ^ d[14] ^ d[0]；
crc16(32)[11] = c[12] ^ d[19] ^ c[3] ^ c[15] ^ c[9] ^ c[4] ^ c[13] ^ d[13] ^ d[17] ^ c[14] ^ c[10] ^ d[5] ^ d[8] ^ c[8] ^ d[10] ^ d[16] ^ d[6] ^ d[9] ^ d[20] ^ c[0] ^ c[5] ^ d[1] ^ d[3] ^ c[2] ^ d[23] ^ c[6] ^ c[7] ^ d[15] ^ d[7] ^ d[21] ^ d[12] ^ d[11] ^ d[2] ^ d[0]；
crc16(32)[12] = c[12] ^ c[1] ^ c[11] ^ c[3] ^ c[9] ^ d[27] ^ d[4] ^ c[14] ^ c[8] ^ d[6] ^ d[9] ^ d[20] ^ c[0] ^ d[1] ^ d[3] ^ d[23] ^ c[6] ^ d[15] ^ d[22] ^ d[7] ^ d[12] ^ d[31] ^ d[14]；
crc16(32)[13] = c[12] ^ d[19] ^ c[1] ^ c[15] ^ c[9] ^ c[4] ^ c[13] ^ d[13] ^ d[26] ^ c[10] ^ d[5] ^ d[8] ^ d[6] ^ d[30] ^ d[3] ^ c[2] ^ c[7] ^ d[22] ^ d[21] ^ d[11] ^ d[2] ^ d[14] ^ d[0]；
crc16(32)[14] = c[11] ^ d[25] ^ c[3] ^ c[13] ^ d[4] ^ d[13] ^ c[14] ^ c[10] ^ d[5] ^ c[8] ^ d[10] ^ d[20] ^ c[5] ^ d[1] ^ c[2] ^ d[7] ^ d[21] ^ d[12] ^ d[2] ^ d[29] ^ d[18]；
crc16(32)[15] = c[12] ^ d[19] ^ c[11] ^ c[3] ^ c[15] ^ c[9] ^ c[4] ^ d[4] ^ d[17] ^ c[14] ^ d[24] ^ d[6] ^ d[9] ^ d[20] ^ d[1] ^ d[3] ^ c[6] ^ d[28] ^ d[12] ^ d[11] ^ d[0]；
3. and (3) repeating the step (2) until the CRC-16 calculation of all the head packet control information is completed, inverting the value of the CRC-16 register at the moment according to bits, inverting the sequence of the 0-7 bits and the 8-15 bits from the high bit to the low bit according to the bits, and inverting the sequence of the high 8 bits and the low 8 bits to obtain the final CRC-16 calculation result.
The receiving side comprises the following specific steps:
1. the initial value of the CRC-16 register of the first valid data period is hexadecimal FFFF, which is marked as CRC16[15:0], and is CRC16[15], CRC16[14], CRC16[13] … … CRC16[1] and CRC16[0] from high order to low order;
2. taking CRC16(n) as the value after n iterations of the CRC-16 register, CRC16(n +1) as the value after n +1 iterations of the CRC-16 register, CRC16(n) [ m ] as the value of the mth bit after n iterations of the CRC-16 register (m ranges from 0 to 15), the initial value of the CRC-16 register is CRC16(0) [15:0], the current data input bit din, based on the single step iteration formula:
crc16(n+1)[0] = din ^ crc16(n) [15]；
crc16(n+1) [1] = din ^ crc16(n) [15] ^ crc16(n) [0]；
crc16(n+1) [2] = crc16(n) [1]；
crc16(n+1) [3] = din ^ crc16(n) [15] ^ crc16(n) [2]；
crc16(n+1) [4] = crc16(n) [3]；
crc16(n+1) [5] = crc16(n) [4]；
crc16(n+1) [6] = crc16(n) [5]；
crc16(n+1) [7] = crc16(n) [6]；
crc16(n+1) [8] = crc16(n) [7]；
crc16(n+1) [9] = crc16(n) [8]；
crc16(n+1) [10] = crc16(n) [9]；
crc16(n+1) [11] = crc16(n) [10]；
crc16(n+1) [12] = din ^ crc16(n) [15] ^ crc16(n) [11]；
crc16(n+1) [13] = crc16(n) [12]；
crc16(n+1) [14] = crc16(n) [13]；
crc16(n+1) [15] = crc16(n) [14]；
and according to the actual data bit width (such as 32 bits, 64 bits or other bit widths), expanding after iterating the corresponding times (32 times, 64 times or other bit width corresponding times), and according to a ^ a ^ b = b (a, b are 2-system variables), eliminating redundant items to obtain the value of the CRC-16 register of the current period.
3. And repeating the step 2 until the CRC-16 calculation of all the head packet control information is completed, and finally, the check calculation result of the CRC-16 is F6AA in hexadecimal, otherwise, reporting that the CRC-16 check fails.
Comparing the single-bit iteration provided by the USB3.1 protocol in the prior art with the single-cycle data processing delay of the CRC-16 hardware implementation scheme based on bit width expansion and redundancy elimination in the technical scheme of the invention:
noting that the hardware delay required by 1 single-bit data exclusive or is T, for the CRC-16 hardware implementation scheme of single-bit iteration provided by the USB3.1 protocol, the maximum delay in a single iteration is the 2 nd bit, the 4 th bit and the 13 th bit of the generated CRC-16 register, namely, CRC16(n) [1], CRC16(n) [3] and CRC16(n) [12], two times of single-bit exclusive OR are required, and the corresponding delay is 2 × T. For a 32-bit data bit width, a single data processing cycle requires 32 iterations, so the total latency of a single cycle is 64 × T.
For the CRC-16 hardware implementation scheme based on data bit width expansion and redundancy item elimination, the maximum delay in a single data processing cycle is the 2 nd bit, the 4 th bit and the 13 th bit of a CRC-16 register, and the corresponding expressions are as follows:
crc16(32)[1] = c[12] ^ d[19] ^ c[11] ^ c[15] ^ c[4] ^ d[27] ^ d[4] ^ d[17] ^ d[26] ^ c[14] ^ c[10] ^ d[5] ^ d[8] ^ c[8] ^ d[16] ^ d[9] ^ c[0] ^ d[1] ^ d[30] ^ d[3] ^ d[23] ^ c[6] ^ c[7] ^ d[15] ^ d[22] ^ d[7] ^ d[31] ^ d[11] ^ d[0]；
crc16(32)[3] = d[19] ^ c[1] ^ d[25] ^ c[15] ^ c[9] ^ c[4] ^ d[27] ^ d[13] ^ d[17] ^ c[14] ^ d[24] ^ d[8] ^ c[8] ^ d[10] ^ d[16] ^ d[6] ^ d[9] ^ d[20] ^ c[0] ^ c[5] ^ d[1] ^ c[2] ^ d[23] ^ c[6] ^ c[7] ^ d[15] ^ d[28] ^ d[7] ^ d[21] ^ d[31] ^ d[11] ^ d[29] ^ d[18] ^ d[14] ^ d[0]；
crc16(32)[12] = c[12] ^ c[1] ^ c[11] ^ c[3] ^ c[9] ^ d[27] ^ d[4] ^ c[14] ^ c[8] ^ d[6] ^ d[9] ^ d[20] ^ c[0] ^ d[1] ^ d[3] ^ d[23] ^ c[6] ^ d[15] ^ d[22] ^ d[7] ^ d[12] ^ d[31] ^ d[14]；
36 "single bit exclusive ors" are required, so the total delay required to generate a CRC-16 cycle is 36 × T.
In table 1, the single-bit iteration provided by the USB3.1 protocol is compared with the hardware delay required for completing the single-cycle data operation under different data bit widths by the CRC-16 hardware implementation scheme based on bit width expansion and redundancy elimination in the technical scheme of the present invention.
Note: all the units of the delay data in the table are hardware delay time required by' single-bit data XOR
With reference to fig. 6, the hardware for USB3.1 protocol 16-bit cyclic redundancy check based on data bit width expansion and redundancy elimination is characterized in that the hardware is applied to USB3.1 devices, the USB3.1 devices include a host, a hub and a slave device, the hardware includes a CRC-16 calculation logic unit and related registers, the CRC-16 calculation logic unit and related registers include a sending module and a receiving module, the sending module is configured to perform CRC-16 calculation on original content of header packet control information at the sending terminal, reverse the order of 0-7 bits and 8-15 bits from high bit to low bit, then reverse the order of high 8 bits and low 8 bits to obtain a final CRC-16 calculation result, and finally send out a complete CRC-16 value in order from low bit to high bit, the receiving module is configured to receive the CRC-16 check value sent by the sending module, and performing CRC-16 calculation on the head packet at the receiving end, judging whether the CRC-16 calculation result is F6AA, if not, indicating that the data has errors in the transmission process, and reporting that the CRC-16 check fails.
The invention has the advantages that: the invention expands the algorithm according to the data bit width and eliminates redundant items, thereby shortening the hardware delay in data generation and improving the working frequency of the system.
The foregoing illustrates and describes the principles, general features, and advantages of the present invention. It should be understood by those skilled in the art that the above embodiments do not limit the present invention in any way, and all technical solutions obtained by using equivalent alternatives or equivalent variations fall within the scope of the present invention.
Claims (6)
1. A hardware implementation method based on a 16-bit cyclic redundancy check of a USB3.1 protocol is characterized by being applied to a USB3.1 device, wherein the USB3.1 device comprises a host, a hub and a slave device, and the method comprises a CRC-16 calculation method in a sending end-to-end header packet and a CRC-16 calculation method in a receiving end-to-end header packet.
2. The hardware implementation method of claim 1, wherein the method for calculating CRC-16 in the header packet at the transmitting end comprises the following steps:
s1, the initial value of the CRC-16 register of the first effective data period is hexadecimal FFFF, which is marked as CRC16[15:0], and the initial values from high order to low order are CRC16[15], CRC16[14], CRC16[13] … … CRC16[1], and CRC16[0 ];
s2, taking a value that CRC-16 register iterates n times CRC16(n), a value that CRC-16 register iterates n +1 times CRC16(n +1) is a value that CRC-16 register iterates n +1 times CRC16(n) [ m ] represents a value that CRC-16 register iterates n times mth bit (m takes a value from 0 to 15), an initial value of CRC-16 register is CRC16(0) [15:0], a current data input bit din is based on a single step iteration formula;
s3, expanding after iteration according to the number of times corresponding to the data bit width iteration;
s4, according to the fact that a ^ a ^ b = b, wherein a and b are both 2-system variables, redundant items are eliminated, and the value of the CRC-16 register of the current period is obtained;
and S5, repeating the steps S2-S4 until the CRC-16 calculation of all the head packet control information is completed, setting the value of the CRC-16 register at the moment to be inverted, reversing the order of the 0-7 bits and the 8-15 bits from the high bit to the low bit, and then reversing the order of the high 8 bits and the low 8 bits to obtain the final calculation result of the CRC-16.
3. The hardware implementation method of claim 2, wherein the method for calculating CRC-16 in the accept-end header packet comprises the following steps:
s1, the initial value of the CRC-16 register of the first effective data period is hexadecimal FFFF, which is marked as CRC16[15:0], and the initial values from high order to low order are CRC16[15], CRC16[14], CRC16[13] … … CRC16[1], and CRC16[0 ];
s2, taking a value CRC16(n) representing the CRC-16 register after iteration for n times, CRC16(n +1) representing the value of the CRC-16 register after iteration for n +1 times, CRC16(n) [ m ] representing the value of the mth bit after the CRC-16 register iterates for n times, wherein m takes a value from 0 to 15, the initial value of the CRC-16 register is CRC16(0) [15:0], and the current data input bit din is substituted into a single-step iteration formula;
s3, iterating for corresponding times according to the data bit width, and then expanding;
s4, according to the fact that a ^ a ^ b = b, wherein a and b are both 2-system variables, redundant items are eliminated, and the value of the CRC-16 register of the current period is obtained;
s5, repeating S2-S4 until CRC-16 calculation of all header packet control information is completed;
and S6, the final check calculation result of the CRC-16 is F6AA in hexadecimal, and if not, the CRC-16 check failure is reported.
4. The hardware implementation method of claim 3, wherein the single-step iteration formula in step S2 of the method for calculating CRC-16 in the sending peer packet and the single-step iteration formula in step S2 of the method for calculating CRC-16 in the receiving peer packet are both:
crc16(n+1)[0] = din ^ crc16(n) [15]；
crc16(n+1) [1] = din ^ crc16(n) [15] ^ crc16(n) [0]；
crc16(n+1) [2] = crc16(n) [1]；
crc16(n+1) [3] = din ^ crc16(n) [15] ^ crc16(n) [2]；
crc16(n+1) [4] = crc16(n) [3]；
crc16(n+1) [5] = crc16(n) [4]；
crc16(n+1) [6] = crc16(n) [5]；
crc16(n+1) [7] = crc16(n) [6]；
crc16(n+1) [8] = crc16(n) [7]；
crc16(n+1) [9] = crc16(n) [8]；
crc16(n+1) [10] = crc16(n) [9]；
crc16(n+1) [11] = crc16(n) [10]；
crc16(n+1) [12] = din ^ crc16(n) [15] ^ crc16(n) [11]；
crc16(n+1) [13] = crc16(n) [12]；
crc16(n+1) [14] = crc16(n) [13]；
crc16(n+1) [15] = crc16(n) [14]。
5. the hardware implementation method of claim 3, wherein the data bit width in the CRC-16 calculation method step S3 in the sending peer packet and the data bit width in the CRC-16 calculation method step S3 in the receiving peer packet are both 32 bits or 64 bits.
6. The hardware of the USB3.1 protocol 16-bit cyclic redundancy check based on data bit width expansion and redundancy elimination is characterized by being applied to a USB3.1 device, wherein the USB3.1 device comprises a host, a hub and a slave device, the hardware comprises a CRC-16 calculation logic unit and related registers, the CRC-16 calculation logic unit and related registers comprise a sending module and a receiving module, the sending module is used for carrying out CRC-16 calculation on the original content of header packet control information at the sending end, reversing the order of 0-7 bits and 8-15 bits from high bits to low bits, then reversing the order of the high 8 bits and the low 8 bits to obtain the final calculation result of the CRC-16, and finally sending out the complete 16-bit CRC-16 check value according to the order from low bits to high bits, and the receiving module is used for receiving the CRC-16 check value sent by the sending module, and performing CRC-16 calculation on the head packet at the receiving end, judging whether the CRC-16 calculation result is F6AA, if not, indicating that the data has errors in the transmission process, and reporting that the CRC-16 check fails.
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