CN112585753A

CN112585753A - Novel bit line architecture and method to improve page size and performance of 3D NAND

Info

Publication number: CN112585753A
Application number: CN202080003775.8A
Authority: CN
Inventors: 刘峻; 薛磊
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-11-24
Filing date: 2020-11-24
Publication date: 2021-03-30
Also published as: WO2022109778A1

Abstract

A three-dimensional memory includes a plurality of bit lines, finger storage regions, and a plurality of channel holes. The bit line has a length extending in a first direction. The finger storage region has a first end defined by a first gate slit extending in a second direction perpendicular to the first direction; a second end defined by a second gate slit extending in a second direction; and a width extending in the first direction between the first end and the second end. The plurality of channel holes are located at the finger storage region, and each channel hole extends in a depth direction perpendicular to each of the first direction and the second direction and is connected to a corresponding one of the plurality of bit lines.

Description

Novel bit line architecture and method to improve page size and performance of 3D NAND

Technical Field

The present disclosure relates generally to three-dimensional electronic memories, and more particularly to increasing the density of memory cells in a 3d nand memory.

Background

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of the memory cell approaches the lower limit, the planar processes and fabrication techniques become challenging and costly. As such, the storage density of planar memory cells approaches an upper limit. A three-dimensional (3D) storage architecture for accessing memory of the 3D storage architecture may address density limitations in planar storage cells.

Disclosure of Invention

The 3D storage architecture of the present disclosure addresses problems of the current state of the art 3D storage architectures and provides a number of benefits.

According to an aspect, there is provided a three-dimensional memory, comprising: a plurality of bit lines, each bit line having a length extending in a first direction; a first finger storage region having a first end defined by a first gate slit extending in a second direction perpendicular to the first direction, a second end defined by a second gate slit extending in the second direction, and a width extending in the first direction between the first end and the second end; and a first plurality of channel holes located at a first finger storage region of the three-dimensional memory, each of the first plurality of channel holes extending in a depth direction perpendicular to each of the first and second directions and connected to a corresponding one of the plurality of bit lines.

In some examples, the first finger storage area may include: eight channel holes connected to the eight bit lines in a one-to-one correspondence; seven channel holes connected to the seven bit lines in a one-to-one correspondence; or six channel holes connected to six bit lines in a one-to-one correspondence.

In some examples, the bit lines may be configured to have a reduced bit line pitch using quad imaging.

In some examples, each of the first and second gate slits may be positioned to separate the first finger storage region from an adjacent finger storage region in the first direction.

In some examples, the three-dimensional memory may include: a second finger storage region adjacent to the first finger storage region and separated from the first finger storage region by a first gate slit; and a second plurality of channel holes located at a second finger storage region, each of the second plurality of channel holes extending in a depth direction and connected to a corresponding one of the plurality of bit lines.

In some examples, the first plurality of trench holes may be disposed in a zigzag pattern along the first direction.

In some examples, the three-dimensional memory may be a Charge Trap Flash (CTF) NAND memory.

According to another aspect, a method of forming a three-dimensional memory including a plurality of finger storage regions, each finger storage region having a width along a first direction and having first and second ends defined by respective first and second gate slits extending along a second direction perpendicular to the first direction is provided. The method can comprise the following steps: forming, for a first finger storage region, a first plurality of channel holes, each of the channel holes extending in a depth direction perpendicular to each of a first direction and a second direction; and forming a plurality of bit lines over the first plurality of channel holes, wherein each bit line may be connected to a corresponding one of the first plurality of channel holes.

In some examples, forming the first plurality of channel holes may include forming eight channel holes, and forming the plurality of bit lines may include forming eight bit lines. In some examples, forming the first plurality of channel holes may include forming six channel holes, and forming the plurality of bit lines may include forming six bit lines.

In some examples, the bit lines may be formed using quad imaging.

In some examples, the method further comprises: forming a second plurality of channel holes for a second finger storage region separated from the first finger storage region by a first gate slit, each of the second plurality of channel holes extending in a depth direction, the plurality of bit lines being formed over the second plurality of channel holes, wherein each bit line may be connected to a corresponding one of the second plurality of channel holes.

According to yet another aspect, there is provided a three-dimensional memory, comprising: a plurality of bit lines, each bit line having a length extending in a first direction; a first finger storage area having a first end defined by a first gate slit extending in a second direction perpendicular to the first direction, a second end defined by a second gate slit extending in the second direction, and a width extending in the first direction; and a first plurality of channel holes located at a first finger storage region of the three-dimensional memory, each of the first plurality of channel holes extending in a depth direction perpendicular to each of the first and second directions. The first plurality of trench holes may include: a medial channel hole disposed along the incision, the incision having a length extending in the second direction; a first subset of the first plurality of channel holes located in a first page of the three-dimensional memory between a first gate aperture and the cut; and a second subset of the first plurality of channel holes located in a second page of the three-dimensional memory between the second gate aperture and the cutout. Each channel hole of the first subset of the first plurality of channel holes may be connected to a corresponding one of the plurality of bit lines, and each channel hole of the second subset of the first plurality of channel holes is connected to a corresponding one of the plurality of bit lines.

In some examples, the notch may have a depth of three write lines.

In some examples, the first plurality of channel holes may include thirteen channel holes, and each of the first and second subsets of the first plurality of channel holes includes six channel holes.

In some examples, each of the first page and the second page may have a finger storage region width equal to six channel holes.

In some examples, a first bit line of the plurality of bit lines may be connected to each of the channel hole closest to the first gate slit and the channel hole closest to the second gate slit, a second bit line of the plurality of bit lines may be connected to each of the channel hole closest to the first gate slit and the channel hole closest to the second gate slit, a third bit line of the plurality of bit lines may be connected to each of the channel hole closest to the third gate slit and the channel hole closest to the third gate slit, a fourth bit line of the plurality of bit lines may be connected to each of the channel hole closest to the fourth gate slit and the channel hole closest to the fourth gate slit, a fifth bit line of the plurality of bit lines may be connected to each of the channel hole closest to the first gate slit and the channel hole closest to the fifth gate slit, and a sixth bit line of the plurality of bit lines may be connected to each of the channel hole closest to the sixth gate slit and the channel holes closest to the sixth gate slit Each of the channel holes of the slits.

In some examples, the plurality of bit lines are arranged along the second direction in the following order: a first bit line, a third bit line, a fifth bit line, a second bit line, a fourth bit line, and a sixth bit line.

According to yet another aspect, a method of operating a three-dimensional memory having one or more finger storage regions, each finger storage region having a width extending in a first direction between a first end defined by a first gate slit extending in a second direction perpendicular to the first direction and a second end defined by a second gate slit extending in the second direction, each finger storage region having a plurality of channel holes, each channel hole extending in a depth direction perpendicular to each of the first and second directions and connected to a plurality of word lines placed in the depth direction is provided. The method can comprise the following steps: activating a single bit line, the activated bit line connected to only one channel hole of the finger storage region; and activating a word line connected to the only one channel, thereby accessing a cell located at an intersection between the only one channel and the activated word line.

Drawings

The foregoing aspects, features and advantages of the disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals refer to like elements. In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be employed for the sake of clarity. However, aspects of the present disclosure are not intended to be limited to the specific terminology used.

FIG. 1 is a plan view of a section of a conventional three-dimensional NAND memory.

FIG. 2 is a plan view of a section of a three-dimensional NAND memory according to an embodiment.

FIG. 3 is a plan view of a section of a three-dimensional NAND memory, according to another embodiment.

FIG. 4 is a plan view of a section of a three-dimensional NAND memory, according to another embodiment.

FIG. 5 is a flow diagram of a routine for forming a section of a three-dimensional NAND memory, according to an embodiment.

Detailed Description

The present techniques are applicable to the field of three-dimensional memories, and in particular to the field of three-dimensional NAND memories (3 DNAND). In 3D NAND memories, memory cells are formed in alternating layers formed of vertically stacked layers formed on a substrate. More specifically, the stack includes alternating buffer layers and memory layers, wherein memory cells occupy the memory layers of the stack.

The cells may be accessed via channels formed in the stack of layers. In general, a bit line can be formed over and electrically connected to the channel. Each vertically aligned memory cell may be electrically coupled to an overlying bit line via a channel. A separate word line can be electrically connected to each of the individual memory cells formed in the respective conductive layers of the stack. In operation, accessing a given memory cell may involve biasing a bit line connected to the channel to which the memory cell is connected, and further biasing a word line to which the memory cell is connected.

A typical stack of layers may include 64 or more layers, meaning that each channel may electrically connect a bit line to 64 or more individual memory cells. Individual memory cells may utilize Charge Trapping Flash (CTF) technology to store data, where each layer includes a charge trapping layer having an insulating material in which charge is stored according to the state of the cell.

A general example of a 3D NAND memory is shown in fig. 1. Specifically, fig. 1 is a plan view of a section of a 3DNAND memory 100. The figure depicts the section as viewed in the depth or Z direction.

In the example of fig. 1, memory 100 includes

several channels

101 and 109 formed by removing material from the stack of layers. The channel may extend downward in the depth or Z-direction from the top surface of the stacked layers to the top surface of the substrate on which the stacked layers are formed.

The channels 101-109 may be aligned in rows extending in a horizontal or X direction as shown in fig. 1. Each channel may be separated by a distance referred to as a channel pitch. FIG. 1 shows the channel spacing in the horizontal or X direction as "channel _ spacing_X(Channel_Pitch_X)". The channels may also optionally be aligned in the vertical or Y direction. For example, in the example of fig. 1,

channels

101, 103, 105, 107, and 109 are substantially aligned in a vertical direction along a first vertical line, and

channels

102, 104, 106, and 108 are substantially aligned in a vertical direction along a second vertical line. FIG. 1 shows the channel spacing in the vertical or Y direction as "channel _ spacing_Y(Channel_Pitch_Y)”。

Memory 100 also includes a plurality of

bit lines

112 and 118 located on a top surface of the stack of layers. The bit lines shown in fig. 1 have lengths that extend in the vertical or Y direction. The bit lines 112 and 114 extend along the first vertical line and thus cover each of the

channels

101, 103, 105, 107, and 109.

Bit lines

116 and 118 extend along the second vertical line and thus cover each of the

channels

102, 104, 106, and 108.

The memory also includes connections 122-128 and 132-138 for each of the respective channels. Each

connection

122, 128, and 132, 138 connects its respective channel to a bit line. As such, although multiple bit lines may overlie a single channel, the channel may be connected to only one of the overlying bit lines. For example, although each of the

bit lines

112 and 114 overlies each of the

channels

101, 103, 105, 107, and 109, connections are provided only between the bit line 112 and the

channels

101 and 109, and connections are provided only between the bit line 114 and the

channels

103 and 107.

Each bit line 112-118 may be separated by a distance in the horizontal or X direction, which distance is referred to herein as the "bit line pitch". The bit line pitch directly limits the number of bit lines that can cover a vertical line of the memory and directly limits the number of channels that each bit line can cover at a time. For example, in the example of fig. 1, it is shown that the bit line pitch only allows two bit lines to fit within a spacing of about the width of the channel. This results in the channel _ pitch X being limited to the four bit lines 112-118, where no additional bit lines can be accommodated.

In the example of fig. 1, the limitation of bit line pitch requires that each bit line be connected to two channels (e.g., bit line 112 to

channels

101 and 109, bit line 114 to

channels

103 and 107, bit line 116 to

channels

104 and 108, and bit line 118 to channels 102 and 106) rather than a one-to-one correspondence. This means that activation of either bit line results in selection of two different channels. To determine which of the two channels is intended to be selected, an additional input is required.

In fig. 1, a top select gate cut 140 is made along the middle row of the array of channels and serves to divide the channel 101-109 between a first page 152 and a second page 154. Specifically,

channels

101 and 104 belong to a first page 152, and

channels

106 and 109 belong to a second page 154. The channel 105 is located above the cut and does not belong to any page. The cut-outs 140 extend down into the stack of layers in the depth or Z-direction. For example, the cutout 140 may have a depth of about three word lines (e.g., about six or seven of the stacked layers), thereby making the channel hole under the cutout unsuitable for data storage.

The design of the memory 100 of fig. 1 has several drawbacks. The effective bit density is reduced by the presence of the cut 140 because the channel at or below the cut is not used for data storage. Furthermore, two instructions are required to access any given unit: the first instruction is used to select one of the

pages

152 or 154; and a second instruction to select one of the bit lines 112-118, each of the bit lines 112-118 being connected to a different channel on each

page

152, 154.

One possible solution is to increase the channel-pitch_XSuch that each bit line 112-118 covers only one connection 122-128, 132-138, rather than two connections. However, increasing the channel _ pitch_XThere is an undesirable effect of increasing the page size, which in turn requires lengthening the word lines connected to the memory cells in each channel. Having longer word lines means that instructions take longer to be sent to each cell, and thus data takes longer to be programmed to, recovered from, or both. Thus, make the channel _ pitch_XMore significantly, the read time (t) of the memory 100 is increased_R) And a programming time (t)_PGM)。

FIG. 2 is a plan view of an example section of a 3D NAND memory 200 according to an embodiment. The figure depicts the finger storage area of the memory 200 as viewed in the depth or Z direction.

In the example of fig. 2, memory 200 includes

several channels

201 and 208 formed by removing material from the stack of layers. The channel may extend downward in the depth or Z-direction from the top surface of the stacked layers to the top surface of the substrate on which the stacked layers are formed.

Memory 200 also includes a plurality of bit lines 211-218 located on the top surface of the stack of layers. The bit lines shown in fig. 2 have lengths that extend in the vertical or Y direction. The bit lines 211-214 extend along the first vertical lines and thus cover each of the

channels

201, 203, 205, and 207. The bit lines 215-218 extend along the second vertical line and thus cover each of the

channels

202, 204, 206, and 208.

The memory 200 also includes

connections

222 and 232 for each of the respective channels and 238. Each

connection

222, 228, and 232, 238 connects its corresponding channel to a bit line. As such, although multiple bit lines may overlie a single channel, the channel may be connected to only one of the overlying bit lines. For example, although each of the bit lines 111-114 overlies each of the

channels

201, 203, 205, and 207, a connection is provided only between the bit line 111 and the channel 201, a connection is provided only between the bit line 112 and the channel 203, a connection is provided only between the bit line 113 and the channel 205, and a connection is provided only between the bit line 114 and the channel 207. A similar arrangement of connections is provided between the bit lines 115 and 118 and the remaining

channels

202, 204, 206 and 208.

The bit line pitch in fig. 2 is half that shown in fig. 1. This means that it is included in the channel _ pitch_XEach of the eight channels in (a) may be connected to a corresponding one of the bit lines, rather than two bit lines. Halving the bit line pitch may be achieved by forming the bit lines using quadruple imaging.

Since each bit line is connected to only one channel. In general, the first finger storage region includes eight channels connected to eight bit lines in a one-to-one correspondence: bit line 211 is connected to channel 201 via connection 222, bit line 212 is connected to channel 203 via connection 226, bit line 213 is connected to channel 205 via connection 232, bit line 214 is connected to channel 207 via connection 236, bit line 215 is connected to channel 202 via connection 224, bit line 216 is connected to channel 204 via connection 228, bit line 217 is connected to channel 206 via connection 234, and bit line 218 is connected to channel 208 via connection 238. As such, there is no need to allocate channels between two pages. Rather, all of the channels 201-208 are included in a single page 250. In this regard, it is also not necessary to provide a top select gate cut at the middle row of channels, as there is no need to divide the channels into two pages. Doing so maintains the bit density of memory 200 without wasting any channel because all of

channels

201 and 208 are used for data storage.

Furthermore, only a single instruction is required to access a cell of a given memory region of memory 200, since no page select instruction is required to determine which of the channels is accessed by activation of any given bit line. In the example of fig. 2, a portion of the memory is shown that refers to memory areas. The finger storage region has a length extending in the horizontal or X direction and is defined by the number of bit lines along the length. In this regard, reducing the bit line pitch of the finger storage region also reduces the finger storage region length. The finger storage area has a width extending end-to-end in the vertical or Y direction. The ends of the finger storage region are defined by gate slots extending in the horizontal or X-direction. In the example of fig. 2, the finger storage region width of the finger storage region is partially shown as defined by

gate gaps

262 and 264, wherein all of the

channels

201 and 208 of the finger storage region are located between the

gate gaps

262 and 264. The gate gap may separate the finger storage region from finger storage regions adjacent to the finger storage region in the vertical or Y direction.

The example of fig. 2 shows an example memory for which the page size is doubled due to the absence of a top select gate cut. Furthermore, the bit density of the memory is increased by about 10% because 100% of the channel is utilized, rather than about 89% as was done in the example of FIG. 1. However, in other examples, it may be possible to achieve different benefits by maintaining page size. For example, if the same arrangement as in FIG. 2 is utilized, but the finger storage block length is halved (meaning fewer bit lines per finger storage block), it would be possible to maintain the page size rather than double it, but t_RAnd t_PGMMay be significantly increased. This is because the finger storage area length can be halved, which in turn halves the average word line length. As with any electrical line, a word line may have both resistive and capacitive characteristics, such that the time for commands and data to travel on that line is defined by its RC constant. Halving the length of this line will halve both its resistance (R) and its capacitance (C), which means that the RC of the word line will be reduced by approximately 75%, essentially causing t of the word line_RAnd t_PGMBoth are significantly increased.

It will be appreciated from the above examples that various characteristics of the memory (such as bit density, page size, t, etc.)_RAnd t_PGM) The improvements can be balanced against each other to achieve an overall improvement in the operation of the memory device. Fig. 3 shows another example configuration of such an improved memory device.

FIG. 3 is a plan view of an example section of a 3D NAND memory 300 in accordance with another embodiment. The figure depicts the finger storage area of the memory 300 as viewed in the depth or Z direction.

In the example of fig. 3, memory 300 includes several channels 301 formed by removing material from the stack of layers 306. The channel may extend downward in the depth or Z-direction from the top surface of the stacked layers to the top surface of the substrate on which the stacked layers are formed. Memory 300 also includes a plurality of bit lines on the top surface of the stack of layers, and the bit lines have lengths extending in the vertical or Y direction and are connected to a respective one of

channels

301 and 306 via

respective connections

322 and 332 and 334. In general, the first finger storage region includes six channels connected to six bit lines in a one-to-one correspondence: bit line 311 is connected to channel 301 via connection 322, bit line 312 is connected to channel 303 via connection 326, bit line 313 is connected to channel 305 via connection 332, bit line 314 is connected to channel 302 via connection 324, bit line 315 is connected to channel 304 via connection 328, and bit line 316 is connected to channel 306 via connection 334. To fit within this channel pitch, the bit lines may be configured to have a reduced bit line pitch as compared to the example of fig. 1 by using quad imaging to form the bit lines.

As in the example of fig. 2, it is not necessary to allocate channels between two pages. Instead, all of the channels 301-306 are included in a single page 350. In this regard, it is also not necessary to provide a top select gate cut at the middle row of channels, as there is no need to divide the channels into separate pages. Doing so maintains the bit density of the memory 300 without wasting any channel, since all of the channels 301-306 are used for data storage.

Furthermore, only a single instruction is required to access the cells of a given memory region of memory 300, since no page select instruction is required to determine which of the channels is selected by activation of any given bit line. In the example of fig. 3, the finger storage region width of the finger storage region shown in part is defined by

gate gaps

362 and 364, wherein all of the channels of

finger storage region

301 and 306 are located between

gate gaps

362, 364. Which may be referred to as a finger storage region width with six channel holes.

In the example of FIG. 3, the bit line pitch and the Trench _ pitch_XThe ratio between is reduced by about one third. In other words, the example of FIG. 1 accommodates two bit lines over a width roughly equal to the diameter of a single channel, while the example of FIG. 3 accommodates three bit lines over a width roughly equal to the diameter of a single channel. This has the advantage of increasing the page size by about 50% and thus the throughput by about 50%. In the alternative, if the finger storage area length in FIG. 3 is reduced to maintain a page size equal to the page size of FIG. 1, doing so will shorten the average word line length, so that t_RAnd t_PGMIs reduced by 60% or more. At the same time, since 100% of the channel is utilized, the bit density remains as high or only slightly lower than that of the memory 100 in fig. 1, despite the reduced finger storage width.

FIG. 4 illustrates another exemplary embodiment of an improved memory device.

FIG. 4 is a plan view of an example section of a 3D NAND memory 400 in accordance with another embodiment. The figure depicts the finger storage area of the memory 400 as viewed in the depth or Z direction.

In the example of fig. 4, the memory 400 includes two

pages

452, 454, where each page is itself similar to the memory 300 of fig. 3. The first page 452 includes a number of first channels 401-. The channel may extend downward in the depth or Z-direction from the top surface of the stacked layers to the top surface of the substrate on which the stacked layers are formed. Memory 400 also includes a plurality of bit lines 411-416 on the top surface of the stack, the bit lines having lengths that extend in the vertical or Y direction. Each of the bit lines 411-416 is connected to a respective one of the channels 401-406 of the first page 452 via respective connections 422-428 and 432-434 and to a respective one of the channels 461-466 of the second page 454 via respective connections 472-478 and 482-484. Specifically, bit line 411 is connected to channel 401 via connection 422 and to channel 466 via connection 484, bit line 412 is connected to channel 403 via connection 426 and to channel 464 via connection 478, bit line 413 is connected to channel 405 via connection 432 and to channel 462 via connection 474, bit line 414 is connected to channel 402 via connection 424 and to channel 465 via connection 482, bit line 415 is connected to channel 404 via connection 428 and to channel 463 via connection 476, and bit line 416 is connected to channel 406 via connection 434 and to channel 461 via connection 472.

In the example of fig. 4, a top select gate cut 440 is provided between

channels

406 and 461. Since each bit line contacts multiple channels, a top select gate is required to divide the low channel between the two pages. Thus, the channel 407 in the middle row of the finger storage area (on which the notch is formed) is not used for data storage. Unlike fig. 1, however, the finger storage region width of the finger storage region is greater than eight channels (as in memory 100 of fig. 1), and certainly greater than six channels (as in memory 300 of fig. 3), so the bit density of memory 400 is still improved relative to the example of fig. 1 despite the top select gate cut, and the bit density of memory 400 is still improved relative to the example of fig. 3 despite the addition of the cut. The overall improvement in bit density is about 10%.

The finger storage area width of memory 400 of fig. 4 is doubled compared to memory 300 of fig. 3. However, the bit line pitch, channel pitch, finger storage region length, and page size are the same for the

memories

300, 400 of fig. 3 and 4. This can be achieved by forming the bit lines using quad imaging, as in fig. 3. This means that the memory 400 of fig. 4 has the same increased throughput and shortened t_R、t_PGMAs described in connection with fig. 3.

FIG. 5 is a flow diagram of a routine 500 for forming a three-dimensional memory as described in any of the embodiments of FIG. 2, FIG. 3, or FIG. 4. It should be appreciated that in some instances, the order of the steps in the routine 500 may be changed. Further, in some instances, steps of routine 500 may be omitted, other steps may be added, or a combination of both.

In block 510, a stack of layers is formed on a top surface of a substrate. The formation of the stack of layers may involve known deposition techniques and processes including, but not limited to, Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), and Physical Vapor Deposition (PVD). The stacked layers may include alternating stacked buffer layers and stacked conductor layers. The buffer layer may include a buffer material, such as an oxide material, e.g., silicon dioxide. The stacked layer conductor layer may include a gate metal for connecting to a word line of the memory device.

In block 520, a plurality of channels are formed in the stack of layers. The channel may be formed in a depth direction extending from a top surface of the stacked layers to a top surface of the substrate. The channel may be formed using any conventional process known in the art, such as imaging and/or dry or wet etching processes.

In block 530, a string of memory cells is formed in each of the channels. Forming the memory cell may involve depositing layers along an inner surface of the channel. For example, in the case of a charge trapping flash NAND device, each of the oxide layers and the charge trapping layer between the oxide layers may be deposited over the inner surface of the channel to form a string of memory cells. Each memory cell includes a gate that controls access to the data stored in the cell.

In block 540, connections are formed on a top surface of each channel. Forming the connection may involve filling the trench with a semiconductor material (such as polysilicon), with a conductive metal, or both, thereby electrically connecting the trench with the bit line to be formed.

In block 550, a plurality of bit lines are formed over the channels. The bit lines may be arranged to extend in a vertical direction from one gate gap separating finger storage regions of the memory device to another gate gap. Further, the bit lines may be arranged to have a bit line pitch that allows a corresponding one (but not more) of the electrical connections connecting each bit line to the channel. This can be achieved by using quadruple imaging to form the bit lines.

In some examples, a top select gate cut may be provided in a middle row of finger storage regions that extends in a direction perpendicular to the length of the bit line. The cuts separate the bitlines between different pages. In such an example, the plurality of bit lines formed at block 550 may connect more than one channel contact. The number of channel contacts to which each bit line is connected is limited by the number of pages into which the width of the finger storage region is divided in the vertical direction.

In operation, a given memory cell of a memory device can be accessed by activating a single bit line connected above to a channel of the given memory cell and activating a word line connected to the same channel at a predetermined depth (e.g., a particular layer of the stack of layers into which the channel is formed). A given cell to be accessed is a cell at the intersection of the channel and the activated word line. Accessing a cell may involve reading data from the cell, programming data to the cell, or a combination of both.

The above examples generally describe channel and bit line layouts for a single finger storage region of a memory device. However, one skilled in the art will readily recognize that the same techniques and principles may be extended to other finger storage regions of the same memory device, where the memory device may include a plurality of finger storage regions having a one-to-one correspondence between bit lines and channel holes. In some such examples, the plurality of finger storage areas may be positioned horizontally adjacent to each other along the X-direction, vertically adjacent to each other along the Y-direction, or both.

The above examples generally describe a layout of six or eight channel holes. However, one skilled in the art will readily recognize that the same techniques or principles may be applied to produce fewer channel holes coupled to fewer bit lines, such as seven channel holes coupled to seven bit lines.

The above examples generally describe a layout of channel holes placed in a zigzag pattern, wherein the channel holes are offset from each other in an alternating manner along the vertical or Y-direction. In essence, the zigzag pattern can be thought of as a series of diagonal lines, each line having a length of two channel holes. In other examples, the channel holes may be placed with other channel hole layouts, such as along a series of longer diagonals or other patterns that maximize the density of channel holes within a finger storage region of a memory device.

The above examples generally describe the application of example embodiments to a three-dimensional charge trapping flash NAND memory. However, it should be appreciated that the same concepts and principles can be applied to other types of three-dimensional memories that utilize channel holes to connect rows of bit lines to strings of memory cells that are built within or along the edges of the channel holes.

Although the present disclosure has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A three-dimensional memory, comprising:

a plurality of bit lines, each bit line having a length extending in a first direction;

a first finger storage area having:

a first end defined by a first gate gap extending in a second direction perpendicular to the first direction;

a second end defined by a second gate slit extending in the second direction; and

a width extending between the first and second ends along the first direction, an

A first plurality of channel holes located at the first finger storage region of the three-dimensional memory, each of the first plurality of channel holes extending in a depth direction perpendicular to each of the first and second directions and connected to a corresponding one of the plurality of bit lines.

2. The three-dimensional memory of claim 1, wherein the first finger storage region comprises any one of:

eight channel holes connected to the eight bit lines in a one-to-one correspondence;

seven channel holes connected to the seven bit lines in a one-to-one correspondence; or

Six channel holes connected to the six bit lines in a one-to-one correspondence.

3. The three-dimensional memory of claim 1, wherein the bit lines are configured to have a reduced bit line pitch using quad imaging.

4. The three-dimensional memory of claim 1, wherein each of the first and second gate apertures is positioned to separate the first finger storage region from an adjacent finger storage region along the first direction.

5. The three-dimensional memory of claim 1, further comprising:

a second finger storage region adjacent to the first finger storage region and separated from the first finger storage region by the first gate slit; and

a second plurality of channel holes located at the second finger storage region, each of the second plurality of channel holes extending in the depth direction and connected to a corresponding one of the plurality of bit lines.

6. The three-dimensional memory of claim 1, wherein the first plurality of channel holes are disposed in a zigzag pattern along the first direction.

7. The three-dimensional memory of claim 1, wherein the three-dimensional memory is a Charge Trap Flash (CTF) NAND memory.

8. A method of forming a three-dimensional memory comprising a plurality of finger storage regions, each finger storage region having a width extending along a first direction and having first and second ends defined by respective first and second gate apertures extending along a second direction perpendicular to the first direction, the method comprising:

forming, for a first finger storage region, a first plurality of channel holes, each channel hole of the first plurality of channel holes extending in a depth direction perpendicular to each of the first and second directions; and

forming a plurality of bit lines over the first plurality of channel holes, wherein each bit line is connected to a corresponding one of the first plurality of channel holes.

9. The method of claim 8, wherein forming a first plurality of channel holes comprises forming eight channel holes, and wherein forming a plurality of bit lines comprises forming eight bit lines.

10. The method of claim 8, wherein forming a first plurality of channel holes comprises forming six channel holes, and wherein forming a plurality of bit lines comprises forming six bit lines.

11. The method of claim 8, wherein the bit lines are formed using quad imaging.

12. The method of claim 8, further comprising: forming a second plurality of channel holes for a second finger storage region separated from the first finger storage region by the first gate slit, each of the second plurality of channel holes extending in the depth direction, wherein the plurality of bit lines are formed over the second plurality of channel holes, wherein each bit line is connected to a corresponding one of the second plurality of channel holes.

13. A three-dimensional memory, comprising:

a first finger storage area having:

a width extending along the first direction, an

A first plurality of channel holes located at the first finger storage region of the three-dimensional memory, each channel hole of the first plurality of channel holes extending along a depth direction perpendicular to each of the first direction and the second direction, the first plurality of channel holes comprising:

a medial channel hole positioned along a cut, the cut having a length extending in the second direction;

a first subset of the first plurality of channel holes located in a first page of the three-dimensional memory between the first gate aperture and the cutout; and

a second subset of the first plurality of channel holes located in a second page of the three-dimensional memory between the second gate aperture and the cutout;

wherein each channel hole of the first subset of the first plurality of channel holes is connected to a corresponding one of the plurality of bit lines, and wherein each channel hole of the second subset of the first plurality of channel holes is connected to a corresponding one of the plurality of bit lines.

14. The three-dimensional memory of claim 13, wherein the cut has a depth of three write lines.

15. The three-dimensional memory of claim 13, wherein a first plurality of channel holes comprises thirteen channel holes, and wherein each of the first subset and the second subset of the first plurality of channel holes comprises six channel holes.

16. The three-dimensional memory of claim 13, wherein each of the first page and the second page has a finger storage region width equal to six channel holes.

17. The three-dimensional memory of claim 13,

wherein a first bit line of the plurality of bit lines is connected to each of a channel hole closest to the first gate slit and a channel hole closest to the second gate slit,

wherein a second bit line of the plurality of bit lines is connected to each of a channel hole second proximate to the first gate slit and a channel hole second proximate to the second gate slit,

wherein a third bit line of the plurality of bit lines is connected to each of the channel hole third proximate to the first gate slit and the channel hole third proximate to the second gate slit,

wherein a fourth bit line of the plurality of bit lines is connected to each of a fourth channel hole proximate to the first gate slit and a fourth channel hole proximate to the second gate slit,

wherein a fifth bit line of the plurality of bit lines is connected to each of a channel hole of a fifth proximity to the first gate slit and a channel hole of a fifth proximity to the second gate slit, and

wherein a sixth bit line of the plurality of bit lines is connected to each of a sixth channel hole proximate to the first gate slit and a sixth channel hole proximate to the second gate slit.

18. The three-dimensional memory of claim 13, wherein the plurality of bit lines are arranged along the second direction in the following order: a first bit line, a third bit line, a fifth bit line, a second bit line, a fourth bit line, and a sixth bit line.

19. A method of operating a three-dimensional memory having one or more finger storage regions, each finger storage region having a width extending in a first direction between a first end defined by a first gate slit extending in a second direction perpendicular to the first direction and a second end defined by a second gate slit extending in the second direction, each finger storage region having a plurality of channel holes, each channel hole extending in a depth direction perpendicular to each of the first and second directions and connected to a plurality of word lines placed in the depth direction, the method comprising:

activating a single bit line, wherein the activated bit line is connected to only one channel hole of the finger storage region; and

activating a word line connected to the only one channel, thereby accessing a cell located at an intersection between the only one channel and the activated word line.