CN112583521B

CN112583521B - Decoding method and device, decoding equipment, terminal equipment and network equipment

Info

Publication number: CN112583521B
Application number: CN201910924868.3A
Authority: CN
Inventors: 童佳杰; 张华滋; 李榕; 刘小成; 王俊
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-09-27
Filing date: 2019-09-27
Publication date: 2022-04-05
Anticipated expiration: 2039-09-27
Also published as: CN112583521A

Abstract

The application provides a decoding method, a decoding device, decoding equipment, terminal equipment and network equipment, and belongs to the technical field of communication. The method comprises the following steps: the data packet is decoded by the first decoder group, when the first decoder group fails in decoding, if the buffer of the second decoder in the second decoder group is full, the data packet is directly discarded, otherwise, the data packet is decoded by the second decoder group with decoding performance superior to that of the first decoder group. According to the method and the device, when the decoding of the first decoder group fails and the cache of the second decoder in the second decoder group is full, the data packet submitted after the decoding of the first decoder group fails is directly discarded, so that the normal work of the first decoder group can be ensured, and the decoding efficiency of the first decoder group is further ensured.

Description

Decoding method and device, decoding equipment, terminal equipment and network equipment

Technical Field

The present application relates to the field of communications technologies, and in particular, to a decoding method, an apparatus, a decoding device, a terminal device, and a network device.

Background

When a signal needs to be transmitted in a communication system, the signal needs to be correspondingly processed through channel coding, an analog signal and the like are converted into a digital signal which is easy to transmit, and the occurrence of error codes in the transmission process is avoided as much as possible. Decoding is the inverse process of encoding and may convert a digital signal having a particular meaning into an output signal in the form of an analog signal to represent a certain state of the circuit for subsequent analysis. Decoding is one of the key technologies of a communication system, and has an important effect on improving the sensitivity and the anti-interference capability of the system.

The existing commonly used decoder is a single-performance decoder, but because the decoding performance and throughput of the single-performance decoder can not be adjusted, the decoder of the same code can be divided into a plurality of different designs, firstly, the light decoder with relatively poor decoding performance and high decoding speed decodes, if the decoding fails, the decoder capability is upgraded to the re-decoder with relatively good decoding performance and low decoding speed at the next stage, if the decoding fails, the re-decoder is upgraded until the re-decoder with the highest stage is upgraded, namely, the adaptive decoder.

The maximum time delay of the existing adaptive decoder is not controllable, the distributed task can not be guaranteed to be completed within a fixed time, when the adaptive decoder is applied to a communication system with the maximum time delay requirement, the adaptive decoder can only be used as a means for reducing average power consumption, and because the decoding time of the re-decoder is long, if a plurality of decoding errors occur continuously, the re-decoder can not process in time, and a new data packet can be blocked from entering, so that the light decoder is suspended to stop working, and the decoding efficiency can not be guaranteed.

Disclosure of Invention

The embodiment of the application provides a decoding method, a decoding device, decoding equipment, terminal equipment and network equipment, and can solve the problems that in the prior art, decoding efficiency cannot be guaranteed and throughput is limited, so that an adaptable decoder can be really applied to a decoding system with the maximum delay requirement. The technical scheme is as follows:

in a first aspect, a decoding method is provided, and the method includes:

decoding the received data packet by a first decoder group, the first decoder group comprising at least one first decoder;

discarding the data packet when the first decoder group fails to decode the data packet and a buffer of a second decoder in a second decoder group is full, the second decoder group comprising at least one second decoder having decoding performance superior to that of the first decoder;

and when the first decoder group fails to decode the data packet and the buffer of the second decoder in the second decoder group is not full, decoding the data packet through the second decoder group.

In the implementation process, the data packet is decoded by the first decoder group, when the first decoder group fails to decode the data packet, if the cache of the second decoder in the second decoder group is full, the data packet submitted after the decoding failure of the first decoder group is directly discarded, otherwise, the data packet is decoded by the second decoder group with decoding performance superior to that of the first decoder group, so that the normal work of the first decoder group can be ensured, and the decoding efficiency of the first decoder group is further ensured.

In a first possible implementation form of the first aspect, the method further comprises any one of:

when the first decoder group fails to decode the data packet, the buffer memory of the second decoder group is detected.

In the above implementation process, after the first decoder group fails to decode the data packet, the buffer of the second decoder group is checked, so that the data packet which fails to decode can be processed under the condition that the buffer of the decoder group with better decoding performance is not full, and the data packet which fails to decode can be discarded under the condition that the buffer of the decoder group with better decoding performance is full, thereby ensuring normal decoding and also ensuring decoding efficiency.

In a second possible implementation manner of the first aspect, before the decoding, by the first decoder group, the received data packet, the method further includes:

self-checking the data packet;

when the verification passes, outputting a verification result;

when the check fails, the step of decoding the received data packet by the first decoder group is executed.

In the implementation process, before decoding, self-checking is carried out on the data packet, decoding is not needed if the self-checking is passed, and decoding is carried out if the self-checking is not passed, so that the decoding efficiency can be improved on the premise of ensuring the decoding performance.

In a third possible implementation manner of the first aspect, the decoding performance of each first decoder in the first decoder group is the same.

In the above implementation process, the decoding performance of each first decoder in the first decoder group is the same, so that the decoding efficiency balance inside the decoder group can be realized, and further, when a data packet is decoded, the decoding capability is controllable.

In a fourth possible implementation manner of the first aspect, the decoding performance of each second decoder in the second decoder group is the same.

In the above implementation process, the decoding performance of each second decoder in the second decoder group is the same, so that the decoding efficiency balance inside the decoder group can be realized, and further, when the data packet is decoded, the decoding capability is controllable.

In a fifth possible implementation manner of the first aspect, after discarding the data packet when the first decoder group fails to decode the data packet and a buffer of the second decoder in the second decoder group is full, the method further includes:

the data packet is included in the decoding failure row.

In the implementation process, after the decoding fails, the data packet is counted into a decoding failure row column, the number of the data packets with decoding failure can be counted, and then the data such as the bad packet rate and the like are counted so as to analyze the decoding condition.

In a second aspect, a decoding method is provided, which includes:

decoding the received data packet by a decoder bank, the decoder bank including at least one decoder;

when the decoder group fails to decode the data packet, switching a first decoding mode of a decoder in the decoder group to a second decoding mode;

and decoding the data packets with failed decoding based on the decoder group in the second decoding mode, and discarding the data packets when the decoder group has failed decoding of a target number of data packets in a decoding window.

In the implementation process, the data packet is decoded by the decoder group, when the decoding fails, the decoder in the decoder group is switched to the decoding mode with better decoding performance, the data packet is decoded continuously, and when the decoding of the data packets with the target number in the decoding window fails, the data packet is discarded, so that the decoding efficiency and the throughput of the decoder group can be ensured.

In a first possible implementation manner of the second aspect, before the switching the first decoding mode to the second decoding mode of the decoders in the decoder group, the method further includes:

determining an available number of iterations of the decoder group within the decoding window;

when the available iteration number is not 0, executing the step of switching the first decoding mode of the decoder in the decoder group to the second decoding mode;

when the number of available iterations is 0, the packet is discarded.

In the implementation process, before switching the decoding mode, the available iteration times of the decoder group in the decoding window is determined, mode switching is performed if the iteration times are not 0, otherwise, the data packet is directly discarded, and the decoding efficiency and throughput of the decoder group can be ensured.

In a second possible implementation manner of the second aspect, before the decoding, by the decoder group, the received data packet, the method further includes:

self-checking the data packet;

when the verification passes, outputting a verification result;

and when the check fails, executing the pass decoder group to decode the received data packet.

In a third aspect, a decoding apparatus is provided for performing the above decoding method. Specifically, the decoding device includes a functional module for executing the decoding method provided by the first aspect or any optional manner of the first aspect.

In a fourth aspect, a decoding apparatus is provided for performing the above decoding method. Specifically, the decoding device includes a functional module for executing the decoding method provided by the second aspect or any optional manner of the second aspect.

In a fifth aspect, there is provided a decoding apparatus comprising:

a plurality of decoder groups, wherein a distributor is connected between every two decoder groups, and each decoder group comprises at least one decoder;

for a first decoder group of any two connected decoder groups, the first decoder group is used for decoding the received data packet;

for a second decoder group of any two connected decoder groups, the second decoder group is used for decoding the data packet after the first decoder group fails to decode the data packet;

for the distributor connected between every two decoder groups, the distributor is used for detecting the buffer memory of the second decoder group and recording the data packet into a decoding failure row and column;

the decoders in the second decoder group have better decoding performance than the decoders of the first decoder group.

In a sixth aspect, there is provided a decoding apparatus comprising:

a plurality of decoder groups, the decoder groups including at least one decoder;

the decoder group is used for decoding the received data packet based on the decoder group in a first decoding mode;

the decoder group is further used for switching the first decoding mode of a decoder in the decoder group to a second decoding mode when the decoder group fails to decode the data packet;

the decoder group is further used for decoding the data packet which is failed in decoding based on the decoder group in the second decoding mode.

In a seventh aspect, a terminal device is provided, where the terminal device includes one or more transceivers for transceiving data packets, and a plurality of decoder sets for performing the above decoding method to decode the data packets.

In an eighth aspect, a network device is provided, which includes one or more transceivers for transceiving data packets and a plurality of decoder sets for performing the above decoding method to decode the data packets.

The technical scheme provided by the embodiment of the application has the following beneficial effects:

the data packet is decoded by the first decoder group, when the decoding of the first decoder group fails and the buffer memory of the second decoder in the second decoder group is full, the data packet is directly discarded, otherwise, the data packet is decoded by the second decoder group with decoding performance superior to that of the first decoder group, so that the normal work of the first decoder group can be ensured, and the decoding efficiency of the first decoder group is further ensured; the data packets are decoded by the decoder group, when the decoding fails, the decoders in the decoder group are switched to a decoding mode with better decoding performance, the data packets are decoded continuously, and when the decoding of the data packets with the target number in the decoding window fails, the data packets are discarded, so that the decoding efficiency and the throughput of the decoder group can be ensured.

Drawings

Fig. 1 is a schematic diagram illustrating an embodiment of a decoding method according to the present disclosure;

fig. 2 is a schematic structural diagram of a terminal device provided in an embodiment of the present application;

FIG. 3 is a block diagram illustrating a network device 300 in accordance with an example embodiment;

FIG. 4 is a block diagram of a decoding system according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a decoding apparatus according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating a combined structure of a light decoder and a heavy decoder according to an embodiment of the present application;

fig. 7 is a flowchart of a decoding method according to an embodiment of the present application;

fig. 8 is a schematic diagram illustrating a variation curve of a bit error rate with a signal-to-noise ratio of a decoder with different decoding performances according to an embodiment of the present application;

fig. 9 is a graph illustrating throughput versus signal-to-noise ratio of a decoder with different decoding performance according to an embodiment of the present application;

fig. 10 is a graph illustrating a variation of a bit error rate with a signal-to-noise ratio of a decoder with different decoding performance according to an embodiment of the present application;

fig. 11 is a graph illustrating throughput versus signal-to-noise ratio of a decoder with different decoding performance according to an embodiment of the present application;

fig. 12 is a flowchart of a decoding method according to an embodiment of the present application;

FIG. 13 is a schematic view of a fixed starting position window provided in an embodiment of the present application;

FIG. 14 is a schematic view of a sliding window provided by an embodiment of the present application;

FIG. 15 is a schematic diagram of a decoding apparatus according to an embodiment of the present application;

fig. 16 is a schematic diagram of a decoding apparatus according to an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The method provided by the embodiment of the present application may be applied to satellite communication, the release 17 (R17) standard and other future mobile phone system fifth-generation (5G) network standards, and fig. 1 is a schematic diagram of an implementation environment of a decoding method provided by the embodiment of the present application, and referring to fig. 1, the implementation environment includes: terminal device 101 and network device 102.

Terminal equipment 101, may refer to User Equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, or a user equipment. The access terminal may be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device with wireless communication capability, a computing device or other processing device connected to a wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a 5G network or a terminal device in a future evolved Public Land Mobile Network (PLMN), a smart home device, and so on. By way of example and not limitation, in the embodiments of the present application, the terminal device may also be a wearable device. Wearable equipment can also be called wearable intelligent equipment, is the general term of applying wearable technique to carry out intelligent design, develop the equipment that can dress to daily wearing, like glasses, gloves, wrist-watch, dress and shoes etc.. A wearable device is a portable device that is worn directly on the body or integrated into the clothing or accessories of the user. The wearable device is not only a hardware device, but also realizes powerful functions through software support, data interaction and cloud interaction. The generalized wearable smart device includes full functionality, large size, and can implement full or partial functionality without relying on a smart phone, such as: smart watches or smart glasses and the like, and only focus on a certain type of application functions, and need to be used in cooperation with other devices such as smart phones, such as various smart bracelets for physical sign monitoring, smart jewelry and the like. The intelligent household equipment can be air conditioners, televisions, water heaters and other household equipment with communication capacity. The terminal device 101 may communicate with the network device 102 through a wireless network or a wired network, the terminal device 101 may be one or more, and multiple terminal devices may also communicate with each other through a wireless network or a wired network, which is not limited in this embodiment of the application.

The network device 102 may be at least one of a router, a base station (e.g., a 5G base station), a server, or a wireless fidelity (WiFi) device. The network device 102 may communicate with the terminal device 101 through a wireless network or a wired network, other network devices that need to be decoded may also apply the method provided by the present application, the network device 102 may be one or more, and the embodiment of the present application does not limit the type and number of the network devices.

Fig. 2 is a schematic structural diagram of a terminal device according to an embodiment of the present application, where the terminal device may be configured to execute decoding methods provided in the following embodiments. Referring to fig. 2, the terminal device 200 includes:

the terminal device 200 may include Radio Frequency (RF) circuitry 210, memory 220 including one or more computer-readable storage media, an input unit 230, a display unit 240, a sensor 250, audio circuitry 260, a wireless fidelity (WiFi) module 270, a processor 280 including one or more processing cores, and a power supply 290. Those skilled in the art will appreciate that the terminal device configuration shown in fig. 2 is not intended to be limiting of terminal devices and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components. Wherein:

the RF circuit 210 may be used for receiving and transmitting signals during a message transmission or call, and in particular, for receiving downlink information of a base station and then processing the received downlink information by the one or more processors 280; in addition, data relating to uplink is transmitted to the base station. In general, RF circuitry 210 includes, but is not limited to, an antenna, at least one amplifier, a tuner, one or more oscillators, a Subscriber Identity Module (SIM) card, a transceiver, a coupler, a Low Noise Amplifier (LNA), a duplexer, and the like. In addition, the RF circuitry 210 may also communicate with networks and other devices via wireless communications. The wireless communication may use any communication standard or protocol, including but not limited to global system for mobile communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Message Service (SMS), etc.

The memory 220 may be used to store software programs and modules, and the processor 280 executes various functional applications and data processing by operating the software programs and modules stored in the memory 220. The memory 220 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the terminal device 200, and the like. Further, the memory 220 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device. Accordingly, the memory 220 may also include a memory controller to provide the processor 280 and the input unit 230 access to the memory 220.

The input unit 230 may be used to receive input numeric or character information and generate keyboard, mouse, joystick, optical or trackball signal inputs related to user settings and function control. In particular, the input unit 230 may include a touch-sensitive surface 231 as well as other input devices 232. The touch-sensitive surface 231, also referred to as a touch display screen or a touch pad, may collect touch operations by a user (e.g., operations by a user on or near the touch-sensitive surface 231 using a finger, a stylus, or any other suitable object or attachment) thereon or nearby, and drive the corresponding connection device according to a predetermined program. Alternatively, the touch sensitive surface 231 may comprise two parts, a touch detection device and a touch controller. The touch detection device detects the touch direction of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch sensing device, converts it to touch point coordinates, and then provides the touch point coordinates to the processor 280, and can receive and execute commands from the processor 280. In addition, the touch-sensitive surface 231 may be implemented in various types, such as resistive, capacitive, infrared, and surface acoustic wave. The input unit 230 may comprise other input devices 232 in addition to the touch sensitive surface 231. In particular, other input devices 232 may include, but are not limited to, one or more of a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like.

The display unit 240 may be used to display information input by or provided to the user and various graphic user interfaces of the terminal apparatus 200, which may be configured by graphics, text, icons, video, and any combination thereof. The display unit 240 may include a display panel 241, and optionally, the display panel 241 may be configured in the form of a Liquid Crystal Display (LCD), an organic light-emitting diode (OLED), or the like. Further, the touch-sensitive surface 231 may overlay the display panel 241, and when the touch-sensitive surface 231 detects a touch operation thereon or nearby, the touch operation is transmitted to the processor 280 to determine the type of the touch event, and then the processor 280 provides a corresponding visual output on the display panel 241 according to the type of the touch event. Although in FIG. 2, touch-sensitive surface 231 and display panel 241 are shown as two separate components to implement input and output functions, in some embodiments, touch-sensitive surface 131 may be integrated with display panel 141 to implement input and output functions.

The terminal device 200 may also include at least one sensor 250, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor may include an ambient light sensor that may adjust the brightness of the display panel 241 according to the brightness of ambient light, and a proximity sensor that may turn off the display panel 241 and/or the backlight when the terminal device 200 is moved to the ear. As one of the motion sensors, the gravity acceleration sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when the mobile phone is stationary, and can be used for applications of recognizing the posture of the mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which can be configured on the terminal device 200, detailed descriptions thereof are omitted.

Audio circuitry 260, speaker 261, and microphone 262 may provide an audio interface between a user and terminal device 200. The audio circuit 260 may transmit the electrical signal converted from the received audio data to the speaker 261, and convert the electrical signal into a sound signal by the speaker 261 and output the sound signal; on the other hand, the microphone 262 converts the collected sound signal into an electric signal, which is received by the audio circuit 260 and converted into audio data, which is then processed by the audio data output processor 280, and then transmitted to, for example, another terminal device via the RF circuit 210, or output to the memory 220 for further processing. The audio circuitry 260 may also include an earbud jack to provide communication of peripheral headphones with the terminal device 200.

WiFi belongs to short-distance wireless transmission technology, and the terminal device 200 can help the user send and receive e-mails, browse web pages, access streaming media, etc. through the WiFi module 270, and it provides wireless broadband internet access for the user. Although fig. 2 shows the WiFi module 270, it is understood that it does not belong to the essential constitution of the terminal device 200, and may be omitted entirely as needed within the scope not changing the essence of the invention.

The processor 280 is a control center of the terminal device 200, connects various parts of the entire cellular phone using various interfaces and lines, and performs various functions of the terminal device 200 and processes data by operating or executing software programs and/or modules stored in the memory 220 and calling data stored in the memory 220, thereby performing overall monitoring of the cellular phone. Optionally, processor 280 may include one or more processing cores; optionally, the processor 280 may integrate an application processor, which mainly handles operating systems, user interfaces, application programs, etc., and a modem processor, which mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into processor 280.

Terminal device 200 also includes a power supply 290 (e.g., a battery) for powering the various components, which may optionally be logically coupled to processor 280 via a power management system to manage charging, discharging, and power consumption management functions via the power management system. The power supply 290 may also include any component of one or more dc or ac power sources, recharging systems, power failure detection circuitry, power converters or inverters, power status indicators, and the like.

Terminal device 200 also includes one or more decoder banks for performing decoding methods described below, optionally, the one or more decoder banks may be part of processor 280 or may be one or more decoder chipsets separate from processor 280.

Although not shown, the terminal device 200 may further include a camera, a bluetooth module, and the like, which will not be described herein. Specifically, in this embodiment, the display unit of the terminal device is a touch screen display, the terminal device further includes a memory, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for executing the decoding method described below.

Fig. 3 is a block diagram illustrating a network device 300 in accordance with an example embodiment. For example, the network device 300 may be provided as a router, a base station (e.g., a 5G base station), a server, or a WiFi device. Referring to fig. 3, network device 300 includes a processing component 301 that further includes one or more processors, and memory resources, represented by memory 302, for storing instructions, such as applications, that are executable by processing component 301. The application programs stored in memory 302 may include one or more modules that each correspond to a set of instructions. Further, the processing component 301 is configured to execute instructions to perform the decoding method described below.

The network device 300 further comprises one or more decoder groups for performing the decoding methods described below, optionally the one or more decoder groups may be part of the processing component 301 or may be one or more decoder chipsets separate from the processing component 301.

Network device 300 may also include a power component 303 configured to perform power management of network device 300, a wired or wireless network interface 304 configured to connect network device 300 to a network, and an input output (I/O) interface 305. Network device 300 may operate based on an operating system, such as Windows Server, stored in memory 302^TM，Mac OS X^TM，Unix^TM,Linux^TM，FreeBSD^TMOr the like.

Fig. 4 is a schematic architecture diagram of a decoding system according to an embodiment of the present application, and referring to fig. 4, the decoding system may include: the system comprises modules such as a data source, a transmitter baseband processor, a radio frequency transmission module, a radio frequency receiving module, a receiver baseband processor, a data receiver, an encoder and a decoder. The data source can be a signal source of a transmitter baseband processor, the transmitter baseband processor can process data to be transmitted, the data is changed into a transmission signal through means of coding, modulation and the like, the radio frequency transmission module can load a signal output by the baseband processor to a transmission carrier frequency through a radio frequency component and transmit the signal, the radio frequency receiving module can convert the received radio frequency signal into a signal required by the receiver baseband processor and transmit the signal to the receiver baseband processor, the receiver baseband processor can process the baseband signal transmitted by the radio frequency receiving module and demodulate and decode the signal, a data receiver can receive the signal processed by the receiver baseband processor, and the signal is the same as the signal transmitted by the data source after being successfully decoded by the decoding module.

Fig. 5 is a schematic structural diagram of a decoding apparatus provided in an embodiment of the present application, and referring to fig. 5, the decoding apparatus includes multiple types of decoders, for example, a light decoder and a heavy decoder, which may be logic concepts, and in a specific implementation process, the light decoder and the heavy decoder may be implemented by different circuits, or by different configuration modes of a logic circuit. The light decoder has relatively poor decoding performance but high decoding speed, the re-decoder has relatively good decoding performance but low decoding speed, the light decoder and the re-decoder are connected through a distributor, the distributor transmits data packets, and the distributor can distribute the data packets which are decoded by the light decoder and fail to be decoded to the re-decoder.

In the design process of the decoder of the same channel, different design methods can be generated according to different working environments and different requirements on performance, throughput and maximum delay of decoding, for example, a light decoder and a heavy decoder are two different decoder design methods, for each type of decoder, the decoders with the same decoding performance can be divided into the same decoder group according to the requirements, one or more decoders can be arranged in one decoder group, for example, a plurality of light decoders can be divided into one decoder group, and a plurality of heavy decoders can be divided into one decoder group.

For example, a decoding device may include N light decoders and M heavy decoders, where N and M are positive integers greater than or equal to 1, and the specific values of N and M may be the same or different. As shown in fig. 5, the light decoder #1 may be a light decoder labeled as No. 1, the light decoder #2 may be a light decoder labeled as No. 2, the light decoder # N may be a light decoder labeled as N, the heavy decoder #1 may be a heavy decoder labeled as No. 1, the heavy decoder #2 may be a heavy decoder labeled as No. 2, the heavy decoder # N may be a heavy decoder labeled as N, and so on.

When decoding a data packet, firstly decoding the data packet by a light decoder, after the data enters the light decoder, caching the data as log-likelihood ratio (LLR) in a relevant storage unit, then decoding the data by a light decoder core, after the decoding is finished, checking a decoding result, if the decoding result is checked correctly, directly outputting the result, if the decoding result is checked incorrectly, sending the data packet with the incorrect checking result to a distributor, detecting the cache of the heavy decoder by the distributor, if the cache is full, namely the heavy decoder is busy, discarding the data packet with the incorrect checking result, if the cache is not full, the distributor can distribute the data packet with the incorrect checking result of the decoding result of the light decoder to the heavy decoder with the not full cache, namely idle cache, and decoding the data packet by the heavy decoder core, after decoding, checking the decoding result, if the decoding result is correct, outputting the result, otherwise, inquiring whether a next-stage re-decoder exists, if so, sending the data packet to a distributor of the next-stage re-decoder, and if not, directly discarding the data packet.

It should be noted that the light decoder and the heavy decoder may be present as a combination of algorithms in pairs, the combination of the light decoder and the heavy decoder may be more than one pair, and the number of the combination of the light decoder and the heavy decoder is not limited in the embodiment of the present application. When there are multiple pairs of combinations of light and heavy decoders that appear in series, the light and heavy in the light and heavy decoders are opposite concepts, and the light decoder in the next combination of light and heavy decoders may be used as the heavy decoder in the previous combination of light and heavy decoders, as shown in figure 6, figure 6 is a schematic diagram of a combined structure of a light decoder and a heavy decoder according to an embodiment of the present application, as shown in fig. 6, the decoding capability #1 of the decoder group is the lightest decoder, the decoding capability #2 of the decoder group is the lightest decoder, the decoding capability is stronger than the decoding capability #1 of the decoder group, the decoding capability # N of the decoder group is the heaviest decoder, the decoding capability is the strongest, where N is a positive integer greater than or equal to 2, and the decoder group decoding capability #2 is both a heavy decoder of the light-heavy decoder combination 1 and a light decoder of the light-heavy decoder combination 2.

Fig. 7 is a flowchart of a decoding method provided in an embodiment of the present application, which is only illustrated by interaction between decoder combination distributors in a decoding apparatus, and referring to fig. 7, the method includes:

701. the decoding device decodes the received data packet through a first decoder group, wherein the first decoder group comprises at least one first decoder, and the decoding performance of each first decoder in the first decoder group is the same.

702. When the first decoder group fails to decode the data packet, the distributor in the decoding apparatus detects whether the buffer of the second decoder group is full, when the buffer of the second decoder in the second decoder group is full, step 703 is performed, and when the buffer of the second decoder in the second decoder group is not full, step 704 is performed, the second decoder group includes at least one second decoder having decoding performance superior to that of the first decoder, and the decoding performance of each second decoder in the second decoder group is the same.

In this embodiment of the present application, only the determination of the above-mentioned cache performed by the distributor is taken as an example for explanation, in some possible implementation manners, the process may also be determined by a processor in another form, and this is not limited in this embodiment of the present application.

703. The distributor in the decoding device discards the data packet and counts the data packet into a decoding failure row and column.

The data packets are counted in the decoding failure row and column, so that the number of the data packets which fail in decoding can be counted, and the data such as the packet error rate of the decoding equipment can be further obtained, and the performance of the decoding equipment can be analyzed conveniently.

704. The decoding device decodes the data packet through the second decoder group.

When polar code is used for channel coding and a Successive Cancellation (SC) algorithm is used for decoding, the decoding device performs decoding on the received data packet through a first decoder group, and the method further includes:

the decoding equipment carries out self-checking on the data packet; when the check is passed, outputting the check result, and when the check is not passed, executing the step of passing the first decoder group to decode the data packet.

The self-checking can directly quantize the signal, the quantized result is higher than the threshold value, namely the output is 1, otherwise, the output is 0, the output result of the self-checking can represent the state of the circuit, and therefore the output signal in the form of an analog signal is not required to be obtained through decoding to represent a certain state of the circuit. In the actual decoding process, when the receiver receives the data packet, the data packet is firstly sent to the self-checking module, and the self-checking module checks the data packet and then determines whether the decoding is needed.

According to the technical scheme, after the first decoder group fails in decoding, the buffer memory of the second decoder group is checked, when the buffer memory of the second decoder group is not full, the data packet failed in decoding can be decoded by the second decoder group with better decoding performance, but when the buffer memory of the second decoder group is full, the data packet failed in decoding is directly discarded by the distributor, normal work of the first decoder group can be guaranteed, the throughput efficiency of the first decoder group can be further guaranteed, decoding time delay can be controlled, the amount of decoding controllable time delay calculation units such as chip area, Field Programmable Gate Array (FPGA) logic number, Central Processing Unit (CPU) or Digital Signal Processor (DSP) number, occupied time and the like can be reduced, and cost is further reduced.

The method provided by the embodiment of the present application can be applied to decoding processes of polar codes, low-density parity-check (LDPC) codes, turbo codes (turbo codes), and decoders with various structures, and the embodiment of the present application does not limit which encoding and decoding method is specifically adopted. The following describes a specific implementation process of the decoding method in different application scenarios.

When polar codes are adopted for channel coding and decoding is carried out by adopting a cyclic redundancy check code-assisted successive cancellation list (CA-SCL) algorithm, the method comprises the following steps:

step one, decoding equipment decodes the received data packet through a CA-SCLx decoder group, wherein the CA-SCLx decoder group comprises at least one CA-SCLx decoder, and the decoding performance of each CA-SCLx decoder in the CA-SCLx decoder group is the same.

In this embodiment, the CA-SCLx decoder group may be used as the first decoder group, and the CA-SCLx decoder group is composed of M CA-SCLx decoders, where the CA-SCLx decoder is a light decoder, M is a positive integer greater than or equal to 1, x is a list (list) size of the decoder, and the larger the value of the list is, the stronger the decoding capability of the decoder is, the longer the decoding time is, and the specific values of M and x are not limited in this embodiment.

Step two, when the CA-SCLx decoder group fails to decode the data packet, the distributor in the decoding equipment detects whether the cache of the CA-SCLy decoder group is full, when the cache of the CA-SCLy decoder in the CA-SCLy decoder group is full, step three is executed, when the cache of the CA-SCLy decoder in the CA-SCLy decoder group is not full, step four is executed, the CA-SCLy decoder group comprises at least one CA-SCLy decoder with decoding performance superior to that of the CA-SCLx decoder, and the decoding performance of each CA-SCLy decoder in the CA-SCLy decoder group is the same.

In this embodiment, the CA-SCLy decoder group may be used as the second decoder group, and the CA-SCLy decoder group is composed of N CA-SCLy decoders, where the CA-SCLy decoder is a re-decoder, N is a positive integer greater than or equal to 1, y is a list size of the decoder, a value of y is greater than a value of x, a cache (buff) depth of the CA-SCLy decoder is L packets, and L is a positive integer greater than or equal to 1, and specific values of N, y and L are not limited in this embodiment.

The number of the CA-SCLx decoder and the CA-SCLy decoder and the number ratio between the CA-SCLx decoder and the CA-SCLy decoder can be configured according to different requirements of throughput, working points and the like under different working environments. For example, in an operating environment requiring higher throughput, a larger number of CA-SCLx decoders and a smaller number of CA-SCLy decoders are required. By configuring the decoders according to the working environment, the excessive number of the decoders can be avoided, and the cost is reduced.

In a possible implementation manner, the distributor detects whether the cache of the CA-SCLy decoder in the CA-SCLy decoder group has reached the maximum value L, if it is detected that the cache has reached the maximum value L, step three is executed, and if it is detected that the cache has not reached the maximum value L, step four is executed.

And step three, a distributor in the decoding equipment discards the data packet and counts the data packet into a decoding failure row and column.

For the CA-SCLx decoder in the CA-SCLx decoder group, after the data packet failed in decoding is discarded, decoding can be continuously performed based on the newly received data packet without waiting for the CA-SCLy decoder in the CA-SCLy decoder group to release the decoding capability, so that the normal work of the CA-SCLx decoder can be ensured, the throughput efficiency of the CA-SCLx decoder can also be ensured, and the maximum delay of the decoding time can be controlled. On the basis of the throughput capability of the CA-SCLx decoder, the performance of the decoder is improved, so that when a signal-to-noise ratio (SNR) is close to a side with a higher Frame Error Rate (FER), that is, when the SNR is lower, the decoding performance is close to that of a light decoder, the decoding performance is improved, and when the SNR gradually increases, the decoding performance is gradually close to that of a heavy decoder.

And step four, decoding the data packet by the decoding equipment through the CA-SCly decoder group.

It should be noted that, when the cache of the CA-SCLy decoder in the CA-SCLy decoder group is not full, the data packet is pushed into the cache of the CA-SCLy decoder after the decoding of the CA-SCLx decoder fails, so that the data packet is decoded by the CA-SCLy decoder group in the following.

For example, 1 CA-SCL8 may be used as a first decoder, 1 CA-SCL32 may be used as a second decoder for explanation, see fig. 8 and fig. 9, fig. 8 is a schematic diagram of a variation curve of the bit error rate with the signal-to-noise ratio of a decoder with different decoding performance provided in this embodiment, and fig. 9 is a schematic diagram of a variation curve of the throughput with the signal-to-noise ratio of a decoder with different decoding performance provided in this embodiment, where N is 1024, K is 523, N is a code length, and K is an information bit number, it can be seen that a common adaptable decoder has no difference from the second decoder in performance, but in throughput, it is obviously changed with a change of SNR, throughput cannot be controlled, and a maximum delay controllable adaptable decoder is in a case of relatively low SNR. The performance will be between SCL32 and SCL8, but the throughput is guaranteed to be controllable, and thus the ability to adapt to communication systems where the maximum delay is controllable. When N is 256 and K is 139, see fig. 10 and fig. 11, fig. 10 is a graph illustrating a variation curve of the bit error rate with the signal-to-noise ratio of a decoder with different decoding performance provided in this embodiment of the present application, and fig. 11 is a graph illustrating a variation curve of the throughput with the signal-to-noise ratio of a decoder with different decoding performance provided in this embodiment of the present application, it can be seen that the simulation result when N is 256 and K is 139 has the same simulation conclusion as when N is 1024 and K is 523.

The technical scheme can control the total number of times of the SCLy decoder in the whole decoding process by configuring the number of the SCLx decoder and the SCLy decoder, further can ensure that the decoding of fixed number is completed in fixed time, and the purpose of controllable time delay is achieved.

When the LDPC is adopted for channel coding and the Belief Propagation (BP) iterative algorithm is adopted for decoding, the method comprises the following steps:

step one, decoding the received data packet by a decoding device through an iter-x decoder group, wherein the iter-x decoder group comprises at least one iter-x decoder, and the decoding performance of each iter-x decoder in the iter-x decoder group is the same.

In this embodiment, the iter-x decoder group may be used as a first decoder group, the iter-x decoder having an LDPC iteration number (iter) of x is set as a light decoder, the larger the iter value is, the stronger the decoding capability of the decoder is, and the longer the decoding time is, the iter-x decoder group is composed of M iter-x decoders, M is a positive integer greater than or equal to 1, and this embodiment of the present application does not limit specific values of M and x.

The iteration number may be a sum of the number of times that the decoder group decodes the data packet, and decoding one data packet by the decoder group may be referred to as one iteration.

Step two, when the group of the iter-x decoders fails to decode the data packet, a distributor in the decoding equipment detects whether the cache of the iter-y decoder group is full, when the cache of the iter-y decoder in the iter-y decoder group is full, step three is executed, when the cache of the iter-y decoder in the iter-y decoder group is not full, step four is executed, the iter-y decoder group comprises at least one iter-y decoder with decoding performance superior to that of the iter-x decoder, and the decoding performance of each iter-y decoder in the iter-y decoder group is the same.

In this embodiment, the iter-y decoder group may be used as a second decoder group, and an iter-y decoder with the number of iterations (iter) of LDPC being y is set as a re-decoder, and the iter-y decoder group is composed of N iter-y decoders, where the value of y is greater than the value of x, N is a positive integer greater than or equal to 1, the buff depth of the iter-y decoder is L packets, and L is a positive integer greater than or equal to 1.

The number of the iter-x decoder and the iter-y decoder and the number ratio between the iter-x decoder and the iter-y decoder can be configured according to different requirements of throughput, working points and the like under different working environments. By configuring the decoders according to the working environment, the excessive number of the decoders can be avoided, and the cost is reduced.

In a possible implementation manner, the distributor detects whether the cache of the iter-y decoder in the iter-y decoder group has reached the maximum value L, if the cache has reached the maximum value L, the third step is executed, and if the cache has not reached the maximum value L, the fourth step is executed.

For the iter-x decoder in the iter-x decoder group, after discarding the data packet with decoding failure, decoding can be continuously performed based on the newly received data packet without waiting for the iter-y decoder in the iter-y decoder group to release the decoding capability, so that the normal work of the iter-x decoder can be ensured, the throughput efficiency of the iter-x decoder can be ensured, and the decoding time is controllable. On the basis of the throughput capacity of the iter-x decoder, the performance of the decoder is improved, so that when the SNR is close to the side with higher FER, namely, the SNR is lower, the decoding performance is close to that of a light decoder, the decoding performance is improved, and when the SNR is gradually increased, the decoding performance is gradually close to that of a heavy decoder.

And step four, the decoding equipment decodes the data packet through the iter-y decoder group.

It should be noted that, when the buffer of the iter-y decoder in the iter-y decoder group is not full, the packet is pushed into the buffer of the iter-y decoder after the decoding of the iter-x decoder fails, so that the packet is decoded by the iter-y decoder group in the following.

The technical scheme can control the total number of times of the decoder with the iterative iter being y in the whole decoding process through the configuration of the numbers of the iter-x decoder and the iter-y decoder, further can ensure that the decoding with the fixed number is completed in fixed time, and the purpose of controllable time delay is achieved.

When turbo codes are adopted for channel coding and BP iterative algorithm is adopted for decoding, the method comprises the following steps:

In this embodiment, the iter-x decoder group may be used as a first decoder group, a decoder that sets the number of iterations (iter) of the turbo code to x is a light decoder, the larger the iter value is, the stronger the decoding capability of the decoder is, and the longer the decoding time is, the iter-x decoder group is composed of M iter-x decoders, M is a positive integer greater than or equal to 1, and the specific values of M and x are not limited in this embodiment of the present application.

In this embodiment, the iter-y decoder group may be used as the second decoder group, and a decoder with the number of iterations (iter) of the turbo code set as y is a re-decoder, and the iter-y decoder group is composed of N iter-y decoders, where y is greater than x, N is a positive integer greater than or equal to 1, and the buff depth of the iter-y decoder is L packets, and L is a positive integer greater than or equal to 1, and the specific values of N, y and L are not limited in this embodiment of the present application.

When other forms of list-structured decoders are employed, the method includes:

firstly, decoding a received data packet by using a list-x decoder group by using decoding equipment, wherein the list-x decoder group comprises at least one list-x decoder, and the decoding performance of each list-x decoder in the list-x decoder group is the same.

In the embodiment of the present application, the concrete introduction of the list-x decoder group can refer to the introduction of the CA-SCLx decoder group used when performing channel coding by using polar code and performing decoding by using CA-SCL algorithm.

And step two, when the list-x decoder group fails to decode the data packet, a distributor in the decoding equipment detects whether the cache of the list-y decoder group is full, when the cache of the list-y decoder in the list-y decoder group is full, step three is executed, when the cache of the list-y decoder in the list-y decoder group is not full, step four is executed, the list-y decoder group comprises at least one list-y decoder with decoding performance superior to that of the list-x decoder, and the decoding performance of each list-y decoder in the list-y decoder group is the same.

In the embodiment of the present application, the specific description of the list-x decoder group may refer to the description of the CA-SCLy decoder group used in decoding by using the polar code for channel coding and the CA-SCL algorithm.

And fourthly, decoding the data packet by the decoding equipment through the list-y decoder group.

The specific implementation manner of each step in the embodiment of the present application can refer to step one to step four when polar codes are used for channel coding and a CA-SCL algorithm is used for decoding.

According to the technical scheme, the total number of times of the decoders with the decoding number of y in the whole decoding process can be controlled through the configuration of the number of the list-x decoders and the number of the list-y decoders, so that the decoding of a fixed number can be completed within a fixed time, and the purpose of controllable time delay is achieved.

When other forms of iterative structured decoders are employed, the method includes:

In the embodiment of the present application, the specific description of the iter-x decoder group may refer to the description of the iter-x decoder group used in the channel coding by using LDPC and the decoding by using BP iterative algorithm.

In the embodiment of the present application, the specific description of the iter-y decoder group may refer to the description of the iter-y decoder group used in the channel coding using LDPC and decoding using BP iterative algorithm.

The specific implementation manner of each step in the embodiment of the present application can refer to step one to step four when LDPC is used for channel coding and BP iterative algorithm is used for decoding.

Fig. 12 is a flowchart of a decoding method provided in an embodiment of the present application, which is similar to fig. 7, and both are flowcharts of the decoding method, except that the decoding method provided in fig. 7 is a physically different circuit implementation, and the decoding method provided in fig. 12 is a different configuration mode of a logic circuit, see fig. 12, and the method includes:

1201. the decoding device decodes the received data packet through a decoder group, wherein the decoder group comprises at least one decoder, and the decoding performance of each decoder in the decoder group is the same.

1202. When the decoder group fails to decode the data packet, the decoding apparatus determines the available iteration number of the decoder group within the decoding window, and when the available iteration number is not 0, step 1203 is executed, and when the available iteration number is 0, the data packet is discarded.

1203. The decoding apparatus switches a first decoding mode of the decoders in the decoder group to a second decoding mode.

1204. The decoding device decodes the data packet whose decoding has failed based on the decoder group in the second decoding mode.

1205. When the target number of data packets in the decoding window of the decoder group fail to be decoded, the decoding device discards the data packets and counts the data packets into a decoding failure row and column.

The data packets are counted in the decoding failure row column, so that the number of the data packets with decoding failure can be counted, and the data such as the bad packet rate of the decoding equipment can be further obtained, and the performance of the decoding equipment can be analyzed conveniently.

When polar code is used for channel coding and a Successive Cancellation (SC) algorithm is used for decoding, the decoding device further includes, before decoding the received data packet by a decoder bank, a decoding unit:

The self-checking check can directly quantize the signal, the quantized result is higher than the threshold value, namely the output is 1, otherwise, the output is 0, the output result of the self-checking check can represent the state of the circuit, and therefore the output signal in the form of an analog signal is not required to be obtained through decoding to represent a certain state of the circuit. In the actual decoding process, when the receiver receives the data packet, the data packet is firstly sent to the self-checking module, and the self-checking module checks the data packet and then determines whether the decoding is needed.

In the above technical solution, after the decoding of the first decoder group fails, the available iteration number of the decoder group in the decoding window is determined, and when the available iteration number is 0, the data packet is discarded, otherwise, the target number of decoders in the first decoding mode is switched to the second decoding mode with better decoding performance, and the data packet with failed decoding is decoded continuously, and if the decoding of the second decoder group fails, the data packet with failed decoding can be discarded directly, so that the normal operation of the decoders in the first decoding mode can be ensured, further the throughput efficiency of the decoders can be ensured, the decoding delay can be controlled, and the amount of the decoding controllable delay calculation unit, such as chip area, Field Programmable Gate Array (FPGA) logic number, Central Processing Unit (CPU) or digital signal processor (digital signal processor, DSP), time, etc., thereby reducing costs.

When polar codes are adopted for channel coding and CA-SCL algorithm is adopted for decoding, the method comprises the following steps:

step one, the decoding device decodes the received data packet through a CA-SCL decoder group, wherein the CA-SCL decoder group comprises at least one CA-SCL decoder.

It should be noted that the CA-SCL decoder may be configured to have multiple decoding modes (not limited to x and y modes) such as CA-SCLx and CA-SCLy.

In the embodiment of the present application, the CA-SCLx decoding mode is set as the light decoding mode, x is the size of the list of the decoder, the larger the value of the list is, the stronger the decoding capability of the decoder is, and the longer the decoding time is, and the embodiment of the present application does not limit the specific value of x.

And step two, when the first decoder group fails to decode the data packet, the decoding equipment switches the CA-SCLx decoding modes of the CA-SCL decoders with the target number in the CA-SCL decoder group to the CA-SCLy decoding mode.

In the embodiment of the present application, the CA-SCLy decoding mode is set as the re-decoding mode, y is the size of the list of the decoder, and the embodiment of the present application does not limit the specific value of y.

The number of decoders switched to the CA-SCly decoding mode and the number ratio between decoders in the CA-SCLx decoding mode and the CA-SCly decoding mode can be configured according to different requirements of throughput, working points and the like under different working environments. By configuring the decoders according to the working environment, the excessive number of the decoders can be avoided, and the cost is reduced.

In one possible implementation, when the CA-SCL decoder group fails to decode, N CA-SCL decoders in the CA-SCL decoder group in CA-SCLx decoding mode can switch to CA-SCLy decoding mode by themselves. Wherein N is a positive integer greater than or equal to 1.

And step three, decoding the decoding failure data packet by the decoding equipment based on the CA-SCL decoder group in the CA-SCLK decoding mode.

Step four, when the CA-SCL decoder group has a target number of data packets in a target decoding window and fails in decoding, the decoding equipment discards the data packets and counts the data packets into a row and a column with failed decoding.

In a possible implementation manner, when N of M consecutive data packets fail to be decoded, a CA-SCL decoder in a CA-SCLx decoding mode directly discards the data packet and counts the data packet into a row and a column of failed decoding, where M is the total number of data packets in a window, N is the number of data packets that can be processed by the CA-SCL decoder in the CA-SCLy decoding mode, M, N are positive integers greater than or equal to 1, and the value of M is greater than the value of N.

It should be noted that, after the CA-SCL decoder in the CA-SCLy decoding mode completes decoding or discards the data packet that fails to be decoded, the CA-SCLx decoding mode can be automatically switched to, and decoding is continued based on the newly received data packet.

For a decoder in a CA-SCLx decoding mode in a CA-SCLx decoder group, after discarding a data packet with decoding failure, decoding can be continued based on a newly received data packet without waiting for the decoder in the CA-SCLy decoding mode to release decoding capability, so that normal work of the decoder in the CA-SCLx decoding mode can be ensured, throughput efficiency of the decoder in the CA-SCLx decoding mode can be ensured, and decoding time is delayed and controllable. On the basis of the throughput capacity of a decoder in a CA-SCLx decoding mode, the performance of the decoder is improved, so that the decoding performance is close to that of a light decoder when the SNR is close to the side with higher FER, namely, the SNR is lower, the decoding performance is improved, and when the SNR is gradually increased, the decoding performance is gradually close to that of a heavy decoder.

The technical scheme can control the total number of times of the decoder in the CA-SCLy decoding mode in the whole decoding process by configuring the number of the decoder in the CA-SCLx decoding mode and the number of the decoders in the CA-SCLy decoding mode, further ensure that the decoding of a fixed number is completed within a fixed time, and achieve the purpose of controllable time delay.

When LDPC is adopted for channel coding and BP iterative algorithm is adopted for decoding, the method comprises the following steps:

step one, the decoding device decodes the received data packet through an iterative decoder group, wherein the iterative decoder group comprises at least one iterative decoder.

It should be noted that the iterative decoder may be configured to have multiple decoding modes (not limited to x and y modes) such as iter-x and iter-y.

In the embodiment of the present application, the iter-x decoding mode is set as a light decoding mode, x is the iteration number of the decoder, the larger the iter value is, the stronger the decoding capability of the decoder is, and the longer the decoding time is, and the specific value of x is not limited in the embodiment of the present application.

And step two, when the iterative decoder group fails to decode the data packet, the decoding equipment switches the iter-x decoding mode of the iterative decoders with the target number in the iterative decoder group to the iter-y decoding mode.

In the embodiment of the present application, the iter-y decoding mode is set as the re-decoding mode, y is the iteration number of the decoder, and the specific value of y is not limited in the embodiment of the present application.

The number of decoders switched to the iter-y decoding mode and the number ratio between decoders in the iter-x decoding mode and the iter-y decoding mode can be configured according to different requirements of throughput, working points and the like under different working environments. By configuring the decoders according to the working environment, the excessive number of the decoders can be avoided, and the cost is reduced.

In one possible implementation, when the iterative decoder group fails to decode, the N decoders in the iterative decoder group in the iter-x decoding mode are switched to the iter-y decoding mode. Wherein N is a positive integer greater than or equal to 1.

And thirdly, decoding the decoding failure data packet by the decoding equipment based on the iterative decoder group in the iter-y decoding mode.

Step four, when the iterative decoder group has a target number of data packet decoding failure in the target decoding window, the decoding device discards the data packet and counts the data packet into a decoding failure row and column.

In a possible implementation manner, when N of M consecutive data packets fail to be decoded, a decoder in an iter-x decoding mode directly discards the data packet and counts the data packet into a row and a column of failed decoding, where M is a total number of data packets in a window, N is a number of data packets that can be processed by the decoder in the iter-y decoding mode, M, N are positive integers greater than or equal to 1, and a value of M is greater than a value of N.

It should be noted that, after the decoder in the iter-y decoding mode completes decoding or discards a data packet that fails to be decoded, the decoder can automatically switch to the iter-x decoding mode to continue decoding based on a newly received data packet.

For a decoder in the iter-x decoding mode in the iterative decoder group, after discarding the data packet with decoding failure, decoding can be continuously performed based on the newly received data packet without waiting for the decoder in the iter-y decoding mode to release the decoding capability, so that normal operation of the decoder in the iter-x decoding mode can be ensured, throughput efficiency of the decoder in the iter-x decoding mode can be ensured, and decoding time is controllable. On the basis of the throughput capacity of the decoder in the iter-x decoding mode, the performance of the decoder is improved, so that the decoding performance is close to that of a light decoder when the SNR is close to the side with higher FER, namely, the SNR is lower, the decoding performance is improved, and when the SNR is gradually increased, the decoding performance is gradually close to that of a heavy decoder.

The technical scheme can control the total number of times of the decoder with the iterative iter being y in the whole decoding process by configuring the number of the decoders in the iter-x decoding mode and the decoders in the iter-y decoding mode, further can ensure that the decoding with the fixed number is completed within fixed time, and achieves the purpose of controllable time delay.

When the turbo code is used for channel coding, the method comprises the following steps:

When other forms of list-structured decoders are employed, the method includes:

step one, the decoding device decodes the received data packet through a list decoder group, wherein the list decoder group comprises at least one list decoder.

In the embodiment of the present application, the specific description of the list decoder group may refer to the description of the CA-SCLx decoder group used when performing channel coding by using polar code and performing decoding by using CA-SCL algorithm.

And step two, when the list decoder group fails to decode the data packet, the decoding equipment switches the list-x decoding modes of the list decoders with the target number in the list-x decoder group to the list-y decoding mode.

In the embodiment of the present application, for a specific introduction of the decoding mode switching method, reference may be made to a decoding mode switching process when a polar code is used for channel coding and a CA-SCL algorithm is used for decoding.

And thirdly, decoding the decoding failure data packet by the decoding equipment based on the list decoder group in the list-y decoding mode.

And step four, when the list decoder group has the data packet decoding failure of the target number in the target decoding window, the decoding equipment discards the data packet and counts the data packet into a decoding failure row and column.

According to the technical scheme, the total number of times of the decoders with the decoding number list of y in the whole decoding process can be controlled through the configuration of the number of the decoders in the list-x decoding mode and the number of the decoders in the list-y decoding mode, so that the fixed number of decoding can be completed within a fixed time, the purpose of controllable time delay is achieved, the whole throughput is guaranteed to be M times that of a single decoder in the list-x decoding mode through the combination of the list-x decoding method and the list-y decoding method, and the decoding performance of the whole system near a working point is guaranteed to be similar to the decoding performance of the system near the working point.

step one, decoding the received data packet through an iterative decoder group, wherein the iterative decoder group comprises at least one iterative decoder.

In the embodiment of the present application, a specific description of the decoding mode switching method may refer to a decoding mode switching process when performing channel coding by using LDPC and performing decoding by using BP iterative algorithm.

In the embodiment of the application, the iter-x decoding mode is set as a light decoding mode, x is the iteration number of the decoder, and the larger the iter value is, the stronger the decoding capability of the decoder is, and the longer the decoding time is. Setting an iterative decoder in a window of M data packets, where the total allowable number of iterations is N, where M, N are positive integers greater than or equal to 1, and the specific values of x, M, and N are not limited in the embodiment of the present application.

Step two, when the iterative decoder group fails to decode the data packet, the decoding device determines the available iteration number of the decoder group in the decoding window, directly discards the data packet when the available iteration number is 0, and executes step three when the available iteration number is not 0.

The window may be a window with a fixed starting position, that is, a decoding window is reset from the M +1 th packet, and the M +1 th packet to the M + M th packet are rearranged into a counting period, where the initial available iteration times in each counting period are the same, and only when the decoding of the packets in the previous counting period is completed, the next counting period is entered.

The window may also be a sliding window, the available iteration number of the next counting period is affected by the iteration number used by the first data packet in the previous counting period and the available iteration number remaining in the previous counting period, when determining the available iteration number of the next counting period, the iteration number used by the 1 st data packet in the previous counting period may be determined, the available iteration number remaining in the previous counting period may be determined, and the sum of the iteration number used by the 1 st data packet and the available iteration number remaining in the previous counting period is used as the current available iteration number of the next counting period. The embodiment of the present application does not limit what window type is specifically adopted. Taking an example that the iterative decoder has a total allowable number of iterations of 20 in a window of 5 data packets, see fig. 13, where fig. 13 is a schematic diagram of a window with a fixed starting position provided in an embodiment of the present application, each box in fig. 13 represents a data packet, and the number in the box is the number of iterations used by the data packet, as shown in fig. 13, the number of iterations used by the 5 data packets in window 1 is respectively 4, 5, 8, 3, and 0, and the available number of iterations is restored to 20 from window 2. Fig. 14 is a schematic diagram of a sliding window provided in an embodiment of the present application, referring to fig. 14, where each box in fig. 14 represents a data packet, and the number in the box is the number of iterations used by the data packet, as shown in fig. 14, a window 1 includes 1 st to 5 th data packets, the number of iterations used by the 5 data packets is 4, 5, 8, 3, and 0, respectively, and a window 2 includes 2 nd to 6 th data packets, since iter-x data packets have already been marked out of the

window

2, 4 iterations can be released, the number of available iterations for the 6 th data packet is 4, and the number of iterations used by the 5 data packets is 5, 8, 3, 0, and 4, respectively. The

windows

1, 2 in the fixed start position window mode are joined to each other and do not coincide at all, while the

windows

1, 2 in the sliding window mode are partially coincident.

And step three, the decoding equipment switches the iter-x decoding mode of the target number of iterative decoders in the iterative decoder group to the iter-y decoding mode.

In one possible implementation, when the iterative decoder group fails to decode, P decoders in the iterative decoder group in the iter-x decoding mode are switched to the iter-y decoding mode. Wherein P is a positive integer greater than or equal to 1.

And step four, the decoding equipment decodes the decoding failure data packet based on the iterative decoder group in the iter-y decoding mode.

And step five, when the iterative decoder group has a target number of data packets in the target decoding window and fails in decoding, the decoding equipment discards the data packets and counts the data packets into a decoding failure row and column.

In a possible implementation manner, when P decoding failures occur in M consecutive data packets, a decoder in the iter-x decoding mode directly discards the data packet and counts the data packet into a row and a column of the decoding failures, where M is the total number of data packets in a window, P is the number of data packets that can be processed by the decoder in the iter-y decoding mode, M, P are positive integers greater than or equal to 1, and the value of M is greater than the value of P.

The technical scheme can ensure that the performance of the decoder reaches the performance of the decoder in an iter-y decoding mode and the throughput reaches the average performance of the decoder in an iter-x decoding mode by controlling the total iteration times of the decoder group in the whole decoding window.

When polar codes are adopted for channel coding and SC algorithm is adopted for decoding, the method comprises the following steps:

step one, the decoding device carries out self-check on the received data packet through an SC decoder group, when the self-check is passed, step two is executed, when the self-check is not passed, step three is executed, and the SC decoder group comprises at least one SC decoder.

It should be noted that the hard decision required for self-checking may directly quantize the signal, and if the quantization result is higher than the threshold value, the output may be regarded as 1, otherwise, the output is 0, and the signal obtained by the hard decision is self-checked, and if the self-check is passed, decoding is not required.

In a possible implementation manner, the sub-code with the size of L is subjected to self-checking, if the checking is passed, the step two is executed, and if the checking is not passed, the step three is executed.

Wherein, the sub-code of polar code is nested mode, the size L can indicate the proportion of the sub-code to the total code length, L is 1/2ⁿN is greater than 0 and less than or equal to log₂The value of N, which is the code length, may be self-checking for a sub-code size of 1/2, for example.

It should be noted that, the SC decoder is configured to perform self-checking on the polar subcodes with L size b times in a window of M data packets, where M, b are positive integers greater than or equal to 1, and the specific values of M and b are not limited in this embodiment of the application.

And step two, the decoding equipment outputs the self-checking result, and the counter is increased.

It should be noted that the counter can be used to count the decoding times.

And step three, the decoding equipment decodes the data packet through the SC decoder group.

The SC decoder may be configured in multiple decoding modes (not limited to x and y modes) such as SCx and SCy. The SCx decoding mode is set to be a light decoding mode, x is the decoding times of the subcodes which are allowed to fail in self-checking of the decoder, and the larger the value of x is, the stronger the decoding capability of the decoder is, and the longer the decoding time is.

Step four, when the SC decoder group fails to decode the data packet, the decoding equipment determines the decoding times of the available subcodes of the decoder group in the decoding window, when the decoding times of the available subcodes is 0, the remaining data packets to be decoded are self-checked, when the self-check is passed, the checking result is output, when the self-check is not passed, the data packet is discarded and the data packet is counted into a decoding failure row and column, and when the available iteration times is not 0, the step five is executed.

The window may be a window at a fixed starting position, or may also be a sliding window, which type of window is specifically adopted is not limited in the embodiment of the present application, and a specific window structure may be as shown in fig. 13 and 14.

In a possible implementation manner, when the decoding times of the available subcodes in the decoder in the SCx decoding mode and the decoder in the SCy decoding mode are 0, performing self-checking on the remaining data packets to be decoded in the window, and if the self-checking passes, outputting a checking result, otherwise, discarding the data packets to be decoded.

And step five, the decoding equipment switches the SCx decoding mode of the target number of SC decoders in the SC decoder group to SCy decoding mode.

It should be noted that, the SCy decoding mode is set as a re-decoding mode, y is the decoding number of the subcodes of the decoder, and the specific value of y is not limited in the embodiment of the present application.

The number of decoders switched to the SCy decoding mode and the number ratio between decoders in the SCx decoding mode and the SCy decoding mode can be configured according to different requirements such as throughput and operating point under different operating environments. By configuring the decoders according to the working environment, the excessive number of the decoders can be avoided, and the cost is reduced.

In one possible implementation, when the decoding of the SC decoder group in the SCx decoding mode fails, P SC decoders in the SCx decoding mode in the SC decoder group in the SCx decoding mode are switched to the SCy decoding mode. Wherein P is a positive integer greater than or equal to 1.

And step six, the decoding device decodes the decoding failure data packet based on the SC decoder group in the SCy decoding mode.

And step seven, when the SC decoder group has a target number of data packets in the target decoding window and fails in decoding, the decoding equipment discards the data packets and counts the data packets into a decoding failure row and column.

In a possible implementation manner, when P decoding fails in M consecutive data packets, a decoder in the SCx decoding mode directly discards the data packet, and counts the data packet into a row and a column of the decoding failure, where M is the total number of data packets in a window, P is the number of data packets that can be processed by the decoder in the SCy decoding mode, M, P is a positive integer greater than or equal to 1, and the value of M is greater than the value of P, and the specific values of M and P are not limited in the embodiment of the present application.

The technical scheme can control the decoding time and increase the throughput by controlling the number of the decoded subcodes in the SC decoder. Because the total decoding number of the subcodes in one window time is limited, the decoding time delay of the whole system is controllable. The decoder increases throughput without increasing area, and its performance approximates the original SC decoder near the operating point.

All the above optional technical solutions may be combined arbitrarily to form optional embodiments of the present application, and are not described herein again.

Fig. 15 is a schematic diagram of a decoding apparatus according to an embodiment of the present application, and referring to fig. 15, the apparatus includes:

a first decoding module 1501, configured to perform step 701;

a packet discarding module 1502 configured to perform step 703;

a second decoding module 1503, configured to perform step 704.

In one possible implementation, the apparatus further includes:

a detection module for performing step 702;

in one possible implementation, the apparatus further includes:

a self-checking module, configured to perform a sub-code self-checking process on the data packet before step 701;

and an output module, configured to perform a process of outputting a verification result when the verification passes before step 701.

In one possible implementation, the apparatus further includes:

an entering module, configured to perform a process of entering the data packet into a decoding failure queue in step 703.

The device firstly decodes the data packet through the first decoder group, when the first decoder group fails in decoding, if the buffer memory of the second decoder in the second decoder group is full, the data packet is directly discarded, otherwise, the data packet is decoded by the second decoder group with decoding performance superior to that of the first decoder group. When the decoding of the first decoder group fails and the buffer memory of the second decoder in the second decoder group is full, the data packet submitted after the decoding of the first decoder group fails can be directly discarded, the normal work of the first decoder group is ensured, and the decoding efficiency of the first decoder group is further ensured.

Fig. 16 is a schematic diagram of a decoding apparatus according to an embodiment of the present application, and referring to fig. 16, the apparatus includes:

a decoding module 1601 for performing step 1201;

a switching module 1602, configured to perform step 1203;

the decoding module 1601 is further configured to execute step 1204;

a packet discard module 1603 for performing step 1205.

In one possible implementation, the apparatus further includes:

a determining module, configured to perform the process of determining the available iteration number of the decoder group in the decoding window in step 1202;

the packet discarding module 1603 is further configured to perform the process of discarding the packet when the available iteration number is 0 in step 1202.

In one possible implementation, the apparatus further includes:

a self-checking module, configured to perform a self-checking process on the data packet before performing step 1201;

and the output module is used for executing the process of outputting the verification result when the verification passes before the step 1201.

The device firstly decodes the data packet through the first decoder group, when the decoding of the first decoder group fails, if the available iteration number of the decoder group is 0, the data packet is directly discarded, otherwise, the first decoding mode of the decoder in the decoder group is switched to the second decoding mode to decode the data packet, when the decoding of the data packet with the target number in the decoding window fails, the data packet is discarded, the normal work of the first decoder group can be ensured, and the decoding efficiency of the first decoder group is further ensured.

It should be noted that: in the decoding device provided in the above embodiment, only the division of the above functional modules is taken as an example for the decoding, and in practical applications, the above function distribution may be completed by different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above described functions. In addition, the decoding apparatus and the decoding method provided in the above embodiments belong to the same concept, and specific implementation processes thereof are described in the method embodiments and are not described herein again.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of decoding, the method comprising:

discarding the data packet when the first decoder group fails to decode the data packet and a buffer of a second decoder in a second decoder group is full, the second decoder group comprising at least one second decoder having decoding performance better than the first decoder;

and when the first decoder group fails to decode the data packet and the buffer of a second decoder in the second decoder group is not full, decoding the data packet through the second decoder group.

2. The method of claim 1, further comprising:

when the first decoder group fails to decode the data packet, the cache of the second decoder group is detected.

3. The method of claim 1, wherein before decoding the received data packet by the first decoder set, the method further comprises:

performing self-checking on the data packet;

when the verification passes, outputting a verification result;

and when the check is failed, executing the step of decoding the received data packet by the first decoder group.

4. The method of claim 1, wherein the decoding performance of each first decoder in the first decoder group is the same.

5. The method of claim 1, wherein the decoding performance of each second decoder in the second decoder group is the same.

6. The method of claim 1, wherein after discarding the packet when the first decoder group fails to decode the packet and a buffer of a second decoder in a second decoder group is full, the method further comprises:

and counting the data packet into a decoding failure row and a decoding failure row.

7. A method of decoding, the method comprising:

decoding the received data packets by a decoder bank, the decoder bank including at least one decoder;

when the decoder group fails to decode the data packet, switching a first decoding mode of a decoder in the decoder group to a second decoding mode, wherein the decoding performance of the second decoding mode is superior to that of the first decoding mode;

8. The method of claim 7, wherein prior to switching the first decoding mode to the second decoding mode of the decoders in the decoder bank, the method further comprises:

determining a number of available iterations of the decoder set within the coding window;

when the number of available iterations is not 0, performing the step of switching a first decoding mode to a second decoding mode of decoders in the decoder group;

and when the available iteration number is 0, discarding the data packet.

9. The method of claim 7, wherein before decoding the received data packet by the decoder bank, the method further comprises:

performing self-checking on the data packet;

when the verification passes, outputting a verification result;

and when the check is failed, executing the step of decoding the received data packet by the passing decoder group.

10. An apparatus for decoding, the apparatus comprising:

a first decoding module, configured to decode a received data packet by a first decoder group, where the first decoder group includes at least one first decoder;

a packet discarding module, configured to discard the packet when the first decoder group fails to decode the packet and a buffer of a second decoder in a second decoder group is full, where the second decoder group includes at least one second decoder having decoding performance better than that of the first decoder;

and the second decoding module is used for decoding the data packet through the second decoder group when the first decoder group fails to decode the data packet and the buffer of the second decoder in the second decoder group is not full.

11. The apparatus of claim 10, further comprising:

a detection module, configured to detect a cache of the second decoder group when the first decoder group fails to decode the data packet.

12. The apparatus of claim 10, further comprising:

the self-checking module is used for carrying out self-checking on the data packet;

and the output module is used for outputting a decoding result when the verification passes.

13. The apparatus of claim 10, further comprising:

and the logging module is used for logging the data packet into a decoding failure row and column.

14. An apparatus for decoding, the apparatus comprising:

a decoding module, configured to decode the received data packet by a decoder group, where the decoder group includes at least one decoder;

a switching module, configured to switch a first decoding mode of a decoder in the decoder group to a second decoding mode when the decoder group fails to decode the data packet, where decoding performance of the second decoding mode is better than that of the first decoding mode;

the decoding module is further configured to decode the data packet that fails to be decoded based on the decoder group in the second decoding mode;

and the data packet discarding module is used for discarding the data packet when the decoding of the target number of data packets in the decoding window of the decoder group fails.

15. The apparatus of claim 14, further comprising:

a determination module for determining a number of available iterations of the decoder group within the decoding window;

the data packet discarding module is further configured to discard the data packet when the available iteration number is 0.

16. The apparatus of claim 14, further comprising:

and the output module is used for outputting the verification result when the verification is passed.

17. A decoding apparatus, characterized in that the decoding apparatus comprises:

a distributor is connected between every two decoder groups, and each decoder group comprises at least one decoder;

for a first decoder group of any two consecutive decoder groups, the first decoder group is configured to decode a received data packet;

for a second decoder group of any two consecutive decoder groups, the second decoder group is configured to decode the data packet after the first decoder group fails to decode the data packet;

for each of the two decoder groups, a distributor for detecting the buffer of the second decoder group and for counting the data packets into a decoding failure line;

the decoders of the second decoder set have better decoding performance than the decoders of the first decoder set.

18. A decoding apparatus, characterized in that the decoding apparatus comprises:

a plurality of decoder banks including at least one decoder;

the decoder set is configured to decode a received data packet based on the decoder set being in a first decoding mode;

the decoder group is further configured to switch the first decoding mode of a decoder in the decoder group to a second decoding mode when the decoder group fails to decode the data packet, and the decoding performance of the second decoding mode is better than that of the first decoding mode;

the decoder group is also used for decoding the data packet which fails in decoding based on the decoder group in the second decoding mode.

19. A terminal device, characterized in that the terminal device comprises one or more transceivers for transceiving data packets and a plurality of decoder sets for performing the decoding method of any one of claims 1 to 9.

20. A network device, comprising one or more transceivers for transceiving data packets and a plurality of decoder sets for performing the decoding method of any one of claims 1 to 9.