CN112582473A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
CN112582473A
CN112582473A CN201910936760.6A CN201910936760A CN112582473A CN 112582473 A CN112582473 A CN 112582473A CN 201910936760 A CN201910936760 A CN 201910936760A CN 112582473 A CN112582473 A CN 112582473A
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Prior art keywords
gate
forming
groove
layer
dummy gate
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CN201910936760.6A
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韩秋华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910936760.6A priority Critical patent/CN112582473A/en
Publication of CN112582473A publication Critical patent/CN112582473A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the invention provides a method for forming a semiconductor device. In the embodiment of the invention, the grooves are formed by etching the dummy gates between the adjacent fin parts, so that the dummy gates are divided into two parts which are separated from each other. And forming extension layers on the side walls of the dummy gates on the two sides of the groove, wherein the extension layers are used for adjusting the size of the groove, so that the distance between the side walls of the groove and the fin parts on the two sides of the groove is increased, and the size of the formed gate accommodating structure is increased. The process window of the subsequent gate growth in the gate accommodating structure can be enlarged, and the performance of the semiconductor device is improved.

Description

Method for forming semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor device.
Background
With the continuous development of semiconductor manufacturing processes, the integration level of semiconductor devices is higher and higher, and the feature size of semiconductor devices is also gradually reduced. However, the performance of semiconductor devices is also in need of improvement.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device. The method provided by the embodiment of the invention comprises the following steps:
providing a front-end device layer comprising a plurality of discrete fins;
forming a dummy gate crossing each fin portion;
forming a first dielectric layer covering the side wall of the pseudo gate;
etching a pseudo gate between adjacent fin parts to form a groove, wherein the groove divides the pseudo gate into two parts which are separated from each other;
forming extension layers on the side walls of the dummy gates on the two sides of the groove to adjust the distance between the side wall of the groove and the fin part;
filling a second dielectric layer in the groove to isolate the pseudo gates on two sides of the groove;
and removing the dummy gate and the extension layer to form a gate accommodating structure.
Furthermore, the material of the dummy gate is polysilicon; the extension layer is made of amorphous silicon.
Further, the thickness of the extension layer is 2 nm-10 nm.
Further, the forming of the extension layer on the side wall of the groove specifically includes:
and forming the extension layer on the side wall of the groove by adopting a selective deposition process.
Further, the distance between the adjacent fin parts is 30-100 nanometers;
the size of the groove is 15-50 nanometers.
Further, the removing the dummy gate and the extension layer specifically includes:
and removing the dummy gate and the extension layer by adopting an etching process in which the etching rate of the dummy gate and the extension layer is greater than that of the first dielectric layer and the second dielectric layer.
Further, the method further comprises:
and forming a gate structure in the gate accommodating structure.
Further, the width of the dummy gate is not more than 30 nanometers.
In the embodiment of the invention, the grooves are formed by etching the dummy gates between the adjacent fin parts, so that the dummy gates are divided into two parts which are separated from each other. And forming extension layers on the side walls of the dummy gates on the two sides of the groove, wherein the extension layers are used for adjusting the size of the groove, so that the distance between the side walls of the groove and the fin parts on the two sides of the groove is increased, and the size of the formed gate accommodating structure is increased. The process window of the subsequent gate growth in the gate accommodating structure can be enlarged, and the performance of the semiconductor device is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 to 3 are schematic views of structures formed at respective steps of a method of forming a semiconductor device of a comparative example;
fig. 4 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;
fig. 5 to 13 are schematic views of structures formed at respective steps of a method of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it is to be understood that the term "layer" is used in its broadest sense, thereby including a film, a cap layer, or the like, and one layer may include a plurality of sub-layers.
In the description of the present invention, it is to be understood that reference throughout the specification to conventional etching techniques known in the semiconductor manufacturing art for selectively removing polysilicon, silicon nitride, silicon dioxide, metal, photoresist, polyimide, or similar materials includes, for example, wet Chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, precleaning, spray cleaning, Chemical Mechanical Polishing (CMP), and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and reference to particular deposition techniques should not be limited to that described. In some examples, two such techniques may be interchanged. For example, stripping the photoresist may include soaking the sample in a wet chemical bath or alternatively spraying a wet chemical directly onto the sample.
The term "cross over" refers to that the dummy gate structure crosses over the fin, which means that the dummy gate structure covers part of the top surface and part of the sidewall surface of the fin, and the dummy gate structure and the fin have a crossed position relationship, and the height of the dummy gate structure is greater than that of the fin.
Semiconductor devices are electronic devices that have electrical conductivity between a good electrical conductor and an insulator, and that use the special electrical properties of semiconductor materials to perform specific functions, and can be used to generate, control, receive, convert, amplify signals, and perform energy conversion. Conventional semiconductor devices include Fin-Field-Effect transistors (Fin-FETs).
The fin field effect transistor is a novel complementary metal oxide semiconductor transistor, and generally comprises a fin part protruding out of the surface of a semiconductor substrate, a gate structure covering part of the top surface and the side wall of the fin part, and source and drain doped regions positioned in the fin part at two sides of the gate structure. The design can improve circuit control, reduce leakage current and shorten the gate length of the transistor.
Fig. 1 is a schematic structural view of a semiconductor device including a finfet, fig. 2 is a three-dimensional structural view of fig. 1 at a region 4, and fig. 3 is a cross-sectional view taken along line AA in fig. 2. Referring to fig. 1-3, the field effect transistor in the figures includes a fin 1, a dummy gate 2, and a recess 3 (also referred to as P2 CUT) between the dummy gate 2. The grooves 3 are used for isolating the end parts of two adjacent dummy gates 2. However, as the integration of the semiconductor device is higher, the distance between adjacent fins 1 is smaller and smaller, as shown in fig. 3, the distance between the sidewall of the recess 3 and the fin 1 is very close, so that the process window in the subsequent process of replacing the dummy gate with the gate is too small, the gate is prone to have defects at the sidewall of the recess 3, and the reliability of the semiconductor device is reduced.
In view of this, the performance of the semiconductor device is improved. The embodiment of the invention provides a method for forming a semiconductor device. In the embodiments of the present invention, the formation of the finfet is taken as an example, and further, the method of the embodiments of the present invention may be used to form the finfet below the 14nm process node and the 14nm process node, for example, to form the finfet of 14nm or 7 nm. Furthermore, the method of forming the fin field effect transistor according to the method of the embodiment of the present invention may also be used for forming other Semiconductor devices such as a Complementary Metal Oxide Semiconductor (CMOS), a NAND Flash Memory (NAND Flash Memory), a Static Random Access Memory (SRAM), and the like.
Fig. 4 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention. As shown in fig. 4, the method for forming a semiconductor device according to the embodiment of the present invention includes the steps of:
step S100, providing a front-end device layer, where the front-end device layer includes a plurality of discrete fin portions.
Step S200, forming a dummy gate crossing each of the fin portions.
And step S300, forming a first dielectric layer covering the side wall of the dummy gate.
Step S400, etching part of the pseudo gate between the adjacent fin parts to form a groove, wherein the groove divides the pseudo gate into two parts which are separated from each other.
Step S500, forming an extension layer on the sidewalls of the dummy gates at the two sides of the groove to adjust a distance between the sidewalls of the groove and the fin portion.
And S600, filling a second dielectric layer in the groove to isolate the pseudo gates on two sides of the groove.
And S700, removing the dummy gate and the extension layer to form a gate accommodating structure.
In an optional implementation manner, the forming method according to the embodiment of the present invention further includes:
step S800, forming a gate structure in the gate accommodating structure.
Fig. 5 to 13 are schematic views of structures formed at respective steps of a method of forming a semiconductor device according to an embodiment of the present invention.
Fig. 5 is a perspective view of the front-end device layer. Referring to fig. 5, in step S100, a front-end device layer 10 is provided, the front-end device layer 10 including a plurality of discrete fins 11.
Specifically, the front-end device layer 10 provided in step S100 may include a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, front-end device layer 10 may also include a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-silicon-germanium (S-SiGeOI), a silicon-on-insulator-silicon-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, a compound front-end device layer, or an alloy front-end device layer. The compound front end device layer comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium phosphide, the alloy front end device layer comprises SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof, the SOI substrate comprises a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a silicon carbon layer, or a germanium layer) disposed on an insulating material layer having active and passive devices therein, the insulating material layer protecting the active and passive devices disposed on the semiconductor layer. And a plurality of epitaxial interface layers or strain layers and other structures can be formed on the surface of the front-end device layer so as to improve the electrical performance of the semiconductor device.
The plurality of fins 11 are parallel or substantially parallel. The pitch between adjacent fins 11 is 30 nm to 100 nm.
In an alternative implementation, the front-end device layer 10 further includes a shallow trench isolation structure therein. The shallow trench isolation structure fills the bottom in the adjacent fin 11. The shallow trench isolation structure is used for electrical isolation between adjacent fins 11.
It should be understood that the fin in the embodiments of the present invention may have other shapes, such as a trapezoid with a top width smaller than a bottom width, a diamond shape, etc., and the shape of the fin is adjusted according to the process conditions and the application scenario.
Referring to fig. 6 and 7, in step S200, a dummy gate 13 is formed to cross each of the fins 11.
Fig. 7 is a schematic cross-sectional view of fig. 6 along line BB. As shown in fig. 7, there is a shallow trench isolation structure 12 between the fin 11 and the dummy gate 13.
The dummy gate 13 may be a strip-shaped cuboid formed on the isolation layer 12 and having a crossed position relationship with the fin 11, and preferably, the dummy gate 13 and the fin 11 have a mutually perpendicular or substantially perpendicular position relationship. As an example, the material of the dummy gate 13 may be polysilicon. In an alternative implementation, the method of forming the dummy gate 13 includes: forming a dummy gate material layer on the isolation layer 12 by a deposition process; and patterning the pseudo gate material layer to form a pseudo gate 13.
The dummy gate 13 is used to define the size and position of the gate structure in the subsequent process. The width of the dummy gate 13 is not more than 30 nm. That is, the feature size of the subsequently formed semiconductor device is no greater than 30 nanometers.
Referring to fig. 8, in step S300, a first dielectric layer 20 is formed to cover sidewalls of the dummy gate 13.
In an alternative implementation manner, before forming the first dielectric layer 20, the method according to the embodiment of the present invention further includes: forming a side wall on the side wall of the pseudo gate 13; and injecting light doping ions into the dummy gate 13 and the fin parts 11 at two sides of the side wall to form a source drain doping area.
In an alternative implementation, a method of forming the first dielectric layer 20 includes: forming a first dielectric material layer covering the upper surface of the pseudo gate 13 and the side wall 15 on the isolation layer 12, wherein the whole surface of the interlayer dielectric material layer is higher than the top surface of the pseudo gate 13; and removing the interlayer dielectric material layer higher than the top surface of the dummy gate 13 to expose the top of the dummy gate 13, thereby forming a first dielectric layer 20. The removal of the interlayer dielectric material layer above the top surface of the gate structure 13 may be achieved by chemical mechanical polishing.
Specifically, the first dielectric material layer is formed by a Chemical Vapor Deposition (CVD) method, such as Low Temperature Chemical Vapor Deposition (LTCVD), Plasma Chemical Vapor Deposition (PCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and Fluid Chemical Vapor Deposition (FCVD).
The material of the first dielectric layer 20 may be silicon dioxide (SiO)2) Silicon oxynitride (SiON), silicon nitride (Si)3N4) Or silicon oxycarbide (SiOC). In the present embodiment, the material of the first dielectric layer 20 is silicon dioxide.
After the first dielectric layer 20 is deposited, the upper surface of the first dielectric layer is polished by a chemical mechanical polishing process so that the upper surface of the first dielectric layer 20 is substantially flush with the upper surface of the dummy gate 13.
Fig. 9 is a schematic illustration of a structure formed without the inclusion of a first dielectric layer. Referring to fig. 9, in step S400, a portion of the dummy gate 13 between adjacent fins 11 is etched to form a groove 30, and the groove 30 divides the dummy gate 13 into two parts separated from each other.
Specifically, a mask pattern with an opening is formed in a predetermined region on the dummy gate 13 between the adjacent fins 11 by using a photolithography process, and a region not covered by the mask is etched.
The method for etching the dummy gate 13 may be wet etching, dry etching or a combination of the wet etching and the dry etching. As an example, a wet etching process is used to remove the dummy gate 13, and the specific parameters include: the adopted etching solution is hydrofluoric acid solution, the mass percent of hydrofluoric acid is 1:100-1:1000, and the etching temperature is 15-75 ℃.
The size of the grooves 30 is 15 nm to 50 nm. The size of the groove 30 is the distance between the sidewalls of the dummy gate 13 at both sides of the groove 30 shown in fig. 9.
Because the pitch of the fins 11 is too small, and the size of the recess 30 cannot be reduced correspondingly due to the limitation of the etching process, the distance between the sidewall of the dummy gate 13 and the fin 11 is very close after etching.
Fig. 10 is a cross-sectional view of the structure along the CC line, and referring to fig. 10, in step S500, an extension layer is formed on the sidewalls of the dummy gates 13 at two sides of the recess 30 to adjust the distance between the sidewalls of the recess 30 and the fin 11.
The extension layer 40 is used to be removed together with the dummy gate 13 in a subsequent process to increase the size of a gate receiving structure formed in the subsequent process. In particular, the distance between the gate receiving structures at the two ends of the recess 30 and the fin portions 11 at the two sides of the recess 30 is increased, so as to enlarge the process window for growing the gate in the gate receiving structures. Specifically, in the present embodiment, the extension layer 40 has a thickness of 2 nm to 10 nm.
Specifically, the material of the extension layer 40 may be the same as or similar to the etching rate of the dummy gate 13 in the subsequent etching process, and specifically may be polysilicon or amorphous silicon. In this embodiment, the material of the extension layer 40 is amorphous silicon.
Specifically, the forming of the extension layer on the side wall of the groove specifically includes:
the extension layer 40 is formed on the sidewalls of the recess 30 using a selective deposition process.
The selective deposition process can control the extension layer to cover only the dummy gate 13 at the sidewall of the groove 30, and not the first dielectric layer 20 at the sidewall of the groove 30. Compared with the common deposition process, the extension layer 40 formed by the selective deposition process does not cover the first dielectric layer 20, so that an additional process is not required to remove the extension layer 40 covering the first dielectric layer 20, and defects of the semiconductor device caused by removing the extension layer 40 on the first dielectric layer 20 can be avoided. Therefore, the selective deposition process can reduce the process flow, improve the efficiency and improve the reliability of the semiconductor device.
Fig. 11 is a cross-sectional view of the structure along the CC line, and referring to fig. 11, in step S600, a second dielectric layer 50 is filled in the groove 30 to isolate the dummy gates 13 at two sides of the groove 30.
Preferably, the method for forming the second dielectric layer 50 includes: an isolation material is deposited in the recess 30, the entire surface of the isolation material being higher than the top surface of the dummy gate 13.
The material of the second dielectric layer 50 may be silicon nitride, silicon oxynitride, or the like. In this embodiment, the second dielectric layer 50 is made of the same silicon oxide as the first dielectric layer 20. The same material as the first dielectric layer 20 is selected to avoid the formation of defects in the deposition process of the second dielectric layer 50, and simultaneously, the first dielectric layer 20 and the second dielectric layer 50 can be ensured to have better bonding performance, thereby achieving better isolation effect.
Referring to fig. 12, in step S700, the dummy gate 13 and the extension layer 40 are removed to form a gate accommodating structure 60.
Specifically, the dummy gate 13 and the extension layer are removed by using an etching process in which the etching rate of the dummy gate 13 and the extension layer is greater than that of the first dielectric layer and the second dielectric layer.
Since the extension layer 40 in the embodiment of the present invention is made of amorphous silicon and has an etching rate similar to that of the dummy gate 13, the dummy gate 13 and the extension layer can be removed by using the same etching process.
In an alternative implementation, the dummy gate 13 and the extension layer are removed by etching. And performing the etching by adopting a dry etching process, wherein the dry etching process has the following process parameters: HBr flow rate of 50sccm-500sccm, NF3The flow rate is 0sccm-50sccm, O2The flow rate is 0sccm-50sccm, the He flow rate is 0sccm-200sccm, the Ar flow rate is 0sccm-500sccm, the chamber pressure is 2mTorr-100mTorr, the source power is 200W-1000W, and the bias power is 0W-200W.
Referring to fig. 13, in step S800, a gate structure 70 is formed in the gate accommodating structure 60.
Forming the gate structure 70 in the gate receiving structure 60 may include forming a gate dielectric layer, a work function layer and a gate conductive layer, which are sequentially stacked.
In particular, the material of the gate dielectric layer may be a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the gate dielectric layer include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium tantalum oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material may also include dopants such as lanthanum and aluminum.
The gate dielectric layer may be formed by a suitable deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, evaporation, physical vapor deposition, chemical solution deposition, or other similar process. The thickness of the gate dielectric layer may vary depending on the deposition process and the composition and amount of high-k dielectric material used. The thickness of the gate dielectric layer may range from about 0.5nm to about 20 nm.
A work function layer may be disposed over the gate dielectric layer. The type of work function layer depends on the type of transistor and may vary between nFET and pFET devices. Non-limiting examples of suitable work function layers include p-type work function metal materials and n-type work function metal materials. The P-type work function material includes a composition such as ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide, or any combination thereof. N-type metallic materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The workfunction metal may be deposited by a suitable deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, evaporation, physical vapor deposition, chemical solution deposition, or other similar process.
Non-limiting examples of the gate conductive layer include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The gate conductive layer may be deposited by a suitable deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, evaporation, physical vapor deposition, chemical solution deposition, or other similar process.
In the subsequent process, the method further comprises the following steps: and forming a conductive through hole which is in gate connection with the source drain region and the metal gate. And forming an interconnect structure electrically connected to the conductive via. And packaging the formed semiconductor structure. To form a completed semiconductor device.
In the embodiment of the invention, the grooves are formed by etching the dummy gates between the adjacent fin parts, so that the dummy gates are divided into two parts which are separated from each other. And forming extension layers on the side walls of the dummy gates on the two sides of the groove, wherein the extension layers are used for adjusting the size of the groove, so that the distance between the side walls of the groove and the fin parts on the two sides of the groove is increased, and the size of the formed gate accommodating structure is increased. The process window of the subsequent gate growth in the gate accommodating structure can be enlarged, and the performance of the semiconductor device is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A method of forming a semiconductor device, the method comprising:
providing a front-end device layer comprising a plurality of discrete fins;
forming a dummy gate crossing each fin portion;
forming a first dielectric layer covering the side wall of the pseudo gate;
etching part of the pseudo gate between part of the adjacent fin parts to form a groove, wherein the groove divides the pseudo gate into two parts which are separated from each other;
forming extension layers on the side walls of the dummy gates on the two sides of the groove to adjust the distance between the side wall of the groove and the fin part;
filling a second dielectric layer in the groove to isolate the pseudo gates on two sides of the groove;
and removing the dummy gate and the extension layer to form a gate accommodating structure.
2. The method for forming a semiconductor device according to claim 1, wherein a material of the dummy gate is polysilicon; the extension layer is made of amorphous silicon.
3. The method of claim 1, wherein the extension layer has a thickness of 2 nm to 10 nm.
4. The method for forming a semiconductor device according to claim 1, wherein the forming of the extension layer on the side wall of the groove is specifically:
and forming the extension layer on the side wall of the groove by adopting a selective deposition process.
5. The method of claim 1, wherein a pitch between adjacent fins is 30 nm to 100 nm;
the size of the groove is 15-50 nanometers.
6. The method for forming a semiconductor device according to claim 1, wherein the removing the dummy gate and the extension layer is specifically:
and removing the dummy gate and the extension layer by adopting an etching process in which the etching rate of the dummy gate and the extension layer is greater than that of the first dielectric layer and the second dielectric layer.
7. The method of forming a semiconductor device according to claim 1, further comprising:
and forming a gate structure in the gate accommodating structure.
8. The method of claim 1, wherein the dummy gate has a width of no more than 30 nm.
CN201910936760.6A 2019-09-29 2019-09-29 Method for forming semiconductor device Pending CN112582473A (en)

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Citations (3)

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CN105097701A (en) * 2014-04-25 2015-11-25 中芯国际集成电路制造(上海)有限公司 Static memory cell forming method
CN107039526A (en) * 2015-11-04 2017-08-11 台湾积体电路制造股份有限公司 Semiconductor devices and its manufacture method
US10083874B1 (en) * 2017-03-23 2018-09-25 Globalfoundries Inc. Gate cut method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097701A (en) * 2014-04-25 2015-11-25 中芯国际集成电路制造(上海)有限公司 Static memory cell forming method
CN107039526A (en) * 2015-11-04 2017-08-11 台湾积体电路制造股份有限公司 Semiconductor devices and its manufacture method
US10083874B1 (en) * 2017-03-23 2018-09-25 Globalfoundries Inc. Gate cut method

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