CN112582460A - Semiconductor device unit, manufacturing method thereof and formed device - Google Patents

Semiconductor device unit, manufacturing method thereof and formed device Download PDF

Info

Publication number
CN112582460A
CN112582460A CN201910937911.XA CN201910937911A CN112582460A CN 112582460 A CN112582460 A CN 112582460A CN 201910937911 A CN201910937911 A CN 201910937911A CN 112582460 A CN112582460 A CN 112582460A
Authority
CN
China
Prior art keywords
layer
region
insulating passivation
semiconductor device
doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910937911.XA
Other languages
Chinese (zh)
Inventor
查祎英
金锐
董少华
王耀华
桑玲
吴军民
潘艳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
State Grid Corp of China SGCC
State Grid Zhejiang Electric Power Co Ltd
Global Energy Interconnection Research Institute
Original Assignee
State Grid Corp of China SGCC
State Grid Zhejiang Electric Power Co Ltd
Global Energy Interconnection Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by State Grid Corp of China SGCC, State Grid Zhejiang Electric Power Co Ltd, Global Energy Interconnection Research Institute filed Critical State Grid Corp of China SGCC
Priority to CN201910937911.XA priority Critical patent/CN112582460A/en
Publication of CN112582460A publication Critical patent/CN112582460A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)

Abstract

The invention provides a semiconductor device unit, a manufacturing method thereof and a forming device, and is characterized in that the unit comprises: the semiconductor device comprises a laminated layer formed by stacking semiconductor material layers with two doping characteristics, a gate control structure and an insulating passivation layer (31); the laminated layer is of a boss structure, the upper bottom surface is smaller than the lower bottom surface, and the side surface of the boss is provided with a positive bevel angle or right angle structure; the insulating passivation layer (31) is arranged on the side face of the laminated layer and is matched with the positive bevel angle or right angle structure to form a cubic structure with the laminated layer; the gate control structure is arranged between the insulating passivation layer (31) and the layer stack. The invention can realize flat stress surface, uniform stress, small stress of the insulated gate and large-area interconnection.

Description

Semiconductor device unit, manufacturing method thereof and formed device
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device unit, a manufacturing method thereof and a formed device.
Background
Semiconductor devices made of semiconductor materials generally implement specific functions by including P-type and N-type PN junctions or schottky junctions including metal-semiconductor, and gate control structures including metal-oxide-semiconductor, and the like. These structures are often realized by local doping or thin film processes. The semiconductor device realizes the control of current on and off through the structures, thereby realizing the transmission of signals. For high power applications, it is often desirable that the semiconductor device has the capability of blocking high voltage and conducting large current simultaneously. However, in order to achieve these functions, effective reduction of the on-resistance of the semiconductor material and effective junction edge isolation termination are required. For example, an insulated gate bipolar transistor IGBT is a semiconductor device invented to satisfy the above functions.
More specifically, the ability of a semiconductor device to pass current is related to its area size. Due to the inevitable defect distribution of the semiconductor crystal material and the inevitable process defects generated during the manufacturing process of the device, the manufacturing yield will rapidly decrease even close to 0 as the device area increases. For example, the size of a single IGBT chip is usually about 1 square centimeter, and the control on the current with the magnitude of tens of amperes can be satisfied. For larger current handling capacity, such as 1000 amperes, it is impractical to use 10 square centimeter sized IGBT chips for manufacturability and economy, and the prior art typically implements multiple IGBT chips of the same size in parallel. The chips are fabricated together from a wafer and test screened and then diced to separate them. After that, the chips are soldered on the same metal base plate, and the electrodes on the other side are interconnected on the other metal base plate by means of wires or pressing. The existing method has the process of firstly separating and then combining chips, increases the complexity of manufacturing and has higher requirement on the accuracy of recombination. While methods such as those described in CN02822412.4 and CN02825276.4 require that test-qualified chips be connected by a step-and-step lithographic process, while the unqualified chips are covered by an insulating layer. The problem that the finally formed electrodes are determined by the distribution condition of qualified chips on each wafer exists, namely, the electrodes of each wafer are different, and the subsequent use is difficult. Therefore, how to easily manufacture a semiconductor device capable of passing a large current is an important issue.
More specifically, the semiconductor material has a certain breakdown field strength, and particularly, a wide band gap material such as silicon carbide (SiC) has a high breakdown field strength and a high thermal conductivity. For use in high voltage applications, effective edge termination isolation is required. More specifically, the electric field concentrated at the PN junction edge causes the device to break down early in the location of the junction edge, resulting in a reduction in the device's ability to block high voltages. In the existing method, the isolation of the edge terminal is realized by introducing additional charges at the edge of the PN junction and changing the distribution of an electric field. For example, junction termination extension JTE achieves isolation protection of the termination by introducing extension regions with the same doping at the junction edges. The method needs to be realized by accurate calculation and multi-step micron-sized semiconductor processing technologies such as photoetching, etching, injection, activation and the like, and has relatively high requirements on design, process and equipment. While the method described in e.g. PCT/SE98/00772 solves the problem of edge termination, it requires that the chips be individually segmented to eventually achieve isolation of the edge termination. In the method described in PCT/US2008/072413, a vertical deep groove method is adopted to realize isolation, so that the problem of poor tolerance of processing deviation exists, and the poor verticality of the deep groove can greatly affect the terminal isolation effect. The method described in US20140151841a1 only enables isolation of two-terminal devices, and the chips need to be individually separated to ultimately achieve isolation of the edge terminations. Therefore, how to realize the high voltage blocking of the semiconductor device without cutting the chip apart, and simple and effective edge termination isolation is an important issue.
For the semiconductor device controlled by the insulated gate, the following can be mainly classified according to the gate: the channel controlled by the insulated gate is positioned on the surface of the semiconductor; trench gates, the channel controlled by the insulated gate extending from the surface into the semiconductor and being perpendicular to the surface or at an angle. The on and off of the semiconductor device can be realized through the control of the insulated gate. Compared with other parts of a semiconductor device, when a chip realizes electrode electric contact by bearing mechanical pressure, the edge of the insulated gate has mechanical stress and becomes a weak point of the whole device. An exemplary insulated gate control device is shown in fig. 1, i.e., includes an insulated gate control structure and other components. The presence of surface insulated gates limits the device's ability to form large current paths through the mechanical press contact of the upper and lower surface electrodes.
As shown in fig. 2, for the edge terminal of the semiconductor device, the surface depletion region width is increased by increasing the curvature of the junction mainly through local doping or removing a part of the semiconductor to realize the loss or compensation of space charge, so as to achieve the purpose of reducing the surface electric field. The structures are all positioned at the edge of the device, surround the whole conducting current area, and occupy a part of area, so that the effect of preventing the edge of the device from being influenced by a high electric field is achieved. For large area devices, the entire device will fail when there is a defect at any point in the area encompassed by the edge termination, leading to premature breakdown. With the increase of the area of the semiconductor device along with the increase of the current capacity requirement of the semiconductor device, the probability of the situation is greatly improved. Therefore, there is a need for a method to isolate the defective portions without affecting the other portions to continue functioning.
Disclosure of Invention
The invention provides a semiconductor device unit, a manufacturing method thereof and a forming device, aiming at solving the problems that the control edge of an insulated gate needs to bear stress and the whole device can be out of action when the unit has problems in the prior art.
The technical scheme provided by the invention is as follows:
a semiconductor device cell, comprising: the semiconductor device comprises a laminated layer formed by stacking semiconductor material layers with two doping characteristics, a gate control structure and an insulating passivation layer (31);
the laminated layer is of a boss structure, the upper bottom surface is smaller than the lower bottom surface, and the side surface of the boss is provided with a positive bevel angle or right angle structure;
the insulating passivation layer (31) is arranged on the side face of the laminated layer and is matched with the positive bevel angle or right angle structure to form a cubic structure with the laminated layer;
the gate control structure is arranged between the insulating passivation layer (31) and the layer stack.
Preferably, the laminate layer comprises: the collector region (10), the drift region (20), the emitter region (11) and the emitter region (21) are sequentially arranged from bottom to top;
wherein the collector region (10) and the emitter region (21) have a first doping characteristic;
the drift region (20) and the emitter region (11) have a second doping characteristic;
the first doping characteristic is N-type doping or P-type doping, and the second doping characteristic is P-type doping or N-type doping;
the side surface of the laminated layer is of a positive bevel angle or right-angle structure, the upper edge of the laminated layer is smaller than or equal to the lower edge of the laminated layer, and the laminated layer sequentially penetrates through the well emitting region (21), the emitting region (11) and the drift region (20) from top to bottom and is in contact with or inserted into the collector region (10).
Preferably, the number of the insulating passivation layers (31) is two, the two insulating passivation layers are respectively arranged in the positive bevel angle structure or the right angle structure of the side face of the laminated layer, the shape of the two insulating passivation layers is adapted to the positive bevel angle structure or the right angle structure, and the depth of the first insulating passivation layer (31) is smaller than that of the second insulating passivation layer (31).
Preferably, the unit further comprises: a well contact electrode (42');
the gate control structure includes: an insulated gate (30) and a gate electrode (41);
the gate electrode (41) is disposed under a first one of the insulating passivation layers (31), and the well contact electrode (42') is disposed under a second one of the insulating passivation layers (31);
the gate electrode (41) is arranged between the laminated layer and the gate electrode (41) and the first insulating passivation layer (31);
the gate electrode (41) is arranged between the layer stack and a well contact electrode (42') and a second one of the insulating passivation layers (31).
Preferably, the unit further comprises: an emitter metal electrode (43) and a collector metal electrode (42);
the emitter metal electrode (43) is provided above the laminated layer, and the collector metal electrode (42) is provided below the laminated layer.
A semiconductor device, the device comprising at least one cell;
on the same wafer, the units or the units turned over in a left-right mirror image mode are fixedly connected with the interconnection metal (3) and the metal bottom plate (4) in a repeated or interval repeated mode, and therefore the semiconductor device is formed.
A method for manufacturing a semiconductor device unit comprises the following steps:
sequentially and alternately stacking layer structures formed by semiconductor materials with two doping characteristics to form a layer stack;
manufacturing a structure with a positive bevel angle or a right angle on the side surface of the laminated layer by an etching and corrosion method, wherein the positive bevel angle or the right angle structure enters the bottommost layer of the laminated layer from top to bottom;
manufacturing a gate control structure in the positive bevel angle or right angle structure;
an insulating passivation layer (31) is fabricated and patterned on the gate control structure within the positive bevel or right angle structure on the side of the laminate layer.
Preferably, the forming of the semiconductor materials with two doping characteristics into thin films sequentially and alternately stacked to form the stacked layer comprises:
forming a drift region (20) by epitaxial, deposition or other suitable method to manufacture a semiconductor film with a second doping characteristic on the semiconductor material with the first doping characteristic of the collector region (10);
forming an emitter region (11) by forming a semiconductor film with a first doping characteristic by epitaxy, deposition or other suitable method on the drift region (20);
over the emitter region (11), a semiconductor film having a second doping characteristic is formed by epitaxy, deposition or other suitable method to form an emitter region (21).
Preferably, the manufacturing of the gate control structure in the positive bevel or right angle structure includes:
forming a first insulating thin layer to form an insulating gate (30) on the collector region (10) including the drift region (20), the emitter region (11), the side surface of the well region (21) and the surface of the well region (21) by oxidation, deposition or other suitable methods;
and forming a gate electrode (41) by making and patterning a first conductive thin layer on the insulated gate (30) and under a first one of the insulating passivation layers (31);
patterning the first insulating thin layer to form an insulated gate (30), and manufacturing and patterning a conductive layer under a second insulating passivation layer (31) to form a well contact electrode (42');
and manufacturing and patterning a third conductive thin layer on the well emitting region (21) to form an emitter metal electrode (43).
Preferably, the method further comprises the following steps after the insulating passivation layer (31) is manufactured and patterned on the gate control structure in the positive bevel or right angle structure on the side surface of the laminated layer: a second conductive thin layer is fabricated and patterned under the layer stack to form a collector metal electrode (42).
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a semiconductor device unit and a manufacturing method thereof, which are characterized in that the unit comprises: the semiconductor device comprises a laminated layer formed by stacking semiconductor material layers with two doping characteristics, a gate control structure and an insulating passivation layer (31); the laminated layer is of a boss structure, the upper bottom surface is smaller than the lower bottom surface, and the side surface of the boss is provided with a positive bevel angle or right angle structure; the insulating passivation layer (31) is arranged on the side face of the laminated layer and is matched with the positive bevel angle or right angle structure to form a cubic structure with the laminated layer; the gate control structure is arranged between the insulating passivation layer (31) and the layer stack. The invention can realize flat stress surface, uniform stress, small stress of the insulated gate and large-area interconnection.
The isolation of the chip edge terminal is realized through the non-through positive bevel angle, so that the chip is easy to realize the isolation of the edge terminal, and the chip is prevented from being rearranged after being cut.
By the method of electrically contacting and isolating the chip part with the defects, the appearance of the chip electrode after interconnection is not influenced by the distribution of the chips with the defects on the wafer.
The method is realized by utilizing the laminated semiconductor thin film layers with different dopings, selective doping is not needed in the preferred embodiment, and the requirement on line width precision is low;
the insulated gate is controlled to be positioned between the upper stressed surface and the lower stressed surface, the upper stressed electrode and the lower stressed electrode are flat in surface, the materials between the two electrodes are uniform, and the stress balance is good;
each functional unit is isolated from each other, the functionality is not influenced mutually, and the functional units with flaws can be selectively removed;
the functional unit can be repeatedly expanded in an unlimited range allowed by the used semiconductor substrate material, the edge different from the functional area does not exist, and the outer contour is not limited;
the circuit with the specific functions including the diode and the switching tube is easy to realize in an interconnection or integration mode;
and the functional module with larger current capacity can be easily formed by parallel expansion again.
Drawings
FIG. 1 is a schematic diagram of a prior art insulated gate control device;
FIG. 2 is a schematic diagram of an edge termination of a prior art device;
FIG. 3 is a schematic diagram of a semiconductor device cell of the present invention;
FIG. 4 is a schematic view of a doped semiconductor stack used to fabricate a device cell of the present invention;
FIG. 5 is a schematic illustration of the formation of edge termination isolation in accordance with the present invention;
FIG. 6 is a schematic diagram of the formation of an insulated gate dielectric of the present invention;
FIG. 7 is a schematic illustration of the formation of a gate electrode of the present invention;
FIG. 8 is a schematic illustration of the formation of a base electrode of the present invention;
FIG. 9 is a schematic illustration of the formation of a conductive electrode of the present invention;
FIG. 10 is a schematic illustration of the formation of isolation passivation of the present invention;
FIG. 11 is a schematic diagram of an embodiment of the present invention for interconnecting semiconductor devices to realize a large-area compression device;
FIG. 12 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of a method of fabricating a semiconductor device cell in accordance with the present invention;
wherein 1 is a unqualified unit, 2 is mechanical pressure, 3 is interconnection metal, 4-bit metal bottom plate, 10 is a collector region, 20 is a drift region, 11 is a well region, 21 is an emitter region, 30 is an insulated gate, 31 is an insulated passivation layer, 41 is a gate electrode, 42 is a collector metal electrode, 42' is a well contact electrode, and 43 is an emitter metal electrode.
Detailed Description
For a better understanding of the present invention, reference is made to the following description taken in conjunction with the accompanying drawings and examples.
Example 1:
a semiconductor device, comprising: at least one cell;
each unit comprising:
as shown in fig. 3, the semiconductor substrate material as a support layer forms a collector region 10 having a first doping characteristic;
a semiconductor layer having a second doping characteristic on the collector region 10 forming a drift region 20;
a semiconductor layer having a first doping characteristic located above the drift region 20 forming a well region 11;
a semiconductor layer having a second doping characteristic over the well region 11 forming an emitter region 21;
an insulating layer covering the collector region 10, the drift region 20, the well region 11 and the side of the emitter region 21 forms an insulated gate 30, which may be silicon oxide or other insulating layers;
the conductive layer above the insulated gate 30 forms a gate electrode 41, which may be doped polysilicon or other conductive layer;
a conductive thin layer located above the emitter region 21 forms an emitter metal electrode 43 and a conductive layer located below the collector region 10 forms a collector metal electrode 42;
a conductive layer located on the side of the collector region 10 and the drift region 20, which is different from the side of the insulated gate 30, forms a well contact electrode 42';
an insulating passivation layer 31 on the other side surface of the collector metal electrode 42; the insulating passivation layer may be a composite layer;
as shown in fig. 11 and 12, functional units 10 to 43 are formed, and on a wafer, one or more functional units or units turned over in a left-right mirror image are pressed by a mechanical pressure 2 in a repeated or interval repeated manner, and are respectively connected with an interconnection metal 3 and a metal bottom plate 4 up and down to form a semiconductor device; or cutting a portion of a wafer comprising the semiconductor device to form the semiconductor device.
Unqualified cells 1 can be isolated by isolating the emitter metal electrodes 43 on the uppermost layer of the cell;
as shown in fig. 13, a method for fabricating a semiconductor device unit includes:
as shown in fig. 4, a second semiconductor thin layer 20 having a second doping characteristic is formed on the first semiconductor thin layer 10 having the first doping characteristic by epitaxy, deposition or other suitable method;
forming a third semiconductor thin layer 11 having the first doping characteristic by epitaxy, deposition or other suitable method on the second semiconductor thin layer 20;
a fourth semiconductor thin layer 21 with a second doping characteristic is formed on the third semiconductor thin layer 11 by epitaxy, deposition or other suitable methods;
as shown in fig. 5, by etching, etching or other suitable methods, a functional region having a positive bevel or vertical side is formed on the first thin semiconductor layer 10 extending from the surface of the fourth thin semiconductor layer 21 to the upper side of the first thin semiconductor layer 10 or extending into a portion of the first thin semiconductor layer 10, and includes the second thin semiconductor layer 20, the third thin semiconductor layer 11 and the fourth thin semiconductor layer 21;
as shown in fig. 6, a first insulating thin layer 30 is formed over the first semiconductor thin layer 10 including the side surfaces of the second semiconductor thin layer 20, the third semiconductor thin layer 11, the fourth semiconductor thin layer 21, and the surface of the fourth semiconductor thin layer 21 by oxidation, deposition, or other suitable methods;
as shown in fig. 7, a first conductive thin layer 41 is formed over the first insulating thin layer 30, and the first conductive thin layer 41 is patterned;
as shown in fig. 8 and 9, the first insulating thin layer 30 is patterned, and a conductive layer 42' is formed and patterned over the first semiconductor thin layer 10, the second semiconductor thin layer 20, and the first insulating thin layer 30;
as shown in fig. 10, a third conductive thin layer 43 is formed over the fourth semiconductor thin layer 21 and patterned;
a second insulating thin layer 31 is formed and patterned on the first conductive thin layer 41, the first insulating thin layer 30, the third conductive thin layer 43, and the second conductive thin layer 42;
on the surface of the first semiconductor thin layer 10, on the other side surface with respect to the surface of the third conductive thin layer 43, a conductive thin layer second conductive thin layer 42 is formed.
The first doping characteristic can be N-type doping or P-type doping, and the second doping characteristic is P-type doping or N-type doping, which are different and correspond to each other.
The first semiconductor thin layer is a collector region after the unit is manufactured;
the second semiconductor thin layer is a drift region after the unit is manufactured;
the third semiconductor thin layer is a well region after the unit is manufactured;
the fourth semiconductor thin layer is an emitting region after the unit is manufactured;
the first insulating thin layer is an insulated gate after the unit is manufactured;
the second insulating thin layer is an insulating passivation layer after the unit is manufactured;
the first conductive thin layer is a gate electrode after the cell is manufactured;
the second conductive thin layer is a collector metal electrode after the unit is manufactured;
the conductive layer is a well contact electrode after the cell is manufactured;
the third conductive thin layer is an emitter metal electrode after the unit is manufactured;
the present invention is not limited to the above embodiments, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the claims of the present invention which are filed as the application.

Claims (10)

1. A semiconductor device cell, comprising: the semiconductor device comprises a laminated layer formed by stacking semiconductor material layers with two doping characteristics, a gate control structure and an insulating passivation layer (31);
the laminated layer is of a boss structure, the upper bottom surface is smaller than the lower bottom surface, and the side surface of the boss is provided with a positive bevel angle or right angle structure;
the insulating passivation layer (31) is arranged on the side face of the laminated layer and is matched with the positive bevel angle or right angle structure to form a cubic structure with the laminated layer;
the gate control structure is arranged between the insulating passivation layer (31) and the layer stack.
2. A semiconductor device cell according to claim 1, wherein the laminated layer includes: the collector region (10), the drift region (20), the emitter region (11) and the emitter region (21) are sequentially arranged from bottom to top;
wherein the collector region (10) and the emitter region (21) have a first doping characteristic;
the drift region (20) and the emitter region (11) have a second doping characteristic;
the first doping characteristic is N-type doping or P-type doping, and the second doping characteristic is P-type doping or N-type doping;
the side surface of the laminated layer is of a positive bevel angle or right-angle structure, the upper edge of the laminated layer is smaller than or equal to the lower edge of the laminated layer, and the laminated layer sequentially penetrates through the well emitting region (21), the emitting region (11) and the drift region (20) from top to bottom and is in contact with or inserted into the collector region (10).
3. A semiconductor device unit as claimed in claim 1, characterized in that the number of insulating passivation layers (31) is two, which are respectively arranged in the positive bevel or right angle structure of the side faces of the layer stack, the shape of which is adapted to the positive bevel or right angle structure, and the depth of the first insulating passivation layer (31) is smaller than the depth of the second insulating passivation layer (31).
4. A semiconductor device cell according to claim 3, wherein the cell further comprises: a well contact electrode (42');
the gate control structure includes: an insulated gate (30) and a gate electrode (41);
the gate electrode (41) is disposed under a first one of the insulating passivation layers (31), and the well contact electrode (42') is disposed under a second one of the insulating passivation layers (31);
the gate electrode (41) is arranged between the laminated layer and the gate electrode (41) and the first insulating passivation layer (31);
the gate electrode (41) is arranged between the layer stack and a well contact electrode (42') and a second one of the insulating passivation layers (31).
5. A semiconductor device cell according to claim 1, wherein the cell further comprises: an emitter metal electrode (43) and a collector metal electrode (42);
the emitter metal electrode (43) is provided above the laminated layer, and the collector metal electrode (42) is provided below the laminated layer.
6. A semiconductor device, characterized in that it comprises at least one cell according to any one of claims 1 to 5;
on the same wafer, the units or the units turned over in a left-right mirror image mode are fixedly connected with the interconnection metal (3) and the metal bottom plate (4) in a repeated or interval repeated mode, and therefore the semiconductor device is formed.
7. A method for manufacturing a semiconductor device unit is characterized by comprising the following steps:
sequentially and alternately stacking layer structures formed by semiconductor materials with two doping characteristics to form a layer stack;
manufacturing a structure with a positive bevel angle or a right angle on the side surface of the laminated layer by an etching and corrosion method, wherein the positive bevel angle or the right angle structure enters the bottommost layer of the laminated layer from top to bottom;
manufacturing a gate control structure in the positive bevel angle or right angle structure;
an insulating passivation layer (31) is fabricated and patterned on the gate control structure within the positive bevel or right angle structure on the side of the laminate layer.
8. The method of claim 7, wherein said sequentially forming thin films of semiconductor material having two doping characteristics into alternating stacks to form a stack of layers comprises:
forming a drift region (20) by epitaxial, deposition or other suitable method to manufacture a semiconductor film with a second doping characteristic on the semiconductor material with the first doping characteristic of the collector region (10);
forming an emitter region (11) by forming a semiconductor film with a first doping characteristic by epitaxy, deposition or other suitable method on the drift region (20);
over the emitter region (11), a semiconductor film having a second doping characteristic is formed by epitaxy, deposition or other suitable method to form an emitter region (21).
9. The method of claim 8, wherein said fabricating a gate control structure within said positive bevel or right angle structure comprises:
forming a first insulating thin layer to form an insulating gate (30) on the collector region (10) including the drift region (20), the emitter region (11), the side surface of the well region (21) and the surface of the well region (21) by oxidation, deposition or other suitable methods;
and forming a gate electrode (41) by making and patterning a first conductive thin layer on the insulated gate (30) and under a first one of the insulating passivation layers (31);
patterning the first insulating thin layer to form an insulated gate (30), and manufacturing and patterning a conductive layer under a second insulating passivation layer (31) to form a well contact electrode (42');
and manufacturing and patterning a third conductive thin layer on the well emitting region (21) to form an emitter metal electrode (43).
10. The method of claim 7, further comprising, after fabricating and patterning an insulating passivation layer (31) on the gate control structure within the positive bevel or right angle structure on the side of the stack layer: a second conductive thin layer is fabricated and patterned under the layer stack to form a collector metal electrode (42).
CN201910937911.XA 2019-09-30 2019-09-30 Semiconductor device unit, manufacturing method thereof and formed device Pending CN112582460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910937911.XA CN112582460A (en) 2019-09-30 2019-09-30 Semiconductor device unit, manufacturing method thereof and formed device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910937911.XA CN112582460A (en) 2019-09-30 2019-09-30 Semiconductor device unit, manufacturing method thereof and formed device

Publications (1)

Publication Number Publication Date
CN112582460A true CN112582460A (en) 2021-03-30

Family

ID=75116122

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910937911.XA Pending CN112582460A (en) 2019-09-30 2019-09-30 Semiconductor device unit, manufacturing method thereof and formed device

Country Status (1)

Country Link
CN (1) CN112582460A (en)

Similar Documents

Publication Publication Date Title
JP5011681B2 (en) Semiconductor device
US9576841B2 (en) Semiconductor device and manufacturing method
CN103367356B (en) There is the semiconductor element of nitride layer
KR101955055B1 (en) Power semiconductor device and method of fabricating the same
CN103975438A (en) Vertical gan jfet with gate and source electrodes on regrown gate
JP6713669B2 (en) Stack type III-V semiconductor diode
US7939887B2 (en) Active semiconductor component with a reduced surface area
US20200258991A1 (en) Semiconductor device and method of manufacturing semiconductor device
US20070042549A1 (en) Semiconductor device having reduced effective substrate resistivity and associated methods
KR100722909B1 (en) Semiconductor device
CN114664922A (en) IGBT semiconductor structure
JP7422799B2 (en) Power semiconductor devices, package structures and electronic devices
JP5087831B2 (en) Semiconductor device and manufacturing method thereof
KR20120112217A (en) Schottky diode and production method therefor
CN112582460A (en) Semiconductor device unit, manufacturing method thereof and formed device
US7683454B2 (en) MOS power component with a reduced surface area
KR101893673B1 (en) Transient voltage suppressor and manufacturing method thereof
CN216793695U (en) MOSFET device integrated with junction barrier Schottky
US8604515B2 (en) Bidirectional protection component
US11177360B2 (en) Semiconductor device
EP4006990A1 (en) Semiconductor device with a side surface having different partial regions
US20230326974A1 (en) Semiconductor diode and manufacturing method
CN108922925B (en) Power device protection chip and manufacturing method thereof
JP2015084444A (en) Semiconductor device
CN115863168A (en) Manufacturing method and structure of high-voltage bidirectional thyristor

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination