CN112580286A

CN112580286A - Multithreading synthesis method and device

Info

Publication number: CN112580286A
Application number: CN202011503750.2A
Authority: CN
Inventors: 王宁; 李元策; 刘奎; 张青
Original assignee: Gowin Semiconductor Corp
Current assignee: Gowin Semiconductor Corp
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2021-03-30
Anticipated expiration: 2040-12-18
Also published as: CN112580286B

Abstract

The invention discloses a multithreading comprehensive method and a device, wherein the method comprises the following steps: splitting the original netlist according to the determined splitting parameters to obtain at least two sub netlists corresponding to the original netlist; creating at least two sub threads according to all the sub netlists obtained by splitting; starting all the created sub threads and executing comprehensive operation on all the sub netlists in parallel to obtain a comprehensive sub netlist corresponding to each sub netlist; and merging the synthesized sub netlists corresponding to all the sub netlists to obtain the synthesized netlist corresponding to the original netlist. Therefore, the method can split the original netlist into at least two sub-netlists and perform parallel synthesis on all the sub-netlists through the created sub-threads, so that the execution efficiency of the FPGA synthesis tool is improved, and the development and design efficiency of the FPGA is improved.

Description

Multithreading synthesis method and device

Technical Field

The invention relates to the technical field of FPGA (field programmable gate array), in particular to a multithreading comprehensive method and a multithreading comprehensive device.

Background

In the design flow of an FPGA (Field Programmable Gate Array), a netlist (netlist) is a text file for describing the connection relationship between circuit elements, and a complex netlist can be understood as being composed of several modules with typical logic functions and a control circuit, wherein common modules include registers, counters, arithmetic and logic operation units, memories, and the like.

With the development of the FPGA industry, the size of the netlist becomes larger and larger, and millions or even tens of millions of unit netlists are layered endlessly. Practice shows that when the FPGA synthesis tool synthesizes these large-scale netlists, the CPU on the computer needs to be relied on, and when the large-scale netlists are synthesized by using the conventional netlist synthesis method, the running time of the CPU will be very long, which seriously affects the execution efficiency of the FPGA synthesis tool. Therefore, how to improve the execution efficiency of the FPGA synthesis tool when synthesizing the large-scale netlist is very important.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a multithreading synthesis method and device, which can improve the execution efficiency of an FPGA synthesis tool by splitting an original netlist into a plurality of sub-netlists and performing multithreading parallel synthesis.

In order to solve the above technical problem, a first aspect of the present invention discloses a multithreading synthesis method, including:

splitting an original netlist according to the determined splitting parameters to obtain at least two sub netlists corresponding to the original netlist;

creating at least two sub threads according to all the sub netlists, starting all the created sub threads to execute synthesis operation on all the sub netlists in parallel, and obtaining a synthesized sub netlist corresponding to each sub netlist;

and merging the synthesized sub netlists corresponding to all the sub netlists to obtain the synthesized netlist corresponding to the original netlist.

As an optional implementation manner, in the first aspect of the present invention, the splitting parameter includes a total number N of the sub netlist, where N is less than or equal to a predetermined maximum thread number and is an integer greater than or equal to 2;

splitting the original netlist according to the determined splitting parameters to obtain at least two sub netlists corresponding to the original netlist, wherein the step of splitting the original netlist according to the determined splitting parameters comprises the following steps:

splitting an original netlist into N sub netlists with the same resource quantity or matched resource quantity according to the resource quantity of the original netlist and the internal connection relation of the original netlist;

and traversing the boundary of the original netlist, and adding independent resources into the corresponding sub-netlists according to the internal connection relation of the original netlist to obtain the sub-netlists corresponding to the original netlist.

searching all output ports and all input ports of the original netlist, and dividing all the output ports into N output port groups;

for each output port group, creating a sub netlist with all output ports included in the output port group as starting nodes as a sub netlist corresponding to the output port group, starting to traverse forwards at the same time by all the starting nodes of the output port group, adding a new node into the sub netlist corresponding to the output port group when traversing to a new node which is not traversed, continuing to traverse forwards until traversing to a traversed node which is traversed, and creating an input port of the sub netlist corresponding to the output port group based on the traversed node when traversing to the traversed node;

and when all input ports of the original netlist are traversed, determining the sub-netlists corresponding to all the output port groups as the sub-netlists corresponding to the original netlist.

As an alternative implementation, in the first aspect of the present invention, the method further includes:

for each output port group, when traversing to a traversed node and after creating an input port of a sub-netlist corresponding to the output port group based on the traversed node, judging whether the traversed node exists in the sub-netlist corresponding to the other output port group, and when the judgment result is yes, creating an incidence relation between the input port of the sub-netlist corresponding to the output port group and an output port of the sub-netlist corresponding to the other output port group, wherein when the traversed node exists in the sub-netlist corresponding to the other output port group, the traversed node is the output port of the sub-netlist corresponding to the other output port group.

As an optional implementation manner, in the first aspect of the present invention, the merging all the synthesized sub-netlists corresponding to the sub-netlists to obtain the synthesized netlist corresponding to the original netlist includes:

determining an input port and an output port of each synthesized sub netlist;

and connecting the input port and the output port associated with each association relation according to all the association relations established in advance to obtain a synthesized netlist corresponding to the original netlist.

As an optional implementation manner, in the first aspect of the present invention, after all the sub-threads created by the startup perform a synthesis operation on all the sub-netlists in parallel to obtain a synthesized sub-netlist corresponding to each of the sub-netlists, the method further includes:

judging whether the target information corresponding to the currently executed synthesis operation on all the sub netlists in parallel meets the predetermined synthesis end condition;

and when the target information is judged not to meet the synthesis end condition, adjusting the splitting parameter, and triggering and executing the step of splitting the original netlist according to the determined splitting parameter to obtain at least two sub netlists corresponding to the original netlist.

As an optional implementation manner, in the first aspect of the present invention, the target information includes a running time corresponding to the currently parallel execution of the synthesis operation on all the sub netlists and/or the synthesized netlist;

wherein the judging whether the target information corresponding to the currently parallel synthesis operation performed on all the sub netlists meets a predetermined synthesis end condition comprises:

when the target information only comprises the running time length, judging whether the running time length is greater than a predetermined maximum running time length, and when the running time length is greater than the maximum running time length, determining that the target information does not meet a predetermined comprehensive ending condition;

when the target information only comprises the synthesized netlist, judging whether the synthesized netlist is matched with the original netlist, and when the synthesized netlist is judged not to be matched with the original netlist, determining that the target information does not meet a predetermined synthesis end condition;

when the target information comprises the operation duration and the synthesized netlist, judging whether the synthesized netlist is matched with the original netlist, and when the synthesized netlist is judged not to be matched with the original netlist, determining that the target information does not meet a predetermined synthesis end condition; when the synthesized netlist is judged to be matched with the original netlist, judging whether the operation time length is longer than a predetermined maximum operation time length, and when the operation time length is judged to be longer than the maximum operation time length, determining that the target information does not meet a predetermined synthesis ending condition; alternatively, the first and second electrodes may be,

when the target information comprises the operation duration and the synthesized netlist, judging whether the operation duration is greater than a predetermined maximum operation duration, and when the operation duration is greater than the maximum operation duration, determining that the target information does not meet a predetermined synthesis ending condition; and when the operation duration is not longer than the maximum operation duration, judging whether the synthesized netlist is matched with the original netlist, and when the synthesized netlist is judged not to be matched with the original netlist, determining that the target information does not meet the predetermined synthesis end condition.

As an optional implementation manner, in the first aspect of the present invention, after determining that the target information does not satisfy the comprehensive end condition, the method further includes:

determining total splitting data of the original netlist, wherein the total splitting data comprises the accumulated splitting times of the original netlist or the accumulated splitting duration of the original netlist;

judging whether the total split data is smaller than a predetermined data threshold value;

when the total split data is judged to be smaller than the data threshold value, triggering and executing the step of adjusting the split parameters;

and when the total splitting data is judged to be not less than the data threshold, determining the shortest operation time length in the operation time lengths corresponding to the comprehensive operation executed on all the sub netlists obtained by splitting after the original netlist is split historically, and determining the splitting parameter corresponding to the shortest operation time length as the splitting parameter for splitting the original netlist at the last time.

As an optional implementation manner, in the first aspect of the present invention, after the merging all the synthesized sub-netlists corresponding to the sub-netlists to obtain the synthesized netlist corresponding to the original netlist, the method further includes:

counting the running time corresponding to the comprehensive operation executed by all the sub netlists obtained by splitting in parallel at present;

judging whether the running time corresponding to the comprehensive operation executed on all the sub netlists obtained by splitting in parallel is shorter than the predetermined shortest running time or not;

and when the judgment result is yes, updating the shortest operation time length to the operation time length corresponding to the current parallel operation of executing the comprehensive operation on all the split sub netlists, and establishing the corresponding relation between the updated shortest operation time length and the split parameters used for splitting the original netlist.

The second aspect of the present invention discloses a multithreading synthesis apparatus, including:

the splitting module is used for splitting the original netlist according to the determined splitting parameters to obtain at least two sub netlists corresponding to the original netlist;

the creating module is used for creating at least two sub threads according to all the sub netlists;

the parallel synthesis module is used for starting all the created sub-threads to perform synthesis operation on all the sub-netlists in parallel to obtain a synthesized sub-netlist corresponding to each sub-netlist;

and the merging module is used for merging all the synthesized sub netlists corresponding to the sub netlists to obtain the synthesized netlist corresponding to the original netlist.

As an optional implementation manner, in the second aspect of the present invention, the splitting parameter includes a total number N of the sub netlist, where N is less than or equal to a predetermined maximum number of threads and is an integer greater than or equal to 2;

the splitting module splits the original netlist according to the determined splitting parameters, and the specific way of obtaining at least two sub netlists corresponding to the original netlist is as follows:

As an alternative embodiment, in the second aspect of the present invention, the apparatus further comprises:

and the association module is used for judging whether the traversed node exists in the sub-netlists corresponding to other output port groups or not after the input port of the sub-netlists corresponding to the output port groups is created based on the traversed node for each output port group, and creating the association relation between the input port of the sub-netlist corresponding to the output port group and the output port of the sub-netlist corresponding to the other output port groups when the judgment result is yes, wherein the traversed node is the output port of the sub-netlist corresponding to the other output port groups when the traversed node exists in the sub-netlists corresponding to the other output port groups.

As an optional implementation manner, in the second aspect of the present invention, the merging module merges all the synthesized sub-netlists corresponding to the sub-netlists, and a specific manner of obtaining the synthesized netlist corresponding to the original netlist is as follows:

determining an input port and an output port of each synthesized sub netlist;

the judging module is used for judging whether target information corresponding to the currently parallel comprehensive operation performed on all the sub netlists meets a predetermined comprehensive ending condition after the parallel comprehensive module starts and creates all the sub threads to perform the comprehensive operation on all the sub netlists in parallel to obtain a comprehensive sub netlist corresponding to each sub netlist;

and the adjusting module is used for adjusting the splitting parameter when the judging module judges that the target information does not meet the synthesis ending condition, and triggering the splitting module to execute the operation of splitting the original netlist according to the determined splitting parameter to obtain at least two sub netlists corresponding to the original netlist.

As an optional implementation manner, in the second aspect of the present invention, the target information includes a running time corresponding to the currently parallel execution of the synthesis operation on all the sub netlists and/or the synthesized netlist;

the specific way for judging whether the target information corresponding to the currently parallel synthesis operation executed on all the sub netlists meets the predetermined synthesis end condition by the judgment module is as follows:

a determining module, configured to determine total splitting data of the original netlist after the determining module determines that the target information does not satisfy the synthesis end condition, where the total splitting data includes an accumulated splitting frequency of the original netlist or an accumulated splitting duration of the original netlist;

the judging module is further configured to judge whether the total split data is smaller than a predetermined data threshold, and when the total split data is judged to be smaller than the data threshold, trigger the adjusting module to perform the operation of adjusting the split parameters;

the determining module is further configured to determine, when the judging module judges that the total split data is not less than the data threshold, the shortest operation duration among the operation durations corresponding to the comprehensive operations performed on all the split sub netlists in parallel after the original netlist is split historically; and determining the splitting parameter corresponding to the shortest operation time as the splitting parameter for splitting the original netlist for the last time.

the statistical module is used for counting the running time corresponding to the comprehensive operation executed by all the sub netlists obtained by splitting at present in parallel after the merging module merges the synthesized sub netlists corresponding to all the sub netlists to obtain the synthesized netlist corresponding to the original netlist;

the judging module is further configured to judge whether an operation duration corresponding to the currently parallel execution of the comprehensive operation on all the sub netlists obtained by splitting is less than a predetermined shortest operation duration;

the updating module is used for updating the shortest running time to the running time corresponding to the comprehensive operation executed by all the sub netlists obtained by splitting the current parallel pair when the judging module judges that the running time corresponding to the comprehensive operation executed by all the sub netlists obtained by splitting the current parallel pair is shorter than the shortest running time;

and the establishing module is used for establishing the corresponding relation between the updated shortest running time and the splitting parameter used for splitting the original netlist at present.

A third aspect of the present invention discloses another multithreading synthesis apparatus, including:

a memory storing executable program code;

a processor coupled with the memory;

the processor calls the executable program code stored in the memory to execute part or all of the steps in the multi-thread synthesis method disclosed by the first aspect of the invention.

In a fourth aspect of the present invention, a computer storage medium is disclosed, which stores computer instructions for performing some or all of the steps of the multi-thread synthesis method disclosed in the first aspect of the present invention when the computer instructions are invoked.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

in the embodiment of the invention, when the original netlist is synthesized, the original netlist is split into a plurality of sub netlists, all the split sub netlists are subjected to synthesis operation in parallel through the created sub threads to obtain a synthesized sub netlist corresponding to each sub netlist, and all the synthesized sub netlists are merged to obtain a synthesized netlist corresponding to the original netlist. Therefore, the execution efficiency of the FPGA comprehensive tool can be improved by splitting the original netlist into a plurality of sub-netlists and performing multi-thread parallel synthesis, so that the development and design efficiency of the FPGA can be improved, and the use experience of a user on the FPGA comprehensive tool can be improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a flow chart of a multithreading synthesis method disclosed in an embodiment of the present invention;

FIG. 2 is a flow chart of another multi-thread synthesis method disclosed in the embodiments of the present invention;

FIG. 3 is a flow chart of another multithreading integration method disclosed in the embodiments of the present invention;

FIG. 4 is a schematic structural diagram of a multithreading synthesis apparatus according to an embodiment of the present invention;

FIG. 5 is a block diagram of another exemplary multithread synthesis apparatus according to the present invention;

FIG. 6 is a schematic structural diagram of another multithread synthesis apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "first," "second," and the like in the description and claims of the present invention and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product, port or port that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, product, port or port.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The invention discloses a multithreading synthesis method and a multithreading synthesis device, which can divide an original netlist into at least two sub-netlists and perform parallel synthesis on all the sub-netlists through a plurality of created sub-threads, so that the execution efficiency of an FPGA synthesis tool is improved, the development and design efficiency of an FPGA is further improved, and the use experience of a user on the FPGA synthesis tool is improved. The following are detailed below.

Example one

Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a multithread synthesis method according to an embodiment of the present invention. The method described in fig. 1 may be applied to an FPGA synthesis tool, and the embodiment of the present invention is not limited. As shown in fig. 1, the method may include the operations of:

101. and the FPGA comprehensive tool splits the original netlist according to the determined splitting parameters to obtain at least two sub netlists corresponding to the original netlist.

In the embodiment of the invention, the original netlist is obtained by analyzing the RTL design file, wherein the original netlist is a circuit-level netlist. Optionally, the splitting parameter is used to implement splitting control on the original netlist, and may include a total number N of the sub netlists obtained by splitting, that is, the FPGA synthesis tool splits the original netlist to obtain N sub netlists, where N is an integer greater than or equal to 2 and N is less than or equal to a maximum number of threads supported by the FPGA synthesis tool. Still further optionally, the sub netlist obtained by splitting the original netlist is a sub netlist with the same size or similar scale, so that the execution time spent by the FPGA synthesis tool in subsequently executing the created sub threads is not very different.

In an alternative embodiment, before performing step 101, the method may further include the following operations:

determining the netlist size of the original netlist by the FPGA comprehensive tool, and judging whether the netlist size of the original netlist exceeds a preset netlist size threshold value or not; when the judgment result is yes, triggering and executing the step 101; and when the judgment result is negative, the FPGA synthesis tool can directly execute synthesis operation aiming at the original netlist to obtain a synthesized netlist corresponding to the original netlist.

Therefore, the optional embodiment can adaptively select a matched comprehensive mode according to the netlist size (such as scale magnitude) of the original netlist before the original netlist is synthesized, that is, can adaptively select a comprehensive mode with higher execution efficiency of the FPGA comprehensive tool after the size of the original netlist is determined, so that the universal applicability of the FPGA comprehensive tool is facilitated, and in addition, the use experience of a user using the FPGA comprehensive tool can be improved.

102. The FPGA synthesis tool creates at least two child threads from all the child netlists.

In the embodiment of the present invention, one child thread corresponds to at least one child netlist, preferably, one child thread corresponds to one child netlist, and the child threads are completely independent and have no data interaction, that is: the number of the sub threads created by the FPGA comprehensive tool is the same as that of the sub netlists, so that the execution time of the FPGA comprehensive tool can depend on the execution time corresponding to the sub thread with the longest execution time when the sub netlists are subjected to comprehensive operation in the subsequent parallel mode, the execution time of the FPGA comprehensive tool can be saved, and the comprehensive efficiency of the FPGA comprehensive tool can be improved.

103. And starting all the created sub threads by the FPGA comprehensive tool and executing comprehensive operation on all the sub netlists in parallel to obtain the comprehensive sub netlists corresponding to each sub netlist.

In the embodiment of the present invention, preferably, after the FPGA synthesis tool creates the child threads, all the child threads are simultaneously started to execute the synthesis operation on the corresponding child netlist, so that it can be further ensured that the execution time of the FPGA synthesis tool depends on the execution time corresponding to the child thread with the longest execution time.

104. And the FPGA synthesis tool merges the synthesized sub netlists corresponding to all the sub netlists to obtain the synthesized netlist corresponding to the original netlist.

It should be noted that, since step 102 relates to the step of creating a thread, step 103 relates to the synthesis step, and step 104 relates to the step of merging to obtain the synthesized netlist, in other embodiments, the FPGA synthesis tool may only perform steps 102 to step 104, and step 101 and/or the step performed before step 101 may be performed by a netlist processing device, which may be integrated in the FPGA synthesis tool or may exist independently of the FPGA synthesis tool, when it exists independently of the FPGA synthesis tool, the netlist processing device is mainly configured to split the original netlist according to the determined splitting parameters to obtain at least two sub netlists, and all the split sub netlists are provided for the FPGA synthesis tool to perform steps 102 to step 104.

Therefore, the method described in the embodiment of the invention can split the original netlist into at least two sub-netlists and perform parallel synthesis on all the sub-netlists through the created sub-threads, because the sub-threads are executed in parallel, the synthesis duration of the FPGA synthesis tool depends on the execution duration of the sub-thread with the longest execution duration, and because the execution duration of the sub-threads depends on the size or scale of the corresponding sub-netlist and the scale of each split sub-netlist is smaller than that of the original netlist, the multithreading parallel synthesis duration is not higher than that of the whole original netlist synthesized by a single thread, so that the execution efficiency of the FPGA synthesis tool is improved, the development and design efficiency of the FPGA is improved, and the use experience of the FPGA synthesis tool by a user is improved.

In an optional embodiment, the splitting parameter may include a total number N of the sub netlist, where N is an integer greater than or equal to 2 and less than or equal to a predetermined maximum number of threads.

In this optional embodiment, as an optional implementation, the splitting the original netlist according to the determined splitting parameter by the FPGA synthesis tool to obtain at least two sub-netlists corresponding to the original netlist may include:

the FPGA comprehensive tool splits the original netlist into N sub-netlists with the same resource quantity or matched resource quantity (namely approximate resource quantity) according to the resource quantity of the original netlist and the internal connection relation of the original netlist;

and traversing the boundary of the original netlist by the FPGA comprehensive tool, and adding the independent resources into the corresponding sub-netlists according to the internal connection relation of the original netlist to obtain the sub-netlists corresponding to the original netlist.

In this alternative embodiment, the FPGA synthesis tool allocates relatively independent resources to the same sub-netlist according to the internal connection relationship of the original netlist, for example, resources having mathematical equation relationship or resources in which multiple nodes can map out 1 BSRAM (Burst pipelined synchronous static RAM) can be placed in the same sub-netlist.

Therefore, the optional implementation method can equally or approximately equally divide the resources included in the original netlist according to the number of the resources included in the original netlist and the internal connection relation, so that the resources of each sub-netlist are equivalent, the running time of each sub-thread is equivalent when the sub-netlists are synthesized in parallel through the created sub-threads, the maximum running time of the FPGA comprehensive tool during the synthesis is dependent on the running time corresponding to the sub-thread with the longest running time, and the optimization of the CPU resources used by the FPGA comprehensive tool during the synthesis is realized while the original netlist is intelligently split.

In this optional embodiment, as another optional implementation, the splitting the original netlist according to the determined splitting parameter by the FPGA synthesis tool to obtain at least two sub-netlists corresponding to the original netlist may include:

searching all output ports and all input ports of the original netlist by the FPGA comprehensive tool, and dividing all the output ports into N output port groups, wherein the number of the output ports included in each output port group is the same or matched (namely approximate);

for each output port group, the FPGA synthesis tool creates a sub netlist which takes all output ports included in the output port group as starting nodes as the sub netlist corresponding to the output port group, simultaneously traverses forwards by starting with all the starting nodes of the output port group, adds a new node into the sub netlist corresponding to the output port group when traversing to the new node which is not traversed, continues to traverse forwards until traversing to the traversed node which is traversed, and creates an input port of the output port group corresponding to the sub netlist based on the traversed node when traversing to the traversed node;

and when all input ports of the original netlist are traversed, determining the sub-netlists corresponding to all the output port groups as the sub-netlists corresponding to the original netlist by the FPGA synthesis tool.

In this optional embodiment, further optionally, the method may further include the following operations:

for each output port group, when traversing to a traversed node and after creating an input port of the output port group corresponding to the sub-netlist based on the traversed node, the FPGA synthesis tool judges whether the traversed node exists in the sub-netlist corresponding to the other output port group, and when the judgment result is yes, creates an incidence relation between the input port of the output port group corresponding to the sub-netlist and an output port of the other output port group corresponding to the sub-netlist, wherein when the traversed node exists in the sub-netlist corresponding to the other output port group, the traversed node is the output port of the other output port group corresponding to the sub-netlist.

Alternatively, the association relationship between the input port of the output port group corresponding sub netlist and the output port of the other output port group corresponding sub netlist may be specifically set to the same and unique port identifier (port name) for the input port and the output port.

Therefore, the optional implementation method can equally divide or approximately equally divide the output ports into N output port groups and traverse forwards by taking the output port included in each output port group as a starting node, thereby realizing the intelligent splitting of the original netlist. In addition, during the forward traversal, if the traversed node is traversed to the traversed node, the incidence relation between the input port of the traversed node as one output port group and the output port of the traversed node as the other output port group can be intelligently established, the subsequent continuous forward traversal from the traversed node can be avoided, further the waste of CPU resources is reduced, in addition, the established incidence relation can also be used for the combination of the subsequent combined sub-netlists, and the combination efficiency and the combination accuracy of the combined sub-netlists are improved.

In another alternative embodiment, each sub-netlist includes a corresponding input port and an output port, and for any sub-netlist, if the node corresponding to the input port of the sub-netlist is the same as the node corresponding to the output port of another sub-netlist, the FPGA synthesis tool further creates an association (or correspondence) between the input port of the sub-netlist and the output port of another sub-netlist. The combining, by the FPGA synthesis tool, the synthesized sub-netlists corresponding to all the sub-netlists to obtain the synthesized netlist corresponding to the original netlist may include:

determining an input port and an output port of each synthesized sub netlist by the FPGA synthesis tool;

and the FPGA synthesis tool connects the input port and the output port associated with each incidence relation according to all incidence relations established in advance to obtain a synthesized netlist corresponding to the original netlist.

Therefore, the optional embodiment can also merge the synthesized sub-netlists according to the incidence relation between the input port and the output port, so that the accuracy and the merging efficiency of subsequently merging the synthesized sub-netlists can be improved, and further, the efficiency of obtaining the synthesized netlist and the matching degree of the synthesized netlist and the original netlist can be improved.

Taking N sub netlists and one sub thread corresponding to one sub netlist as an example, the principle or flow of the FPGA synthesis tool for multi-thread synthesis may be as shown in fig. 2, and fig. 2 is a schematic flow diagram of another multi-thread synthesis method disclosed in the embodiment of the present invention. As shown in fig. 2, after the RTL design file is parsed to obtain the original netlist, the original netlist is split or divided into N sub-netlists: and (3) the sub netlist [1] to the sub netlist [ N ], and a synthesis sub thread corresponding to each sub netlist is created: and synthesizing the sub-thread [1] to the sub-net list [ N ] in parallel through the sub-thread [1] to the sub-thread [ N ] to obtain a synthesized sub-net list [1] to a synthesized sub-net list [ N ] corresponding to the sub-net list [1] to the sub-net list [ N ], and finally merging the synthesized sub-net list [1] to the synthesized sub-net list [ N ] to obtain a synthesized net list.

Therefore, the multithreading synthesis method described in the embodiment of the invention can split the original netlist into at least two sub-netlists and perform parallel synthesis on all the sub-netlists through the created multiple sub-threads, and since the multiple sub-threads are executed in parallel, the synthesis duration of the FPGA synthesis tool depends on the execution duration of the sub-thread with the longest execution duration, and since the execution duration of the sub-threads depends on the size or scale of the corresponding sub-netlist and the scale of each split sub-netlist is smaller than that of the original netlist, the multithreading parallel synthesis duration is not higher than that of the single thread synthesis of the whole original netlist, so that the execution efficiency of the FPGA synthesis tool is improved, the development and design efficiency of the FPGA is improved, and the use experience of a user on the FPGA synthesis tool is improved. In addition, the original netlist can be split according to the number of output ports included in the original netlist or according to the resource number of the original netlist and the internal connection relation of the original netlist, so that the sizes of the split sub netlists are the same or similar, the running time of each sub thread is equivalent when the sub netlists are synthesized in parallel through the created sub threads, the maximum running time of the FPGA synthesis tool during synthesis depends on the running time corresponding to the sub thread with the longest running time, and the optimization of CPU resources used by the FPGA synthesis tool during synthesis is realized while the original netlist is split intelligently. In addition, when the original netlist is split in a forward traversal mode by taking the number of output ports included in the original netlist as a starting point, the incidence relation between the input port of one output port group which is a traversed node and the output port of the other output port group which is the traversed node is intelligently established, so that the subsequent forward traversal from the traversed node can be avoided, and further the waste of CPU resources is reduced. In addition, the sub-netlists after synthesis can be merged according to the incidence relation between the input port and the output port, so that the accuracy and the efficiency of merging the sub-netlists after synthesis can be improved, and the efficiency of obtaining the synthesized netlist and the matching degree of the synthesized netlist and the original netlist can be improved.

Example two

Referring to fig. 3, fig. 3 is a flowchart illustrating another multithread synthesis method according to an embodiment of the present invention. The method described in fig. 3 may be applied to an FPGA synthesis tool, and the embodiment of the present invention is not limited. As shown in fig. 3, the method may include the operations of:

201. and the FPGA comprehensive tool splits the original netlist according to the determined splitting parameters to obtain at least two sub netlists corresponding to the original netlist.

202. And the FPGA synthesis tool creates at least two sub-threads according to all the sub-netlists, and starts all the created sub-threads to execute synthesis operation on all the sub-netlists in parallel to obtain a synthesized sub-netlist corresponding to each sub-netlist.

203. And the FPGA synthesis tool merges the synthesized sub netlists corresponding to all the sub netlists to obtain the synthesized netlist corresponding to the original netlist.

It should be noted that, for other detailed descriptions of step 201 to step 203, please refer to the detailed descriptions of step 101, step 102 to step 103, and step 104 in the first embodiment, which is not repeated herein.

204. Judging whether the target information corresponding to the currently executed parallel synthesis operation on all the sub netlists meets the predetermined synthesis ending condition by the FPGA synthesis tool, and ending the process if the judgment result in the step 204 is yes; when the determination result of step 204 is no, step 205 may be triggered to be executed.

Optionally, the target information includes a running time and/or a synthesized netlist corresponding to the currently parallel synthesis operation performed on all the sub-netlists. The determining, by the FPGA synthesis tool, whether target information corresponding to the currently parallel execution of the synthesis operation on all the sub netlists meets a predetermined synthesis end condition may include:

when the target information only comprises the running duration, the FPGA comprehensive tool judges whether the running duration is longer than the predetermined maximum running duration, and when the running duration is judged to be longer than the maximum running duration, the target information is determined not to meet the predetermined comprehensive ending condition;

when the target information only comprises the synthesized netlist, the FPGA synthesis tool judges whether the synthesized netlist is matched with the original netlist, and when the synthesized netlist is judged not to be matched with the original netlist, the target information is determined not to meet the synthesis end condition determined in advance;

when the target information comprises the operation duration and the synthesized netlist, judging whether the synthesized netlist is matched with the original netlist by the FPGA synthesis tool, and when the synthesized netlist is judged not to be matched with the original netlist, determining that the target information does not meet the synthesis end condition determined in advance; when the synthesized netlist is matched with the original netlist, judging whether the running time is longer than the predetermined maximum running time, and when the running time is longer than the maximum running time, determining that the target information does not meet the predetermined synthesis ending condition; alternatively, the first and second electrodes may be,

when the target information comprises the operation time length and the synthesized netlist, judging whether the operation time length is longer than the predetermined maximum operation time length by the FPGA synthesis tool, and when the operation time length is longer than the maximum operation time length, determining that the target information does not meet the predetermined synthesis end condition; and when the operation duration is not longer than the maximum operation duration, judging whether the synthesized netlist is matched with the original netlist, and when the synthesized netlist is judged not to be matched with the original netlist, determining that the target information does not meet the predetermined synthesis ending condition.

It should be noted that, in other alternative embodiments, when the determination result in step 204 is negative, step 207 may also be directly triggered to be executed.

205. And determining total splitting data of the original netlist by the FPGA comprehensive tool, wherein the total splitting data comprises the accumulated splitting times of the original netlist or the accumulated splitting duration of the original netlist.

In the embodiment of the invention, the starting time of the accumulated splitting time of the original netlist is the time of initially splitting the original netlist, and the ending time of the accumulated splitting time of the original netlist can be the current real-time or the time of obtaining the synthesized netlist through the last merging.

206. Judging whether the total split data is smaller than a predetermined data threshold value by the FPGA comprehensive tool, and triggering to execute the step 207 when the judgment result in the step 206 is yes; when the determination result in step 206 is negative, step 208 is triggered to be executed.

207. The FPGA comprehensive tool adjusts the splitting parameters and triggers the execution of step 201.

When step 201 is triggered to be executed after step 207 is executed, the splitting parameter determined in step 201 is the splitting parameter adjusted in step 207.

208. And determining the shortest operation time length in the operation time lengths corresponding to the synthesis operation of all the split sub netlists after the original netlist is split historically by the FPGA synthesis tool.

In the embodiment of the invention, after the original netlist is split each time, the corresponding running time length exists for executing the comprehensive operation on all the split sub-netlists in parallel, and after the original netlist is split each time, the running time length corresponding to the parallel execution of the comprehensive operation on all the split sub-netlists can be as follows: parallel comprehensive duration; or, the sum of the parallel comprehensive time length, the netlist splitting time length and the sub-thread creating time length; or the sum of the parallel synthesis time length, the netlist splitting time length, the thread creating time length and the netlist merging time length. The parallel comprehensive duration is from the starting time of executing comprehensive operation on all sub netlists in parallel by all the sub threads which are started and created to the ending time of executing comprehensive operation on all the sub netlists in parallel, and the parallel comprehensive duration can also be directly understood as the longest running duration in the running durations corresponding to all the sub threads.

Most preferably, after the original netlist is split, the running time corresponding to the comprehensive operation executed on all the split sub-netlists in parallel comprises the sum of the parallel comprehensive time, the netlist splitting time, the thread creating time and the netlist merging time, so that the accuracy of the determined running time is improved, and the accuracy of evaluating the running efficiency of the FPGA comprehensive tool is improved.

209. And determining the splitting parameter corresponding to the shortest operation time as the splitting parameter for splitting the original netlist at the last time by the FPGA comprehensive tool.

In the embodiment of the present invention, after the step 209 is executed, the step 201 to the step 203 may be triggered and executed for the last time, so as to obtain a final synthesized netlist.

It should be noted that in other embodiments, the steps executed before step 209 may be understood as a procedure for determining the optimal splitting parameter, so as to provide the optimal splitting parameter for the final multithread synthesis. The process can be a simulation process, and can also be understood as a preparation process for splitting the netlist, creating the sub-thread, running the sub-thread and synthesizing the sub-netlist in parallel at the last time, and merging the synthesized sub-netlists to obtain the synthesized netlist.

In an alternative embodiment, after performing step 203, the method may further include the following operations:

the FPGA comprehensive tool counts the running time corresponding to the comprehensive operation executed on all the sub netlists obtained by splitting in parallel;

judging whether the running time corresponding to the comprehensive operation executed on all the sub netlists obtained by splitting in parallel by the FPGA comprehensive tool is shorter than the predetermined shortest running time or not;

and when the judgment result is yes, the FPGA comprehensive tool updates the shortest operation time length to the operation time length corresponding to the current parallel comprehensive operation executed on all the split sub-netlists, and establishes the corresponding relation between the updated shortest operation time length and the split parameters used for splitting the original netlist currently.

Further optionally, before the FPGA synthesis tool determines whether the running time corresponding to the synthesis operation performed on all the split sub netlists in parallel is less than the predetermined shortest running time, the method may further include the following operations:

judging whether the original netlist is split for the first time by the FPGA comprehensive tool; when the judgment result is yes, directly determining the running time corresponding to the comprehensive operation executed by all the sub netlists obtained by splitting the current parallel pair to be the shortest running time; and when the judgment result is negative, triggering and executing the operation of judging whether the running time corresponding to the comprehensive operation executed on all the sub netlists obtained by splitting at present is smaller than the predetermined shortest running time or not.

It can be seen that in the process of performing parallel synthesis operation for multiple times to obtain the synthesized netlist, the optional embodiment can also dynamically update the shortest operation time and establish a corresponding relationship between the shortest operation time and the corresponding splitting parameter, so as to improve the efficiency of determining the shortest operation time in step 208 and improve the efficiency of determining the splitting parameter corresponding to the shortest operation time in step 209.

In another alternative embodiment, before performing step 204, the method may further comprise the operations of:

determining the current use type of the original netlist by the FPGA comprehensive tool;

if the current usage type is the simulation usage type, triggering to execute step 204;

if the current usage type is the actual comprehensive usage type, the process may be ended.

Therefore, after the integrated netlist is obtained through combination, the optional embodiment can intelligently execute matched operation according to the current use type of the original netlist, and the use scene of the FPGA synthesis tool for multi-thread parallel synthesis is expanded, namely: the method can improve the operating efficiency of the FPGA comprehensive tool in an actual comprehensive scene, can obtain the optimal splitting parameter in a mode of carrying out multithreading parallel synthesis by splitting the original netlist through repeatedly adjusting the splitting parameter in a simulated use scene, can provide the optimal splitting parameter for the actual multithreading parallel synthesis in the actual comprehensive scene, can also provide a splitting parameter reference basis for splitting other netlists with the same or similar scales, and is further favorable for improving the operating efficiency for synthesizing other netlists.

Therefore, the method described in the embodiment of the invention can split the original netlist into at least two sub-netlists and perform parallel synthesis on all the sub-netlists through the created sub-threads, because the sub-threads are executed in parallel, the synthesis duration of the FPGA synthesis tool depends on the execution duration of the sub-thread with the longest execution duration, and because the execution duration of the sub-threads depends on the size or scale of the corresponding sub-netlist and the scale of each split sub-netlist is smaller than that of the original netlist, the multithreading parallel synthesis duration is not higher than that of the whole original netlist synthesized by a single thread, so that the execution efficiency of the FPGA synthesis tool is improved, the development and design efficiency of the FPGA is improved, and the use experience of the FPGA synthesis tool by a user is improved. In addition, after the combined netlist is obtained through combination, whether the information corresponding to the splitting and parallel synthesis meets the synthesis ending condition or not can be judged, if yes, the synthesis process can be ended, if not, the netlist can be continuously split again in a splitting parameter adjusting mode and the corresponding parallel synthesis process is executed, the flexibility of the multithread synthesis method is improved, when the multithread synthesis method is applied to a simulation scene, the optimal splitting parameter can be found through repeated splitting and repeated parallel synthesis, furthermore, the unlimited splitting and parallel synthesis can be avoided by setting the corresponding control condition, the optimal splitting parameter is intelligently determined according to the shortest operation time principle in the control condition, the optimal splitting parameter can be provided for actual synthesis, and a splitting parameter reference basis can be provided for other netlists with the same scale or similar scales, the running efficiency of the FPGA comprehensive tool can be further improved.

EXAMPLE III

Referring to fig. 4, fig. 4 is a schematic structural diagram of a multithread synthesis apparatus according to an embodiment of the present invention. The multithreading synthesis apparatus described in fig. 4 may be applied to an FPGA synthesis tool, and the embodiment of the present invention is not limited. As shown in fig. 4, the multithread synthesis apparatus may include:

the splitting module 301 is configured to split the original netlist according to the determined splitting parameters, so as to obtain at least two sub-netlists corresponding to the original netlist.

A creating module 302 for creating at least two child threads from all child netlists.

And the parallel synthesis module 303 is configured to start all the created sub-threads to perform a synthesis operation on all the sub-netlists in parallel, so as to obtain a synthesized sub-netlist corresponding to each sub-netlist.

And a merging module 304, configured to merge the synthesized sub-netlists corresponding to all the sub-netlists to obtain a synthesized netlist corresponding to the original netlist.

It should be noted that the splitting module 301 is an optional module of the multithread synthesis apparatus, that is, other apparatuses may perform splitting operation on the original netlist, and provide all the sub-netlists obtained by splitting to the multithread synthesis apparatus.

It can be seen that, by implementing the apparatus described in fig. 4, the original netlist can be split into at least two sub-netlists, and all the sub-netlists are subjected to parallel synthesis through the created multiple sub-threads, because the multiple sub-threads are executed in parallel, the synthesis duration of the original netlist depends on the execution duration of the sub-thread with the longest execution duration, and because the execution duration of the sub-threads depends on the size or scale of the corresponding sub-netlist, and the size of each split sub-netlist is smaller than that of the original netlist, the parallel synthesis duration of multiple threads is not higher than that of the single thread synthesis of the whole original netlist, so that the execution efficiency of the FPGA synthesis tool is improved, the development and design efficiency of the FPGA is improved, and the use experience of the FPGA synthesis tool by a user is improved.

In an alternative embodiment, the splitting parameter may include a total number N of the sub netlist, where N is an integer greater than or equal to 2 and less than or equal to a predetermined maximum number of threads.

In this optional embodiment, as an optional implementation, the specific way for the splitting module 301 to split the original netlist according to the determined splitting parameters to obtain at least two sub-netlists corresponding to the original netlist is as follows:

the splitting module 301 splits the original netlist into N sub-netlists with the same resource quantity or matched resource quantity according to the resource quantity of the original netlist and the internal connection relation of the original netlist;

the splitting module 301 traverses the boundary of the original netlist, and adds the independent resources to the corresponding sub-netlist according to the internal connection relationship of the original netlist, so as to obtain the sub-netlist corresponding to the original netlist.

In this alternative embodiment, the splitting module 301 allocates relatively independent resources to the same sub-netlist according to the internal connection relationship of the original netlist, for example, resources having mathematical equation relationship or resources in which a plurality of nodes can map out 1 BSRAM are placed in the same sub-netlist. Therefore, the optional implementation method can equally or approximately equally divide the resources included in the original netlist according to the number of the resources included in the original netlist and the internal connection relation, so that the resources of each sub-netlist are equivalent, the running time of each sub-thread is equivalent when the sub-netlists are synthesized in parallel through the created sub-threads, the maximum running time of the FPGA comprehensive tool during the synthesis is dependent on the running time corresponding to the sub-thread with the longest running time, and the optimization of the CPU resources used by the FPGA comprehensive tool during the synthesis is realized while the original netlist is intelligently split.

As another optional implementation, the specific way for the splitting module 301 to split the original netlist according to the determined splitting parameters to obtain at least two sub-netlists corresponding to the original netlist is as follows:

the splitting module 301 searches all output ports and all input ports of the original netlist, and divides all output ports into N output port groups, where the number of output ports included in each output port group is the same or matched (i.e. approximate);

for each output port group, the splitting module 301 creates a sub-netlist with all output ports included in the output port group as start nodes as a sub-netlist corresponding to the output port group, simultaneously traverses forward by starting with all start nodes of the output port group, adds a new node to the sub-netlist corresponding to the output port group when traversing to a new node which is not traversed, continues to traverse forward until traversing to a traversed node which is traversed, and creates an input port of the output port group corresponding to the sub-netlist based on the traversed node when traversing to the traversed node;

when all the input ports of the original netlist are traversed, the splitting module 301 determines the sub-netlists corresponding to all the output port groups as the sub-netlists corresponding to the original netlist.

In this optional implementation manner, further optionally, as shown in fig. 5, the multithreading synthesis apparatus may further include:

and an association module 305, for each output port group, when traversing to a traversed node and after creating an input port of the output port group corresponding to the sub-netlist based on the traversed node, determining whether the traversed node exists in the sub-netlist corresponding to the other output port group, and when the determination result is yes, creating an association relationship between the input port of the output port group corresponding to the sub-netlist and the output port of the other output port group corresponding to the sub-netlist, wherein when the traversed node exists in the sub-netlist corresponding to the other output port group, the traversed node is the output port of the other output port group corresponding to the sub-netlist.

In another alternative embodiment, the merging module 304 merges the synthesized sub-netlists corresponding to all the sub-netlists to obtain the synthesized netlist corresponding to the original netlist in the specific manner:

determining an input port and an output port of each synthesized sub netlist;

In yet another alternative embodiment, as shown in fig. 5, the multithread synthesis apparatus may further include:

a judging module 306, configured to judge whether target information corresponding to the currently parallel execution of the synthesis operation on all the sub netlists meets a predetermined synthesis end condition after the parallel synthesis module 303 starts the created all the sub threads to perform the synthesis operation on all the sub netlists in parallel to obtain a synthesized sub netlist corresponding to each sub netlist.

An adjusting module 307, configured to adjust the splitting parameter when the determining module 306 determines that the target information does not satisfy the synthesis end condition, and trigger the splitting module 301 to perform the operation of splitting the original netlist according to the determined splitting parameter to obtain at least two sub-netlists corresponding to the original netlist.

In this alternative embodiment, the target information may further optionally include a run-time and/or a synthesized netlist corresponding to the synthesis operation currently performed on all the sub-netlists in parallel.

The specific way for the determining module 306 to determine whether the target information corresponding to the currently parallel synthesis operation performed on all the sub netlists meets the predetermined synthesis end condition may be:

when the target information only comprises the running duration, judging whether the running duration is greater than the maximum running duration which is determined in advance, and when the running duration is greater than the maximum running duration, determining that the target information does not meet the comprehensive end condition which is determined in advance;

when the target information comprises the operation duration and the synthesized netlist, judging whether the synthesized netlist is matched with the original netlist, and when the synthesized netlist is judged not to be matched with the original netlist, determining that the target information does not meet a predetermined synthesis ending condition; when the synthesized netlist is matched with the original netlist, judging whether the running time is longer than the predetermined maximum running time, and when the running time is longer than the maximum running time, determining that the target information does not meet the predetermined synthesis ending condition; alternatively, the first and second electrodes may be,

when the target information comprises the operation time length and the synthesized netlist, judging whether the operation time length is greater than the predetermined maximum operation time length, and when the operation time length is greater than the maximum operation time length, determining that the target information does not meet the predetermined synthesis ending condition; and when the operation duration is not longer than the maximum operation duration, judging whether the synthesized netlist is matched with the original netlist, and when the synthesized netlist is judged not to be matched with the original netlist, determining that the target information does not meet the predetermined synthesis ending condition.

It can be seen that, by implementing the apparatus described in fig. 5, after merging the synthesized sub-netlists to obtain the synthesized netlist, it can be further intelligently determined whether the target information (operation duration and/or the synthesized sub-netlist) corresponding to the parallel synthesis operation executed this time meets the requirements, if so, the process can be directly ended, and if not, the splitting parameter is adjusted and the operations of splitting the original netlist, creating the sub-thread, parallel synthesis and merging the synthesized sub-netlists are re-performed, so that the obtained synthesized netlist is the synthesized netlist under the optimal splitting parameter, thereby providing a reference for splitting the original netlist by the FPGA synthesis tool, further optimizing the splitting parameter of the original netlist by the FPGA synthesis tool, and further improving the efficiency of multithread parallel synthesis by the FPGA synthesis tool.

In yet another alternative embodiment, as shown in fig. 5, the apparatus may further include:

a determining module 308, configured to determine total splitting data of the original netlist after the determining module 306 determines that the target information does not satisfy the synthesis end condition, where the total splitting data includes an accumulated splitting time of the original netlist or an accumulated splitting duration of the original netlist.

The determining module 306 is further configured to determine whether the total split data is smaller than a predetermined data threshold, and when the total split data is smaller than the data threshold, trigger the adjusting module 307 to perform the operation of adjusting the split parameter.

The determining module 308 is further configured to determine, when the determining module 306 determines that the total split data is not less than the data threshold, the shortest operation duration among the operation durations corresponding to the synthesis operations performed on all the split sub-netlists in parallel after the original netlist is split historically; and determining the splitting parameter corresponding to the shortest operation time as the splitting parameter for splitting the original netlist at the last time.

the counting module 309 is configured to count the running time corresponding to the synthesis operation performed on all the sub netlists obtained by splitting in parallel at present after the merging module 304 merges the synthesized sub netlists corresponding to all the sub netlists to obtain the synthesized netlist corresponding to the original netlist.

The determining module 306 may further be configured to determine whether the running time corresponding to the currently executed parallel synthesis operation on all the split sub-netlists is less than a predetermined shortest running time.

An updating module 310, configured to update the shortest running time to the running time corresponding to the current parallel operation on all the split sub-netlists when the determining module 306 determines that the running time corresponding to the current parallel operation on all the split sub-netlists performing the synthesis operation is less than the shortest running time.

The establishing module 311 is configured to establish a corresponding relationship between the updated shortest operation time and a splitting parameter used for splitting the original netlist.

Therefore, the implementation of the device described in fig. 5 can avoid unlimited splitting and parallel synthesis by setting corresponding control conditions, intelligently determine the optimal splitting parameters according to the shortest operation time principle within the control conditions, provide the optimal splitting parameters for actual synthesis, provide splitting parameter reference bases for other netlists with the same or similar scales, and further improve the operation efficiency of the FPGA synthesis tool. In addition, the shortest operation time can be dynamically updated and the corresponding relation between the shortest operation time and the corresponding splitting parameter can be established in the process of obtaining the synthesized netlist by executing the parallel synthesis operation for multiple times, so that the efficiency of determining the shortest operation time and the efficiency of determining the splitting parameter corresponding to the shortest operation time can be improved.

Example four

Referring to fig. 6, fig. 6 is a schematic structural diagram of another multithreading synthesis apparatus according to an embodiment of the present invention. As shown in fig. 6, the multithread synthesis apparatus includes:

a memory 401 storing executable program code;

a processor 402 coupled with the memory 401;

the processor 402 calls the executable program code stored in the memory 401 to execute part or all of the steps executed by the FPGA synthesis tool in the multi-thread synthesis method disclosed in the first embodiment or the second embodiment of the present invention.

EXAMPLE five

The embodiment of the invention discloses a computer storage medium, wherein computer instructions are stored in the computer storage medium and used for executing part or all of steps executed by an FPGA comprehensive tool in a multithreading comprehensive method disclosed by the first embodiment or the second embodiment of the invention when the computer instructions are called.

The above-described embodiments of the apparatus are merely illustrative, and the modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Through the above detailed description of the embodiments, those skilled in the art will clearly understand that the embodiments may be implemented by software plus a necessary general hardware platform, and may also be implemented by hardware. Based on such understanding, the above technical solutions may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, where the storage medium includes a Read-Only Memory (ROM), a Random Access Memory (RAM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), a One-time Programmable Read-Only Memory (OTPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Compact Disc-Read-Only Memory (CD-ROM), or other disk memories, CD-ROMs, or other magnetic disks, A tape memory, or any other medium readable by a computer that can be used to carry or store data.

Finally, it should be noted that: the multi-thread comprehensive method and device disclosed in the embodiments of the present invention are only preferred embodiments of the present invention, and are only used for illustrating the technical solutions of the present invention, not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for multi-threaded synthesis, the method comprising:

2. The multithreading synthesis method according to claim 1, wherein the split parameter includes a total number N of sub netlists, wherein N is less than or equal to a predetermined maximum number of threads and is an integer greater than or equal to 2;

3. The multithreading synthesis method according to claim 1, wherein the split parameter includes a total number N of sub netlists, wherein N is less than or equal to a predetermined maximum number of threads and is an integer greater than or equal to 2;

4. The multi-threaded synthesis method of claim 3, wherein the method further comprises:

5. The multithreading synthesis method of claim 4, wherein the merging of the synthesized sub-netlists corresponding to all the sub-netlists to obtain the synthesized netlist corresponding to the original netlist comprises:

determining an input port and an output port of each synthesized sub netlist;

6. A multithreaded synthesis apparatus, the apparatus comprising:

7. The multithreading synthesis apparatus of claim 6, wherein the split parameter includes a total number N of sub netlists, where N is less than or equal to a predetermined maximum number of threads and is an integer greater than or equal to 2;

8. The multithreading synthesis apparatus of claim 6, wherein the split parameter includes a total number N of sub netlists, where N is less than or equal to a predetermined maximum number of threads and is an integer greater than or equal to 2;

9. A multithreaded synthesis apparatus, the apparatus comprising:

a memory storing executable program code;

a processor coupled with the memory;

the processor calls the executable program code stored in the memory to perform the multi-threaded synthesis method of any one of claims 1-5.

10. A computer storage medium storing computer instructions which, when invoked, perform a multi-threaded synthesis method as claimed in any one of claims 1 to 5.