CN112580276A - HCI degradation model of MOS transistor-VCO circuit performance using knowledge-based neural network - Google Patents

Abstract

The invention discloses an HCI degradation model of the performance of a circuit from an MOS tube to a VCO by using a knowledge-based neural network, which can predict the degradation condition of the performance parameters of the VCO according to the degradation condition of the performance parameters of the tested MOS tube. The process is mainly divided into three steps: firstly, performing an HCI degradation experiment on an MOS tube and a VCO circuit used for modeling to obtain HCI degradation conditions of the MOS tube and the VCO circuit under different direct-current stresses; secondly, establishing a knowledge-based neural network structure as an initial model; and thirdly, taking the test result as training and test data, and continuously adjusting and optimizing the model structure through training a neural network to obtain an optimal model.

Description

HCI degradation model of MOS transistor-VCO circuit performance using knowledge-based neural network

Technical Field

The invention relates to the technical field of device reliability and circuit reliability, in particular to an HCI degradation model from MOS (metal oxide semiconductor) transistors to VCO (voltage controlled oscillator) circuit performance by using a knowledge-based neural network.

Background

Voltage Controlled Oscillators (VCOs) have become an important component of radio frequency circuits as a tunable signal source. In order to integrate with a mainstream standard CMOS process that is often used for RF circuit design, a VCO in a CMOS process having excellent performance is designed as a hot issue for RF circuit design, and an amplification function in the VCO circuit in the CMOS process is mainly realized by a MOS transistor. On one hand, however, as the CMOS process level is continuously improved, the channel length of the device is continuously shortened, the gate oxide layer is continuously thinned, and the reliability problem of the MOS transistor, especially the hot carrier effect, becomes an important problem that affects the performance and the service life of the MOS transistor; on the other hand, the working frequency band of the circuit is continuously improved, and the working voltage applied to the device is not reduced along with the reduction of parameters such as the length, the width, the thickness of gate oxide and the like of a channel, so that the hot carrier effect (HCI) 1 of the MOS transistor is further enhanced, and the performance of the whole VCO circuit is influenced. Therefore, it is important to research the reliability problem of the MOS tube and the VCO circuit by modeling. The knowledge-based neural network [2] is widely applied to the field of device and circuit modeling as an important Computer-Aided Design (CAD) technology [3], can help people to quickly establish a model with high precision and good performance, and has guiding significance for subsequent Design work.

Conventional circuit reliability studies often separate devices from the circuit. In order to carry out systematic research by linking the reliability problems of devices and circuits and simplify the modeling process, the invention provides an HCI degradation model of circuit performance parameters from an MOS tube to a VCO by using a knowledge-based neural network.

Disclosure of Invention

The invention discloses an HCI degradation model from MOS tube to VCO circuit performance by using knowledge-based neural network, which mainly aims at the following three points: 1. researching the degradation condition that the performance parameters of the MOS tube and the VCO circuit are influenced by HCI under direct current stress; 2. under different direct current stresses, fitting the corresponding relation between the HCI degradation condition of the tested MOS tube performance parameters and the HCI degradation condition of the tested VCO circuit performance parameters, predicting the HCI degradation condition of the VCO circuit performance parameters according to the HCI degradation condition of the MOS tube performance parameters, reducing a data set used for modeling, and simplifying the testing process; 3. and modeling by using a knowledge-based neural network, further reducing a data set used for modeling according to the guidance of prior knowledge, and improving the modeling speed and the model precision.

To achieve the object of the present invention, the present invention provides an HCI degradation model of circuit performance from MOS transistors to VCO using knowledge-based neural networks,

the structure of the model is specifically as follows:

(1) and an input layer: HCI degradation measurement results comprising stress applied to the MOS tube and corresponding MOS tube performance parameters;

(2) prior knowledge: taking an expression expressing the relation between the performance parameters of the MOS transistor and the performance parameters of the VCO circuit as prior knowledge, and analyzing according to specific circuits;

(3) and an accurate model: taking HCI degradation measurement results of the corresponding VCO performance parameters after stress is applied as an accurate model;

(4) and an output layer: the fitting result of HCI degradation condition of the VCO circuit performance parameters after stress is applied is the final output of the whole model;

(5) the multi-layer perceptron (MLP), namely a neural network structure, makes the final output of the whole model approach the expected output by continuously adjusting the internal structure of the MLP, namely the number of hidden layers, the number of hidden layer neurons and each connection weight, which is the working mechanism of the neural network;

and training and testing the model, and selecting the model with higher testing accuracy as a final model.

Compared with the prior art, the invention has the advantages that,

firstly, different from existing models such as complex formulas, the method can quickly establish a relatively accurate model only by determining input and output data sets;

secondly, the HCI degradation condition of the performance parameters of the VCO circuit can be predicted according to the HCI degradation condition of the performance parameters of the MOS transistor, so that a data set is reduced, a test process is simplified, and time cost is reduced;

and thirdly, the prior knowledge in the knowledge-based neural network has guiding significance on the formation of a fitting relation in the training process, so that the modeling speed is higher, and the final output of the model is more accurate.

Drawings

FIG. 1 is a schematic diagram of a model of the present invention

FIG. 2 is a flow chart of the modeling of the present invention;

FIG. 3 is an equivalent circuit diagram of a differential cross-coupled CMOS VCO to which the present invention relates;

figure 4 is a circuit diagram of a four-stage ring VCO according to the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and specific examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when used in this specification the singular forms "a", "an" and/or "the" include "specify the presence of stated features, steps, operations, elements, or modules, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

As shown in figures 1 and 2 of the drawings,

the method uses the knowledge-based neural network to model the HCI degradation condition of the performance of the MOS tube and the VCO circuit under the direct-current stress, and the model can predict the degradation condition of the performance parameters of the VCO circuit according to the degradation condition of the performance parameters of the tested MOS tube. The process is mainly divided into three steps: firstly, performing an HCI degradation experiment on an MOS tube and a VCO circuit used for modeling to obtain HCI degradation conditions of the MOS tube and the VCO circuit under different direct-current stresses; secondly, establishing a knowledge-based neural network structure as an initial model; and thirdly, taking the test result as training and test data, and continuously adjusting and optimizing the model structure through training a neural network to obtain an optimal model.

And respectively carrying out HCI degradation experiments on the MOS tube and the VCO circuit used for modeling, measuring HCI degradation conditions of performance parameters of the MOS tube and the VCO circuit under different direct-current stresses, and carrying out data preprocessing. Important performance parameters of the MOS tube comprise an Id-Vd curve, transconductance, output conductance, threshold voltage, S parameters, noise coefficient, maximum working frequency, maximum oscillation frequency, mobility and the like. Important performance parameters of a VCO circuit include dc current, gain, frequency, phase noise, power consumption, output power, etc. The scheme for modeling is shown in fig. 1.

The structure of the model is specifically as follows:

(1) and an input layer: HCI degradation measurement results comprising stress applied to the MOS tube and corresponding MOS tube performance parameters;

(2) prior knowledge: may be an already existing model, which may be inaccurate. Taking an expression expressing the relation between the performance parameters of the MOS transistor and the performance parameters of the VCO circuit as prior knowledge, and analyzing according to specific circuits;

taking the differential cross-coupled CMOS VCO shown in fig. 3 as an example, there are the following expressions:

phase noise:

wherein, the gamma of the long channel device is 2/3

Wherein, suppose R_out≈R_L

Taking the four-stage ring VCO shown in fig. 4 as an example, the following expression is provided:

(3) and an accurate model: an accurate model is a relatively accurate data or result. In the invention, HCI degradation measurement results of corresponding VCO performance parameters after stress is applied are used as accurate models. The output of the exact model can be taken as the desired output of the entire model.

(4) And an output layer: the fitting result of HCI degradation condition of the VCO circuit performance parameters after stress is applied is the final output of the whole model;

(5) the multi-layer perceptron (MLP), namely a neural network structure, makes the final output of the whole model approach the expected output by continuously adjusting the internal structure of the MLP, namely the number of hidden layers, the number of hidden layer neurons and each connection weight, which is the working mechanism of the neural network;

and training and testing the model, and selecting the model with higher testing accuracy as a final model.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (1)

1. A HCI degradation model from MOS transistor to VCO circuit performance using knowledge-based neural networks, characterized by:

the structure of the model is specifically as follows:

(1) and an input layer: HCI degradation measurement results comprising stress applied to the MOS tube and corresponding MOS tube performance parameters;

(2) prior knowledge: taking an expression expressing the relation between the performance parameters of the MOS transistor and the performance parameters of the VCO circuit as prior knowledge, and analyzing according to specific circuits;

(3) and an accurate model: taking HCI degradation measurement results of the corresponding VCO performance parameters after stress is applied as an accurate model;

(4) and an output layer: the fitting result of HCI degradation condition of the VCO circuit performance parameters after stress is applied is the final output of the whole model;

(5) the multi-layer perceptron (MLP), namely a neural network structure, makes the final output of the whole model approach the expected output by continuously adjusting the internal structure of the MLP, namely the number of hidden layers, the number of hidden layer neurons and each connection weight, which is the working mechanism of the neural network;

and training and testing the model, and selecting the model with higher testing accuracy as a final model.

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